forked from OSchip/llvm-project
AMDGPU/GlobalISel: Fix assert on load from constant address
llvm-svn: 371006
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@ -1137,13 +1137,13 @@ void AMDGPUInstructionSelector::getAddrModeInfo(const MachineInstr &Load,
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GEPInfo GEPInfo(*PtrMI);
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GEPInfo GEPInfo(*PtrMI);
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for (unsigned i = 1, e = 3; i < e; ++i) {
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for (unsigned i = 1; i != 3; ++i) {
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const MachineOperand &GEPOp = PtrMI->getOperand(i);
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const MachineOperand &GEPOp = PtrMI->getOperand(i);
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const MachineInstr *OpDef = MRI.getUniqueVRegDef(GEPOp.getReg());
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const MachineInstr *OpDef = MRI.getUniqueVRegDef(GEPOp.getReg());
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assert(OpDef);
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assert(OpDef);
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if (isConstant(*OpDef)) {
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if (i == 2 && isConstant(*OpDef)) {
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// FIXME: Is it possible to have multiple Imm parts? Maybe if we
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// TODO: Could handle constant base + variable offset, but a combine
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// are lacking other optimizations.
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// probably should have commuted it.
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assert(GEPInfo.Imm == 0);
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assert(GEPInfo.Imm == 0);
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GEPInfo.Imm = OpDef->getOperand(1).getCImm()->getSExtValue();
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GEPInfo.Imm = OpDef->getOperand(1).getCImm()->getSExtValue();
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continue;
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continue;
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@ -5,6 +5,7 @@
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--- |
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--- |
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define amdgpu_kernel void @smrd_imm(i32 addrspace(4)* %const0) { ret void }
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define amdgpu_kernel void @smrd_imm(i32 addrspace(4)* %const0) { ret void }
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define amdgpu_kernel void @smrd_wide() { ret void }
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define amdgpu_kernel void @smrd_wide() { ret void }
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define amdgpu_kernel void @constant_address_positive() { ret void }
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...
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...
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---
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---
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@ -185,3 +186,29 @@ body: |
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%5:sgpr(<16 x s32>) = G_LOAD %1 :: (load 64, addrspace 1)
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%5:sgpr(<16 x s32>) = G_LOAD %1 :: (load 64, addrspace 1)
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$sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 = COPY %5
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$sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 = COPY %5
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...
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...
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# Test a load of an offset from a constant base address
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# GCN-LABEL: name: constant_address_positive{{$}}
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# GCN: %4:sreg_32_xm0 = S_MOV_B32 44
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# GCN: %5:sreg_32_xm0 = S_MOV_B32 0
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# GCN: %0:sreg_64 = REG_SEQUENCE %4, %subreg.sub0, %5, %subreg.sub1
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# VI: %3:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %0, 64, 0, 0 :: (dereferenceable invariant load 4, addrspace 4)
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# SICI: %3:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %0, 16, 0, 0 :: (dereferenceable invariant load 4, addrspace 4)
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---
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name: constant_address_positive
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1, $vgpr2_vgpr3
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%0:sgpr(p4) = G_CONSTANT i64 44
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%1:sgpr(s64) = G_CONSTANT i64 64
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%2:sgpr(p4) = G_GEP %0, %1
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%3:sgpr(s32) = G_LOAD %2 :: (dereferenceable invariant load 4, align 4, addrspace 4)
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S_ENDPGM 0, implicit %3
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...
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