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AMDGPU/GlobalISel: Fix assert on load from constant address 

llvm-svn: 371006
This commit is contained in:
Matt Arsenault 2019-09-05 02:20:25 +00:00
parent 6d3ea2d9b6
commit d51a3746d0
2 changed files with 31 additions and 4 deletions
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8
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
View File

@ -1137,13 +1137,13 @@ void AMDGPUInstructionSelector::getAddrModeInfo(const MachineInstr &Load,
GEPInfo GEPInfo(*PtrMI);
for (unsigned i = 1, e = 3; i < e; ++i) {
for (unsigned i = 1; i != 3; ++i) {
const MachineOperand &GEPOp = PtrMI->getOperand(i);
const MachineInstr *OpDef = MRI.getUniqueVRegDef(GEPOp.getReg());
assert(OpDef);
if (isConstant(*OpDef)) {
// FIXME: Is it possible to have multiple Imm parts? Maybe if we
// are lacking other optimizations.
if (i == 2 && isConstant(*OpDef)) {
// TODO: Could handle constant base + variable offset, but a combine
// probably should have commuted it.
assert(GEPInfo.Imm == 0);
GEPInfo.Imm = OpDef->getOperand(1).getCImm()->getSExtValue();
continue;

27
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-smrd.mir
View File

@ -5,6 +5,7 @@
--- |
define amdgpu_kernel void @smrd_imm(i32 addrspace(4)* %const0) { ret void }
define amdgpu_kernel void @smrd_wide() { ret void }
define amdgpu_kernel void @constant_address_positive() { ret void }
...
---
@ -185,3 +186,29 @@ body: |
%5:sgpr(<16 x s32>) = G_LOAD %1 :: (load 64, addrspace 1)
$sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15 = COPY %5
...
# Test a load of an offset from a constant base address
# GCN-LABEL: name: constant_address_positive{{$}}
# GCN: %4:sreg_32_xm0 = S_MOV_B32 44
# GCN: %5:sreg_32_xm0 = S_MOV_B32 0
# GCN: %0:sreg_64 = REG_SEQUENCE %4, %subreg.sub0, %5, %subreg.sub1
# VI: %3:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %0, 64, 0, 0 :: (dereferenceable invariant load 4, addrspace 4)
# SICI: %3:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %0, 16, 0, 0 :: (dereferenceable invariant load 4, addrspace 4)
---
name: constant_address_positive
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $sgpr0_sgpr1, $vgpr2_vgpr3
%0:sgpr(p4) = G_CONSTANT i64 44
%1:sgpr(s64) = G_CONSTANT i64 64
%2:sgpr(p4) = G_GEP %0, %1
%3:sgpr(s32) = G_LOAD %2 :: (dereferenceable invariant load 4, align 4, addrspace 4)
S_ENDPGM 0, implicit %3
...