forked from OSchip/llvm-project
[SVE][LoopVectorize] Add masked load/store and gather/scatter support for SVE
This patch updates IRBuilder::CreateMaskedGather/Scatter to work with ScalableVectorType and adds isLegalMaskedGather/Scatter functions to AArch64TargetTransformInfo. In addition I've fixed up isLegalMaskedLoad/Store to return true for supported scalar types, since this is what the vectorizer asks for. In LoopVectorize.cpp I've changed LoopVectorizationCostModel::getInterleaveGroupCost to return an invalid cost for scalable vectors, since currently this relies upon using shuffle vector for reversing vectors. In addition, in LoopVectorizationCostModel::setCostBasedWideningDecision I have assumed that the cost of scalarising memory ops is infinitely expensive. I have added some simple masked load/store and gather/scatter tests, including cases where we use gathers and scatters for conditional invariant loads and stores. Differential Revision: https://reviews.llvm.org/D95350
This commit is contained in:
David Sherwood
parent
679ef22f2e
commit
d4d4ceeb8f
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@ -522,14 +522,14 @@ CallInst *IRBuilderBase::CreateMaskedIntrinsic(Intrinsic::ID Id,
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CallInst *IRBuilderBase::CreateMaskedGather(Value *Ptrs, Align Alignment,
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Value *Mask, Value *PassThru,
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const Twine &Name) {
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auto *PtrsTy = cast<FixedVectorType>(Ptrs->getType());
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auto *PtrsTy = cast<VectorType>(Ptrs->getType());
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auto *PtrTy = cast<PointerType>(PtrsTy->getElementType());
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unsigned NumElts = PtrsTy->getNumElements();
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auto *DataTy = FixedVectorType::get(PtrTy->getElementType(), NumElts);
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ElementCount NumElts = PtrsTy->getElementCount();
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auto *DataTy = VectorType::get(PtrTy->getElementType(), NumElts);
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if (!Mask)
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Mask = Constant::getAllOnesValue(
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FixedVectorType::get(Type::getInt1Ty(Context), NumElts));
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VectorType::get(Type::getInt1Ty(Context), NumElts));
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if (!PassThru)
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PassThru = UndefValue::get(DataTy);
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@ -552,20 +552,20 @@ CallInst *IRBuilderBase::CreateMaskedGather(Value *Ptrs, Align Alignment,
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/// be accessed in memory
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CallInst *IRBuilderBase::CreateMaskedScatter(Value *Data, Value *Ptrs,
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Align Alignment, Value *Mask) {
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auto *PtrsTy = cast<FixedVectorType>(Ptrs->getType());
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auto *DataTy = cast<FixedVectorType>(Data->getType());
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unsigned NumElts = PtrsTy->getNumElements();
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auto *PtrsTy = cast<VectorType>(Ptrs->getType());
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auto *DataTy = cast<VectorType>(Data->getType());
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ElementCount NumElts = PtrsTy->getElementCount();
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#ifndef NDEBUG
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auto PtrTy = cast<PointerType>(PtrsTy->getElementType());
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assert(NumElts == DataTy->getNumElements() &&
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assert(NumElts == DataTy->getElementCount() &&
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PtrTy->getElementType() == DataTy->getElementType() &&
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"Incompatible pointer and data types");
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#endif
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if (!Mask)
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Mask = Constant::getAllOnesValue(
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FixedVectorType::get(Type::getInt1Ty(Context), NumElts));
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VectorType::get(Type::getInt1Ty(Context), NumElts));
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Type *OverloadedTypes[] = {DataTy, PtrsTy};
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Value *Ops[] = {Data, Ptrs, getInt32(Alignment.value()), Mask};
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@ -186,11 +186,7 @@ public:
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bool getTgtMemIntrinsic(IntrinsicInst *Inst, MemIntrinsicInfo &Info);
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bool isLegalMaskedLoadStore(Type *DataType, Align Alignment) {
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if (!isa<ScalableVectorType>(DataType) || !ST->hasSVE())
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return false;
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Type *Ty = cast<ScalableVectorType>(DataType)->getElementType();
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bool isLegalScalarTypeForSVEMaskedMemOp(Type *Ty) const {
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if (Ty->isPointerTy())
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return true;
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@ -205,6 +201,13 @@ public:
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return false;
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}
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bool isLegalMaskedLoadStore(Type *DataType, Align Alignment) {
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if (isa<FixedVectorType>(DataType) || !ST->hasSVE())
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return false;
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return isLegalScalarTypeForSVEMaskedMemOp(DataType->getScalarType());
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}
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bool isLegalMaskedLoad(Type *DataType, Align Alignment) {
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return isLegalMaskedLoadStore(DataType, Alignment);
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}
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@ -213,6 +216,20 @@ public:
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return isLegalMaskedLoadStore(DataType, Alignment);
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}
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bool isLegalMaskedGatherScatter(Type *DataType) const {
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if (isa<FixedVectorType>(DataType) || !ST->hasSVE())
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return false;
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return isLegalScalarTypeForSVEMaskedMemOp(DataType->getScalarType());
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}
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bool isLegalMaskedGather(Type *DataType, Align Alignment) const {
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return isLegalMaskedGatherScatter(DataType);
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}
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bool isLegalMaskedScatter(Type *DataType, Align Alignment) const {
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return isLegalMaskedGatherScatter(DataType);
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}
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bool isLegalNTStore(Type *DataType, Align Alignment) {
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// NOTE: The logic below is mostly geared towards LV, which calls it with
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// vectors with 2 elements. We might want to improve that, if other
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@ -6792,6 +6792,11 @@ LoopVectorizationCostModel::getGatherScatterCost(Instruction *I,
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InstructionCost
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LoopVectorizationCostModel::getInterleaveGroupCost(Instruction *I,
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ElementCount VF) {
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// TODO: Once we have support for interleaving with scalable vectors
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// we can calculate the cost properly here.
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if (VF.isScalable())
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return InstructionCost::getInvalid();
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Type *ValTy = getMemInstValueType(I);
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auto *VectorTy = cast<VectorType>(ToVectorTy(ValTy, VF));
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unsigned AS = getLoadStoreAddressSpace(I);
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@ -6800,7 +6805,6 @@ LoopVectorizationCostModel::getInterleaveGroupCost(Instruction *I,
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assert(Group && "Fail to get an interleaved access group.");
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unsigned InterleaveFactor = Group->getFactor();
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assert(!VF.isScalable() && "scalable vectors not yet supported.");
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auto *WideVecTy = VectorType::get(ValTy, VF * InterleaveFactor);
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// Holds the indices of existing members in an interleaved load group.
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@ -7064,7 +7068,7 @@ void LoopVectorizationCostModel::setCostBasedWideningDecision(ElementCount VF) {
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}
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// Choose between Interleaving, Gather/Scatter or Scalarization.
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InstructionCost InterleaveCost = std::numeric_limits<int>::max();
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InstructionCost InterleaveCost = InstructionCost::getInvalid();
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unsigned NumAccesses = 1;
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if (isAccessInterleaved(&I)) {
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auto Group = getInterleavedAccessGroup(&I);
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@ -7082,10 +7086,11 @@ void LoopVectorizationCostModel::setCostBasedWideningDecision(ElementCount VF) {
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InstructionCost GatherScatterCost =
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isLegalGatherOrScatter(&I)
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? getGatherScatterCost(&I, VF) * NumAccesses
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: std::numeric_limits<int>::max();
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: InstructionCost::getInvalid();
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InstructionCost ScalarizationCost =
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getMemInstScalarizationCost(&I, VF) * NumAccesses;
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!VF.isScalable() ? getMemInstScalarizationCost(&I, VF) * NumAccesses
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: InstructionCost::getInvalid();
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// Choose better solution for the current VF,
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// write down this decision and use it during vectorization.
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@ -7099,6 +7104,8 @@ void LoopVectorizationCostModel::setCostBasedWideningDecision(ElementCount VF) {
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Decision = CM_GatherScatter;
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Cost = GatherScatterCost;
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} else {
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assert(!VF.isScalable() &&
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"We cannot yet scalarise for scalable vectors");
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Decision = CM_Scalarize;
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Cost = ScalarizationCost;
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}
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@ -7448,8 +7455,12 @@ LoopVectorizationCostModel::getInstructionCost(Instruction *I, ElementCount VF,
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}
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}
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assert(!VF.isScalable() && "VF is assumed to be non scalable");
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unsigned N = isScalarAfterVectorization(I, VF) ? VF.getKnownMinValue() : 1;
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unsigned N;
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if (isScalarAfterVectorization(I, VF)) {
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assert(!VF.isScalable() && "VF is assumed to be non scalable");
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N = VF.getKnownMinValue();
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} else
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N = 1;
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return N *
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TTI.getCastInstrCost(Opcode, VectorTy, SrcVecTy, CCH, CostKind, I);
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}
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@ -0,0 +1,130 @@
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; RUN: opt -loop-vectorize -dce -instcombine -mtriple aarch64-linux-gnu -mattr=+sve -S %s -o - | FileCheck %s
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define void @gather_nxv4i32_ind64(float* noalias nocapture readonly %a, i64* noalias nocapture readonly %b, float* noalias nocapture %c, i64 %n) {
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; CHECK-LABEL: @gather_nxv4i32_ind64
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; CHECK: vector.body:
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; CHECK: %[[IND:.*]] = load <vscale x 4 x i64>, <vscale x 4 x i64>*
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; CHECK: %[[PTRS:.*]] = getelementptr inbounds float, float* %a, <vscale x 4 x i64> %[[IND]]
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; CHECK: %[[GLOAD:.*]] = call <vscale x 4 x float> @llvm.masked.gather.nxv4f32.nxv4p0f32(<vscale x 4 x float*> %[[PTRS]]
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; CHECK: store <vscale x 4 x float> %[[GLOAD]], <vscale x 4 x float>*
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entry:
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br label %for.body
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for.body: ; preds = %entry, %for.body
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%indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
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%arrayidx = getelementptr inbounds i64, i64* %b, i64 %indvars.iv
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%0 = load i64, i64* %arrayidx, align 8
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%arrayidx3 = getelementptr inbounds float, float* %a, i64 %0
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%1 = load float, float* %arrayidx3, align 4
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%arrayidx5 = getelementptr inbounds float, float* %c, i64 %indvars.iv
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store float %1, float* %arrayidx5, align 4
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%exitcond.not = icmp eq i64 %indvars.iv.next, %n
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br i1 %exitcond.not, label %for.cond.cleanup, label %for.body, !llvm.loop !0
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for.cond.cleanup: ; preds = %for.cond.cleanup.loopexit, %entry
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ret void
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}
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; NOTE: I deliberately chose '%b' as an array of i32 indices, since the
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; additional 'sext' in the for.body loop exposes additional code paths
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; during vectorisation.
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define void @scatter_nxv4i32_ind32(float* noalias nocapture %a, i32* noalias nocapture readonly %b, float* noalias nocapture readonly %c, i64 %n) {
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; CHECK-LABEL: @scatter_nxv4i32_ind32
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; CHECK: vector.body:
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; CHECK: %[[VALS:.*]] = load <vscale x 4 x float>
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; CHECK: %[[IND:.*]] = load <vscale x 4 x i32>, <vscale x 4 x i32>* %7, align 4
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; CHECK: %[[EXTIND:.*]] = sext <vscale x 4 x i32> %[[IND]] to <vscale x 4 x i64>
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; CHECK: %[[PTRS:.*]] = getelementptr inbounds float, float* %a, <vscale x 4 x i64> %[[EXTIND]]
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; CHECK: call void @llvm.masked.scatter.nxv4f32.nxv4p0f32(<vscale x 4 x float> %[[VALS]], <vscale x 4 x float*> %[[PTRS]]
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entry:
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br label %for.body
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for.body: ; preds = %entry, %for.body
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%indvars.iv = phi i64 [ %indvars.iv.next, %for.body ], [ 0, %entry ]
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%arrayidx = getelementptr inbounds float, float* %c, i64 %indvars.iv
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%0 = load float, float* %arrayidx, align 4
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%arrayidx3 = getelementptr inbounds i32, i32* %b, i64 %indvars.iv
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%1 = load i32, i32* %arrayidx3, align 4
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%idxprom4 = sext i32 %1 to i64
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%arrayidx5 = getelementptr inbounds float, float* %a, i64 %idxprom4
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store float %0, float* %arrayidx5, align 4
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%exitcond.not = icmp eq i64 %indvars.iv.next, %n
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br i1 %exitcond.not, label %for.cond.cleanup, label %for.body, !llvm.loop !0
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for.cond.cleanup: ; preds = %for.body, %entry
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ret void
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}
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define void @scatter_inv_nxv4i32(i32* noalias nocapture %inv, i32* noalias nocapture readonly %b, i64 %n) {
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; CHECK-LABEL: @scatter_inv_nxv4i32
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; CHECK: vector.ph:
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; CHECK: %[[INS:.*]] = insertelement <vscale x 4 x i32*> poison, i32* %inv, i32 0
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; CHECK: %[[PTRSPLAT:.*]] = shufflevector <vscale x 4 x i32*> %[[INS]], <vscale x 4 x i32*> poison, <vscale x 4 x i32> zeroinitializer
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; CHECK: vector.body:
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; CHECK: %[[VALS:.*]] = load <vscale x 4 x i32>, <vscale x 4 x i32>* %5, align 4
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; CHECK: %[[MASK:.*]] = icmp ne <vscale x 4 x i32> %[[VALS]],
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; CHECK: call void @llvm.masked.scatter.nxv4i32.nxv4p0i32({{.*}}, <vscale x 4 x i32*> %[[PTRSPLAT]], i32 4, <vscale x 4 x i1> %[[MASK]])
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entry:
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br label %for.body
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for.body: ; preds = %entry, %for.inc
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%indvars.iv = phi i64 [ %indvars.iv.next, %for.inc ], [ 0, %entry ]
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%arrayidx = getelementptr inbounds i32, i32* %b, i64 %indvars.iv
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%0 = load i32, i32* %arrayidx, align 4
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%tobool.not = icmp eq i32 %0, 0
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br i1 %tobool.not, label %for.inc, label %if.then
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if.then: ; preds = %for.body
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store i32 3, i32* %inv, align 4
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br label %for.inc
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for.inc: ; preds = %for.body, %if.then
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%exitcond.not = icmp eq i64 %indvars.iv.next, %n
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br i1 %exitcond.not, label %for.cond.cleanup, label %for.body, !llvm.loop !0
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for.cond.cleanup: ; preds = %for.cond.cleanup.loopexit, %entry
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ret void
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}
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define void @gather_inv_nxv4i32(i32* noalias nocapture %a, i32* noalias nocapture readonly %inv, i64 %n) {
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; CHECK-LABEL: @gather_inv_nxv4i32
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; CHECK: vector.ph:
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; CHECK: %[[INS:.*]] = insertelement <vscale x 4 x i32*> poison, i32* %inv, i32 0
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; CHECK: %[[PTRSPLAT:.*]] = shufflevector <vscale x 4 x i32*> %[[INS]], <vscale x 4 x i32*> poison, <vscale x 4 x i32> zeroinitializer
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; CHECK: vector.body:
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; CHECK: %[[VALS:.*]] = load <vscale x 4 x i32>, <vscale x 4 x i32>* %5, align 4
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; CHECK: %[[MASK:.*]] = icmp sgt <vscale x 4 x i32> %[[VALS]],
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; CHECK: %{{.*}} = call <vscale x 4 x i32> @llvm.masked.gather.nxv4i32.nxv4p0i32(<vscale x 4 x i32*> %[[PTRSPLAT]], i32 4, <vscale x 4 x i1> %[[MASK]]
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entry:
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br label %for.body
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for.body: ; preds = %entry, %for.inc
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%indvars.iv = phi i64 [ %indvars.iv.next, %for.inc ], [ 0, %entry ]
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%arrayidx = getelementptr inbounds i32, i32* %a, i64 %indvars.iv
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%0 = load i32, i32* %arrayidx, align 4
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%cmp2 = icmp sgt i32 %0, 3
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br i1 %cmp2, label %if.then, label %for.inc
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if.then: ; preds = %for.body
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%1 = load i32, i32* %inv, align 4
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store i32 %1, i32* %arrayidx, align 4
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br label %for.inc
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for.inc: ; preds = %for.body, %if.then
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%exitcond.not = icmp eq i64 %indvars.iv.next, %n
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br i1 %exitcond.not, label %for.cond.cleanup, label %for.body, !llvm.loop !0
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for.cond.cleanup: ; preds = %for.inc, %entry
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ret void
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}
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!0 = distinct !{!0, !1, !2, !3, !4, !5}
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!1 = !{!"llvm.loop.mustprogress"}
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!2 = !{!"llvm.loop.vectorize.width", i32 4}
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!3 = !{!"llvm.loop.vectorize.scalable.enable", i1 true}
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!4 = !{!"llvm.loop.interleave.count", i32 1}
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!5 = !{!"llvm.loop.vectorize.enable", i1 true}
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@ -0,0 +1,82 @@
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; RUN: opt -loop-vectorize -dce -instcombine -mtriple aarch64-linux-gnu -mattr=+sve -S %s -o - | FileCheck %s
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define void @mloadstore_f32(float* noalias nocapture %a, float* noalias nocapture readonly %b, i64 %n) {
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; CHECK-LABEL: @mloadstore_f32
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; CHECK: vector.body:
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; CHECK: %[[LOAD1:.*]] = load <vscale x 4 x float>, <vscale x 4 x float>*
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; CHECK-NEXT: %[[MASK:.*]] = fcmp ogt <vscale x 4 x float> %[[LOAD1]],
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; CHECK-NEXT: %[[GEPA:.*]] = getelementptr inbounds float, float* %a,
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; CHECK-NEXT: %[[MLOAD_PTRS:.*]] = bitcast float* %[[GEPA]] to <vscale x 4 x float>*
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; CHECK-NEXT: %[[LOAD2:.*]] = call <vscale x 4 x float> @llvm.masked.load.nxv4f32.p0nxv4f32(<vscale x 4 x float>* %[[MLOAD_PTRS]], i32 4, <vscale x 4 x i1> %[[MASK]]
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; CHECK-NEXT: %[[FADD:.*]] = fadd <vscale x 4 x float> %[[LOAD1]], %[[LOAD2]]
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; CHECK-NEXT: %[[MSTORE_PTRS:.*]] = bitcast float* %[[GEPA]] to <vscale x 4 x float>*
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; CHECK-NEXT: call void @llvm.masked.store.nxv4f32.p0nxv4f32(<vscale x 4 x float> %[[FADD]], <vscale x 4 x float>* %[[MSTORE_PTRS]], i32 4, <vscale x 4 x i1> %[[MASK]])
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entry:
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br label %for.body
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for.body: ; preds = %entry, %for.inc
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%i.011 = phi i64 [ %inc, %for.inc ], [ 0, %entry ]
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%arrayidx = getelementptr inbounds float, float* %b, i64 %i.011
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%0 = load float, float* %arrayidx, align 4
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%cmp1 = fcmp ogt float %0, 0.000000e+00
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br i1 %cmp1, label %if.then, label %for.inc
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if.then: ; preds = %for.body
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%arrayidx3 = getelementptr inbounds float, float* %a, i64 %i.011
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%1 = load float, float* %arrayidx3, align 4
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%add = fadd float %0, %1
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store float %add, float* %arrayidx3, align 4
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br label %for.inc
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for.inc: ; preds = %for.body, %if.then
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%inc = add nuw nsw i64 %i.011, 1
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%exitcond.not = icmp eq i64 %inc, %n
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br i1 %exitcond.not, label %exit, label %for.body, !llvm.loop !0
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exit: ; preds = %for.inc
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ret void
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}
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||||
|
||||
define void @mloadstore_i32(i32* noalias nocapture %a, i32* noalias nocapture readonly %b, i64 %n) {
|
||||
; CHECK-LABEL: @mloadstore_i32
|
||||
; CHECK: vector.body:
|
||||
; CHECK: %[[LOAD1:.*]] = load <vscale x 4 x i32>, <vscale x 4 x i32>*
|
||||
; CHECK-NEXT: %[[MASK:.*]] = icmp ne <vscale x 4 x i32> %[[LOAD1]],
|
||||
; CHECK-NEXT: %[[GEPA:.*]] = getelementptr inbounds i32, i32* %a,
|
||||
; CHECK-NEXT: %[[MLOAD_PTRS:.*]] = bitcast i32* %[[GEPA]] to <vscale x 4 x i32>*
|
||||
; CHECK-NEXT: %[[LOAD2:.*]] = call <vscale x 4 x i32> @llvm.masked.load.nxv4i32.p0nxv4i32(<vscale x 4 x i32>* %[[MLOAD_PTRS]], i32 4, <vscale x 4 x i1> %[[MASK]]
|
||||
; CHECK-NEXT: %[[FADD:.*]] = add <vscale x 4 x i32> %[[LOAD1]], %[[LOAD2]]
|
||||
; CHECK-NEXT: %[[MSTORE_PTRS:.*]] = bitcast i32* %[[GEPA]] to <vscale x 4 x i32>*
|
||||
; CHECK-NEXT: call void @llvm.masked.store.nxv4i32.p0nxv4i32(<vscale x 4 x i32> %[[FADD]], <vscale x 4 x i32>* %[[MSTORE_PTRS]], i32 4, <vscale x 4 x i1> %[[MASK]])
|
||||
entry:
|
||||
br label %for.body
|
||||
|
||||
for.body: ; preds = %entry, %for.inc
|
||||
%i.011 = phi i64 [ %inc, %for.inc ], [ 0, %entry ]
|
||||
%arrayidx = getelementptr inbounds i32, i32* %b, i64 %i.011
|
||||
%0 = load i32, i32* %arrayidx, align 4
|
||||
%cmp1 = icmp ne i32 %0, 0
|
||||
br i1 %cmp1, label %if.then, label %for.inc
|
||||
|
||||
if.then: ; preds = %for.body
|
||||
%arrayidx3 = getelementptr inbounds i32, i32* %a, i64 %i.011
|
||||
%1 = load i32, i32* %arrayidx3, align 4
|
||||
%add = add i32 %0, %1
|
||||
store i32 %add, i32* %arrayidx3, align 4
|
||||
br label %for.inc
|
||||
|
||||
for.inc: ; preds = %for.body, %if.then
|
||||
%inc = add nuw nsw i64 %i.011, 1
|
||||
%exitcond.not = icmp eq i64 %inc, %n
|
||||
br i1 %exitcond.not, label %exit, label %for.body, !llvm.loop !0
|
||||
|
||||
exit: ; preds = %for.inc
|
||||
ret void
|
||||
}
|
||||
|
||||
!0 = distinct !{!0, !1, !2, !3, !4, !5}
|
||||
!1 = !{!"llvm.loop.mustprogress"}
|
||||
!2 = !{!"llvm.loop.vectorize.width", i32 4}
|
||||
!3 = !{!"llvm.loop.vectorize.scalable.enable", i1 true}
|
||||
!4 = !{!"llvm.loop.interleave.count", i32 1}
|
||||
!5 = !{!"llvm.loop.vectorize.enable", i1 true}
|
||||
Loading…
Reference in New Issue