forked from OSchip/llvm-project
[SelectionDAG] Improve known bits support for CTPOP.
This is based on the same concept from ValueTracking's version of computeKnownBits. llvm-svn: 302110
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@ -2376,7 +2376,10 @@ void SelectionDAG::computeKnownBits(SDValue Op, KnownBits &Known,
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break;
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}
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case ISD::CTPOP: {
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Known.Zero.setBitsFrom(Log2_32(BitWidth)+1);
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computeKnownBits(Op.getOperand(0), Known2, DemandedElts, Depth + 1);
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// If we know some of the bits are zero, they can't be one.
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unsigned PossibleOnes = BitWidth - Known2.Zero.countPopulation();
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Known.Zero.setBitsFrom(Log2_32(PossibleOnes) + 1);
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break;
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}
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case ISD::LOAD: {
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@ -1,6 +1,7 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=corei7 | FileCheck %s
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declare i8 @llvm.ctpop.i8(i8) nounwind readnone
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declare i64 @llvm.ctpop.i64(i64) nounwind readnone
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define i32 @test1(i64 %x) nounwind readnone {
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@ -48,3 +49,16 @@ define i32 @test3(i64 %x) nounwind readnone {
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%conv = zext i1 %cmp to i32
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ret i32 %conv
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}
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define i8 @test4(i8 %x) nounwind readnone {
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; CHECK-LABEL: test4:
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; CHECK: # BB#0:
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; CHECK-NEXT: andl $127, %edi
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; CHECK-NEXT: popcntw %di, %ax
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; CHECK-NEXT: # kill: %AL<def> %AL<kill> %AX<kill>
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; CHECK-NEXT: retq
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%x2 = and i8 %x, 127
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%count = tail call i8 @llvm.ctpop.i8(i8 %x2)
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%and = and i8 %count, 7
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ret i8 %and
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}
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