maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

GlobalISel: Combine fneg(fneg x) to x 

https://reviews.llvm.org/D87473
This commit is contained in:
Volkan Keles 2020-09-10 12:57:38 -07:00
parent 4934127e62
commit d4bf90271f
4 changed files with 48 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
View File

@ -269,6 +269,9 @@ public:
bool applyCombineExtOfExt(MachineInstr &MI,
std::tuple<Register, unsigned> &MatchInfo);
/// Transform fneg(fneg(x)) to x.
bool matchCombineFNegOfFNeg(MachineInstr &MI, Register &Reg);
/// Return true if any explicit use operand on \p MI is defined by a
/// G_IMPLICIT_DEF.
bool matchAnyExplicitUseIsUndef(MachineInstr &MI);

12
llvm/include/llvm/Target/GlobalISel/Combine.td
View File

@ -385,6 +385,15 @@ def not_cmp_fold : GICombineRule<
(apply [{ return Helper.applyNotCmp(*${d}, ${info}); }])
>;
// Fold (fneg (fneg x)) -> x.
def fneg_fneg_fold_matchinfo : GIDefMatchData<"Register">;
def fneg_fneg_fold: GICombineRule <
(defs root:$root, fneg_fneg_fold_matchinfo:$matchinfo),
(match (wip_match_opcode G_FNEG):$root,
[{ return Helper.matchCombineFNegOfFNeg(*${root}, ${matchinfo}); }]),
(apply [{ return Helper.replaceSingleDefInstWithReg(*${root}, ${matchinfo}); }])
>;
// FIXME: These should use the custom predicate feature once it lands.
def undef_combines : GICombineGroup<[undef_to_fp_zero, undef_to_int_zero,
undef_to_negative_one,
@ -397,7 +406,8 @@ def undef_combines : GICombineGroup<[undef_to_fp_zero, undef_to_int_zero,
def identity_combines : GICombineGroup<[select_same_val, right_identity_zero,
binop_same_val, binop_left_to_zero,
binop_right_to_zero, p2i_to_i2p,
i2p_to_p2i, anyext_trunc_fold]>;
i2p_to_p2i, anyext_trunc_fold,
fneg_fneg_fold]>;
def known_bits_simplifications : GICombineGroup<[
and_trivial_mask, redundant_sext_inreg]>;

6
llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
View File

@ -1813,6 +1813,12 @@ bool CombinerHelper::applyCombineExtOfExt(
return false;
}
bool CombinerHelper::matchCombineFNegOfFNeg(MachineInstr &MI, Register &Reg) {
assert(MI.getOpcode() == TargetOpcode::G_FNEG && "Expected a G_FNEG");
Register SrcReg = MI.getOperand(1).getReg();
return mi_match(SrcReg, MRI, m_GFNeg(m_Reg(Reg)));
}
bool CombinerHelper::matchAnyExplicitUseIsUndef(MachineInstr &MI) {
return any_of(MI.explicit_uses(), [this](const MachineOperand &MO) {
return MO.isReg() &&

28
llvm/test/CodeGen/AArch64/GlobalISel/combine-fneg.mir Normal file
View File

@ -0,0 +1,28 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -o - -mtriple=aarch64-unknown-unknown -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s | FileCheck %s
---
name: test_combine_fneg_fneg
body: |
bb.1:
liveins: $w0
; CHECK-LABEL: name: test_combine_fneg_fneg
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK: $w0 = COPY [[COPY]](s32)
%0:_(s32) = COPY $w0
%1:_(s32) = G_FNEG %0(s32)
%2:_(s32) = G_FNEG %1(s32)
$w0 = COPY %2(s32)
...
---
name: test_combine_fneg_fneg_vec
body: |
bb.1:
liveins: $x0
; CHECK-LABEL: name: test_combine_fneg_fneg_vec
; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $x0
; CHECK: $x0 = COPY [[COPY]](<2 x s32>)
%0:_(<2 x s32>) = COPY $x0
%1:_(<2 x s32>) = G_FNEG %0(<2 x s32>)
%2:_(<2 x s32>) = G_FNEG %1(<2 x s32>)
$x0 = COPY %2(<2 x s32>)
...