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AMDGPU: Treat more custom operations as canonicalizing 

Everything should quiet, and I think everything should
flush.

I assume the min3/med3/max3 follow the same rules
as regular min/max for flushing, which should at
least be conservatively correct.

There are still more operations that need to
be handled.

llvm-svn: 339065
This commit is contained in:
Matt Arsenault 2018-08-06 21:58:11 +00:00
parent ce6d61fba8
commit d49ab0b214
3 changed files with 63 additions and 4 deletions
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5
llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
View File

@ -4369,7 +4369,8 @@ bool AMDGPUTargetLowering::isKnownNeverNaNForTargetNode(SDValue Op,
// TODO: Need is known positive check.
return false;
}
case AMDGPUISD::LDEXP: {
case AMDGPUISD::LDEXP:
case AMDGPUISD::FRACT: {
if (SNaN)
return true;
return DAG.isKnownNeverNaN(Op.getOperand(0), SNaN, Depth + 1);
@ -4394,6 +4395,8 @@ bool AMDGPUTargetLowering::isKnownNeverNaNForTargetNode(SDValue Op,
return true;
case Intrinsic::amdgcn_frexp_mant:
if (SNaN)
return true;
return DAG.isKnownNeverNaN(Op.getOperand(1), SNaN, Depth + 1);
default:
return false;

18
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
View File

@ -6779,6 +6779,18 @@ bool SITargetLowering::isCanonicalized(SelectionDAG &DAG, SDValue Op,
case ISD::FP_EXTEND:
case AMDGPUISD::FMUL_LEGACY:
case AMDGPUISD::FMAD_FTZ:
case AMDGPUISD::RCP:
case AMDGPUISD::RSQ:
case AMDGPUISD::RSQ_CLAMP:
case AMDGPUISD::RCP_LEGACY:
case AMDGPUISD::RSQ_LEGACY:
case AMDGPUISD::RCP_IFLAG:
case AMDGPUISD::TRIG_PREOP:
case AMDGPUISD::DIV_SCALE:
case AMDGPUISD::DIV_FMAS:
case AMDGPUISD::DIV_FIXUP:
case AMDGPUISD::FRACT:
case AMDGPUISD::LDEXP:
return true;
// It can/will be lowered or combined as a bit operation.
@ -6794,7 +6806,11 @@ bool SITargetLowering::isCanonicalized(SelectionDAG &DAG, SDValue Op,
return Op.getValueType().getScalarType() != MVT::f16;
case ISD::FMINNUM:
case ISD::FMAXNUM: {
case ISD::FMAXNUM:
case AMDGPUISD::CLAMP:
case AMDGPUISD::FMED3:
case AMDGPUISD::FMAX3:
case AMDGPUISD::FMIN3: {
// FIXME: Shouldn't treat the generic operations different based these.
bool IsIEEEMode = Subtarget->enableIEEEBit(DAG.getMachineFunction());
if (IsIEEEMode) {

44
llvm/test/CodeGen/AMDGPU/known-never-snan.ll
View File

@ -535,8 +535,7 @@ define float @v_test_not_known_frexp_mant_input_fmed3_r_i_i_f32(float %arg) #0 {
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_frexp_mant_f32_e32 v0, v0
; GCN-NEXT: v_max_f32_e32 v0, 2.0, v0
; GCN-NEXT: v_min_f32_e32 v0, 4.0, v0
; GCN-NEXT: v_med3_f32 v0, v0, 2.0, 4.0
; GCN-NEXT: s_setpc_b64 s[30:31]
%known.not.snan = call float @llvm.amdgcn.frexp.mant.f32(float %arg)
%max = call float @llvm.maxnum.f32(float %known.not.snan, float 2.0)
@ -559,6 +558,44 @@ define float @v_test_known_not_frexp_mant_input_fmed3_r_i_i_f32(float %arg) #0 {
ret float %med
}
define float @v_test_known_not_snan_rcp_input_fmed3_r_i_i_f32(float %a) #0 {
; GCN-LABEL: v_test_known_not_snan_rcp_input_fmed3_r_i_i_f32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_rcp_f32_e32 v0, v0
; GCN-NEXT: v_med3_f32 v0, v0, 2.0, 4.0
; GCN-NEXT: s_setpc_b64 s[30:31]
%known.not.snan = call float @llvm.amdgcn.rcp.f32(float %a)
%max = call float @llvm.maxnum.f32(float %known.not.snan, float 2.0)
%med = call float @llvm.minnum.f32(float %max, float 4.0)
ret float %med
}
define float @v_test_known_not_snan_rsq_input_fmed3_r_i_i_f32(float %a) #0 {
; GCN-LABEL: v_test_known_not_snan_rsq_input_fmed3_r_i_i_f32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_rsq_f32_e32 v0, v0
; GCN-NEXT: v_med3_f32 v0, v0, 2.0, 4.0
; GCN-NEXT: s_setpc_b64 s[30:31]
%known.not.snan = call float @llvm.amdgcn.rsq.f32(float %a)
%max = call float @llvm.maxnum.f32(float %known.not.snan, float 2.0)
%med = call float @llvm.minnum.f32(float %max, float 4.0)
ret float %med
}
define float @v_test_known_not_snan_fract_input_fmed3_r_i_i_f32(float %a) #0 {
; GCN-LABEL: v_test_known_not_snan_fract_input_fmed3_r_i_i_f32:
; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_fract_f32_e32 v0, v0
; GCN-NEXT: v_med3_f32 v0, v0, 2.0, 4.0
; GCN-NEXT: s_setpc_b64 s[30:31]
%known.not.snan = call float @llvm.amdgcn.fract.f32(float %a)
%max = call float @llvm.maxnum.f32(float %known.not.snan, float 2.0)
%med = call float @llvm.minnum.f32(float %max, float 4.0)
ret float %med
}
define float @v_test_known_not_snan_cubeid_input_fmed3_r_i_i_f32(float %a, float %b, float %c) #0 {
; GCN-LABEL: v_test_known_not_snan_cubeid_input_fmed3_r_i_i_f32:
; GCN: ; %bb.0:
@ -592,6 +629,9 @@ declare float @llvm.amdgcn.ldexp.f32(float, i32) #1
declare float @llvm.amdgcn.fmul.legacy(float, float) #1
declare float @llvm.amdgcn.fmed3.f32(float, float, float) #1
declare float @llvm.amdgcn.frexp.mant.f32(float) #1
declare float @llvm.amdgcn.rcp.f32(float) #1
declare float @llvm.amdgcn.rsq.f32(float) #1
declare float @llvm.amdgcn.fract.f32(float) #1
declare float @llvm.amdgcn.cubeid(float, float, float) #0
attributes #0 = { nounwind }