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[SelectionDAG] Don't pass on DemandedElts when handling SCALAR_TO_VECTOR 

Fixes an assertion:

llc: lib/CodeGen/SelectionDAG/SelectionDAG.cpp:2200: llvm::KnownBits llvm::SelectionDAG::computeKnownBits(llvm::SDValue, const llvm::APInt&, unsigned int) const: Assertion `(!Op.getValueType().isVector() || NumElts == Op.getValueType().getVectorNumElements()) && "Unexpected vector size"' failed.

Committed on behalf of: @pendingchaos (Rhys Perry)

Differential Revision: https://reviews.llvm.org/D55223

llvm-svn: 348574
This commit is contained in:
Simon Pilgrim 2018-12-07 09:18:44 +00:00
parent d765108cf1
commit d498dee7a2
2 changed files with 12 additions and 1 deletions
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2
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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@ -2352,7 +2352,7 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
break;
SDValue N0 = Op.getOperand(0);
Known = computeKnownBits(N0, DemandedElts, Depth + 1);
Known = computeKnownBits(N0, Depth + 1);
if (N0.getValueSizeInBits() != BitWidth)
Known = Known.trunc(BitWidth);

11
llvm/test/CodeGen/AMDGPU/computeKnownBits-scalar-to-vector-crash.ll Normal file
View File

@ -0,0 +1,11 @@
; RUN: llc -march=amdgcn -mcpu=gfx802 -verify-machineinstrs < %s | FileCheck %s
; CHECK: s_waitcnt
define <2 x i16> @main(<2 x float>) #0 {
%2 = bitcast <2 x float> %0 to <4 x i16>
%3 = shufflevector <4 x i16> %2, <4 x i16> undef, <2 x i32> <i32 0, i32 undef>
%4 = extractelement <4 x i16> %2, i32 0
%5 = insertelement <2 x i16> %3, i16 %4, i32 0
ret <2 x i16> %5
}