forked from OSchip/llvm-project
[X86][AVX512] Tag BLENDM instruction scheduler classes
llvm-svn: 319833
This commit is contained in:
Simon Pilgrim
parent
f363fd8d30
commit
d495301414
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@ -1775,92 +1775,109 @@ defm VPERMT2PD : avx512_perm_t_sizes<0x7F, "vpermt2pd", AVX512_PERM2_F,
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//===----------------------------------------------------------------------===//
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// AVX-512 - BLEND using mask
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//
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multiclass avx512_blendmask<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
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let Sched = WriteFVarBlend in
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def AVX512_BLENDM : OpndItins<
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IIC_SSE_ALU_F32P_RR, IIC_SSE_ALU_F32P_RM
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>;
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let Sched = WriteVarBlend in
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def AVX512_PBLENDM : OpndItins<
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IIC_SSE_INTALU_P_RR, IIC_SSE_INTALU_P_RM
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>;
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multiclass avx512_blendmask<bits<8> opc, string OpcodeStr, OpndItins itins,
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X86VectorVTInfo _> {
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let ExeDomain = _.ExeDomain, hasSideEffects = 0 in {
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def rr : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
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(ins _.RC:$src1, _.RC:$src2),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, ${dst}|${dst}, $src1, $src2}"),
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[]>, EVEX_4V;
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[], itins.rr>, EVEX_4V, Sched<[itins.Sched]>;
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def rrk : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
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(ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
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[]>, EVEX_4V, EVEX_K;
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[], itins.rr>, EVEX_4V, EVEX_K, Sched<[itins.Sched]>;
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def rrkz : AVX5128I<opc, MRMSrcReg, (outs _.RC:$dst),
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(ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
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[]>, EVEX_4V, EVEX_KZ;
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[], itins.rr>, EVEX_4V, EVEX_KZ, Sched<[itins.Sched]>;
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let mayLoad = 1 in {
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def rm : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
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(ins _.RC:$src1, _.MemOp:$src2),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, ${dst}|${dst}, $src1, $src2}"),
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[]>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>;
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[], itins.rm>, EVEX_4V, EVEX_CD8<_.EltSize, CD8VF>,
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Sched<[itins.Sched.Folded, ReadAfterLd]>;
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def rmk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
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(ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
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[]>, EVEX_4V, EVEX_K, EVEX_CD8<_.EltSize, CD8VF>;
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[], itins.rm>, EVEX_4V, EVEX_K, EVEX_CD8<_.EltSize, CD8VF>,
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Sched<[itins.Sched.Folded, ReadAfterLd]>;
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def rmkz : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
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(ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
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!strconcat(OpcodeStr,
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"\t{$src2, $src1, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src1, $src2}"),
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[]>, EVEX_4V, EVEX_KZ, EVEX_CD8<_.EltSize, CD8VF>;
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[], itins.rm>, EVEX_4V, EVEX_KZ, EVEX_CD8<_.EltSize, CD8VF>,
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Sched<[itins.Sched.Folded, ReadAfterLd]>;
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}
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}
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}
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multiclass avx512_blendmask_rmb<bits<8> opc, string OpcodeStr, X86VectorVTInfo _> {
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multiclass avx512_blendmask_rmb<bits<8> opc, string OpcodeStr, OpndItins itins,
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X86VectorVTInfo _> {
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let mayLoad = 1, hasSideEffects = 0 in {
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def rmbk : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
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(ins _.KRCWM:$mask, _.RC:$src1, _.ScalarMemOp:$src2),
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!strconcat(OpcodeStr,
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"\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
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"$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
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[]>, EVEX_4V, EVEX_K, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
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[], itins.rm>, EVEX_4V, EVEX_K, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>,
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Sched<[itins.Sched.Folded, ReadAfterLd]>;
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def rmb : AVX5128I<opc, MRMSrcMem, (outs _.RC:$dst),
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(ins _.RC:$src1, _.ScalarMemOp:$src2),
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!strconcat(OpcodeStr,
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"\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
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"$dst, $src1, ${src2}", _.BroadcastStr, "}"),
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[]>, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>;
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[], itins.rm>, EVEX_4V, EVEX_B, EVEX_CD8<_.EltSize, CD8VF>,
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Sched<[itins.Sched.Folded, ReadAfterLd]>;
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}
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}
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multiclass blendmask_dq <bits<8> opc, string OpcodeStr,
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multiclass blendmask_dq <bits<8> opc, string OpcodeStr, OpndItins itins,
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AVX512VLVectorVTInfo VTInfo> {
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defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>,
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avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
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defm Z : avx512_blendmask <opc, OpcodeStr, itins, VTInfo.info512>,
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avx512_blendmask_rmb <opc, OpcodeStr, itins, VTInfo.info512>, EVEX_V512;
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let Predicates = [HasVLX] in {
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defm Z256 : avx512_blendmask<opc, OpcodeStr, VTInfo.info256>,
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avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
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defm Z128 : avx512_blendmask<opc, OpcodeStr, VTInfo.info128>,
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avx512_blendmask_rmb <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
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defm Z256 : avx512_blendmask<opc, OpcodeStr, itins, VTInfo.info256>,
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avx512_blendmask_rmb<opc, OpcodeStr, itins, VTInfo.info256>, EVEX_V256;
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defm Z128 : avx512_blendmask<opc, OpcodeStr, itins, VTInfo.info128>,
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avx512_blendmask_rmb<opc, OpcodeStr, itins, VTInfo.info128>, EVEX_V128;
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}
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}
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multiclass blendmask_bw <bits<8> opc, string OpcodeStr,
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multiclass blendmask_bw <bits<8> opc, string OpcodeStr, OpndItins itins,
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AVX512VLVectorVTInfo VTInfo> {
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let Predicates = [HasBWI] in
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defm Z : avx512_blendmask <opc, OpcodeStr, VTInfo.info512>, EVEX_V512;
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defm Z : avx512_blendmask<opc, OpcodeStr, itins, VTInfo.info512>, EVEX_V512;
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let Predicates = [HasBWI, HasVLX] in {
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defm Z256 : avx512_blendmask <opc, OpcodeStr, VTInfo.info256>, EVEX_V256;
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defm Z128 : avx512_blendmask <opc, OpcodeStr, VTInfo.info128>, EVEX_V128;
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defm Z256 : avx512_blendmask<opc, OpcodeStr, itins, VTInfo.info256>, EVEX_V256;
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defm Z128 : avx512_blendmask<opc, OpcodeStr, itins, VTInfo.info128>, EVEX_V128;
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}
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}
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defm VBLENDMPS : blendmask_dq <0x65, "vblendmps", avx512vl_f32_info>;
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defm VBLENDMPD : blendmask_dq <0x65, "vblendmpd", avx512vl_f64_info>, VEX_W;
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defm VPBLENDMD : blendmask_dq <0x64, "vpblendmd", avx512vl_i32_info>;
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defm VPBLENDMQ : blendmask_dq <0x64, "vpblendmq", avx512vl_i64_info>, VEX_W;
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defm VPBLENDMB : blendmask_bw <0x66, "vpblendmb", avx512vl_i8_info>;
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defm VPBLENDMW : blendmask_bw <0x66, "vpblendmw", avx512vl_i16_info>, VEX_W;
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defm VBLENDMPS : blendmask_dq <0x65, "vblendmps", AVX512_BLENDM, avx512vl_f32_info>;
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defm VBLENDMPD : blendmask_dq <0x65, "vblendmpd", AVX512_BLENDM, avx512vl_f64_info>, VEX_W;
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defm VPBLENDMD : blendmask_dq <0x64, "vpblendmd", AVX512_PBLENDM, avx512vl_i32_info>;
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defm VPBLENDMQ : blendmask_dq <0x64, "vpblendmq", AVX512_PBLENDM, avx512vl_i64_info>, VEX_W;
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defm VPBLENDMB : blendmask_bw <0x66, "vpblendmb", AVX512_PBLENDM, avx512vl_i8_info>;
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defm VPBLENDMW : blendmask_bw <0x66, "vpblendmw", AVX512_PBLENDM, avx512vl_i16_info>, VEX_W;
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//===----------------------------------------------------------------------===//
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@ -7330,7 +7330,7 @@ define <64 x i8> @vmov_test16(i64 %x) {
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; GENERIC-NEXT: vpmovm2b %k0, %zmm1
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; GENERIC-NEXT: movl $32, %eax # sched: [1:0.33]
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; GENERIC-NEXT: kmovd %eax, %k1
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; GENERIC-NEXT: vpblendmb %ymm0, %ymm1, %ymm0 {%k1}
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; GENERIC-NEXT: vpblendmb %ymm0, %ymm1, %ymm0 {%k1} # sched: [2:1.00]
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; GENERIC-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm0[0,1,2,3],zmm1[4,5,6,7] sched: [1:1.00]
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; GENERIC-NEXT: vpmovb2m %zmm0, %k0
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; GENERIC-NEXT: vpmovm2b %k0, %zmm0
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@ -7370,7 +7370,7 @@ define <64 x i8> @vmov_test17(i64 %x, i32 %y, i32 %z) {
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; GENERIC-NEXT: vpmovm2b %k0, %zmm1
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; GENERIC-NEXT: movl $32, %eax # sched: [1:0.33]
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; GENERIC-NEXT: kmovd %eax, %k1
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; GENERIC-NEXT: vpblendmb %ymm0, %ymm1, %ymm0 {%k1}
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; GENERIC-NEXT: vpblendmb %ymm0, %ymm1, %ymm0 {%k1} # sched: [2:1.00]
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; GENERIC-NEXT: vshufi64x2 {{.*#+}} zmm0 = zmm0[0,1,2,3],zmm1[4,5,6,7] sched: [1:1.00]
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; GENERIC-NEXT: vpmovb2m %zmm0, %k0
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; GENERIC-NEXT: vpmovm2b %k0, %zmm0
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