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R600: Add AR_X to the R600_TReg_X register class. 

NOTE: This is a candidate for the Mesa stable branch.
llvm-svn: 175519
This commit is contained in:
Tom Stellard 2013-02-19 15:22:47 +00:00
parent a24a516737
commit d4409e2cec
1 changed files with 1 additions and 1 deletions
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2
llvm/lib/Target/R600/R600RegisterInfo.td
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@ -81,7 +81,7 @@ def R600_Addr : RegisterClass <"AMDGPU", [i32], 127, (add (sequence "Addr%u_X",
} // End isAllocatable = 0 } // End isAllocatable = 0
def R600_TReg32_X : RegisterClass <"AMDGPU", [f32, i32], 32, def R600_TReg32_X : RegisterClass <"AMDGPU", [f32, i32], 32,
(add (sequence "T%u_X", 0, 127))>; (add (sequence "T%u_X", 0, 127), AR_X)>;
def R600_TReg32_Y : RegisterClass <"AMDGPU", [f32, i32], 32, def R600_TReg32_Y : RegisterClass <"AMDGPU", [f32, i32], 32,
(add (sequence "T%u_Y", 0, 127))>; (add (sequence "T%u_Y", 0, 127))>;