forked from OSchip/llvm-project
[WebAssembly] Stackify code emitted by eliminateFrameIndex and SP writeback
Summary: MRI::eliminateFrameIndex can emit several instructions to do address calculations; these can usually be stackified. Because instructions with FI operands can have subsequent operands which may be expression trees, find the top of the leftmost tree and insert the code before it, to keep the LIFO property. Also use stackified registers when writing back the SP value to memory in the epilog; it's unnecessary because SP will not be used after the epilog, and it results in better code. Differential Revision: http://reviews.llvm.org/D18234 llvm-svn: 263725
This commit is contained in:
Derek Schuff
parent
93bbc7cd66
commit
d4207ba0f6
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@ -78,19 +78,20 @@ bool WebAssemblyFrameLowering::needsSPWriteback(
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static void writeSPToMemory(unsigned SrcReg, MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator &InsertPt,
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MachineBasicBlock::iterator &InsertAddr,
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MachineBasicBlock::iterator &InsertStore,
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DebugLoc DL) {
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auto *SPSymbol = MF.createExternalSymbolName("__stack_pointer");
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unsigned SPAddr =
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MF.getRegInfo().createVirtualRegister(&WebAssembly::I32RegClass);
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const auto *TII = MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo();
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BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::CONST_I32), SPAddr)
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BuildMI(MBB, InsertAddr, DL, TII->get(WebAssembly::CONST_I32), SPAddr)
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.addExternalSymbol(SPSymbol);
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auto *MMO = new MachineMemOperand(MachinePointerInfo(),
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MachineMemOperand::MOStore, 4, 4);
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BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::STORE_I32),
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WebAssembly::SP32)
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BuildMI(MBB, InsertStore, DL, TII->get(WebAssembly::STORE_I32),
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SrcReg)
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.addImm(0)
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.addReg(SPAddr)
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.addImm(2) // p2align
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@ -108,7 +109,7 @@ void WebAssemblyFrameLowering::eliminateCallFramePseudoInstr(
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if (I->getOpcode() == TII->getCallFrameDestroyOpcode() &&
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needsSPWriteback(MF, *MF.getFrameInfo())) {
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DebugLoc DL = I->getDebugLoc();
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writeSPToMemory(WebAssembly::SP32, MF, MBB, I, DL);
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writeSPToMemory(WebAssembly::SP32, MF, MBB, I, I, DL);
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}
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MBB.erase(I);
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}
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@ -171,7 +172,7 @@ void WebAssemblyFrameLowering::emitPrologue(MachineFunction &MF,
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.addReg(WebAssembly::SP32);
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}
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if (StackSize && needsSPWriteback(MF, *MFI)) {
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writeSPToMemory(WebAssembly::SP32, MF, MBB, InsertPt, DL);
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writeSPToMemory(WebAssembly::SP32, MF, MBB, InsertPt, InsertPt, DL);
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}
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}
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@ -192,18 +193,24 @@ void WebAssemblyFrameLowering::emitEpilogue(MachineFunction &MF,
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// Restore the stack pointer. If we had fixed-size locals, add the offset
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// subtracted in the prolog.
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unsigned SPReg = 0;
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MachineBasicBlock::iterator InsertAddr = InsertPt;
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if (StackSize) {
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unsigned OffsetReg = MRI.createVirtualRegister(&WebAssembly::I32RegClass);
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BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::CONST_I32), OffsetReg)
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.addImm(StackSize);
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BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::ADD_I32),
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WebAssembly::SP32)
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InsertAddr =
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BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::CONST_I32), OffsetReg)
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.addImm(StackSize);
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// In the epilog we don't need to write the result back to the SP32 physreg
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// because it won't be used again. We can use a stackified register instead.
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SPReg = MRI.createVirtualRegister(&WebAssembly::I32RegClass);
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BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::ADD_I32), SPReg)
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.addReg(hasFP(MF) ? WebAssembly::FP32 : WebAssembly::SP32)
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.addReg(OffsetReg);
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WFI->stackifyVReg(OffsetReg);
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WFI->stackifyVReg(SPReg);
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} else {
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SPReg = hasFP(MF) ? WebAssembly::FP32 : WebAssembly::SP32;
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}
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writeSPToMemory(
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(!StackSize && hasFP(MF)) ? WebAssembly::FP32 : WebAssembly::SP32, MF,
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MBB, InsertPt, DL);
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writeSPToMemory(SPReg, MF, MBB, InsertAddr, InsertPt, DL);
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}
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@ -51,6 +51,51 @@ WebAssemblyRegisterInfo::getReservedRegs(const MachineFunction & /*MF*/) const {
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return Reserved;
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}
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static bool isStackifiedVReg(const WebAssemblyFunctionInfo *WFI,
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const MachineOperand& Op) {
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if (Op.isReg()) {
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unsigned Reg = Op.getReg();
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return TargetRegisterInfo::isVirtualRegister(Reg) &&
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WFI->isVRegStackified(Reg);
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}
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return false;
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}
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static bool canStackifyOperand(const MachineInstr& Inst) {
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unsigned Op = Inst.getOpcode();
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return Op != TargetOpcode::PHI &&
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Op != TargetOpcode::INLINEASM &&
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Op != TargetOpcode::DBG_VALUE;
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}
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// Determine if the FI sequence can be stackified, and if so, where the code can
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// be inserted. If stackification is possible, returns true and ajusts II to
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// point to the insertion point.
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bool findInsertPt(const WebAssemblyFunctionInfo *WFI, MachineBasicBlock &MBB,
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unsigned OperandNum, MachineBasicBlock::iterator &II) {
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if (!canStackifyOperand(*II)) return false;
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MachineBasicBlock::iterator InsertPt(II);
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int StackCount = 0;
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// Operands are popped in reverse order, so any operands after FIOperand
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// impose a constraint
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for (unsigned i = OperandNum; i < II->getNumOperands(); i++) {
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if (isStackifiedVReg(WFI, II->getOperand(i))) ++StackCount;
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}
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// Walk backwards, tracking stack depth. When it reaches 0 we have reached the
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// top of the subtree.
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while (StackCount) {
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if (InsertPt == MBB.begin()) return false;
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--InsertPt;
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for (const auto &def : InsertPt->defs())
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if (isStackifiedVReg(WFI, def)) --StackCount;
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for (const auto &use : InsertPt->explicit_uses())
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if (isStackifiedVReg(WFI, use)) ++StackCount;
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}
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II = InsertPt;
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return true;
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}
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void WebAssemblyRegisterInfo::eliminateFrameIndex(
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MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum,
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RegScavenger * /*RS*/) const {
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@ -78,20 +123,34 @@ void WebAssemblyRegisterInfo::eliminateFrameIndex(
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MI.getOperand(FIOperandNum)
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.ChangeToRegister(WebAssembly::SP32, /*IsDef=*/false);
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} else {
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// Otherwise create an i32.add SP, offset and make it the operand.
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// Otherwise calculate the address
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auto &MRI = MF.getRegInfo();
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const auto *TII = MF.getSubtarget<WebAssemblySubtarget>().getInstrInfo();
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unsigned FIRegOperand = WebAssembly::SP32;
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if (FrameOffset) {
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FIRegOperand = MRI.createVirtualRegister(&WebAssembly::I32RegClass);
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BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(WebAssembly::CONST_I32),
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FIRegOperand)
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// Create i32.add SP, offset and make it the operand. We want to stackify
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// this sequence, but we need to preserve the LIFO expr stack ordering
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// (i.e. we can't insert our code in between MI and any operands it
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// pops before FIOperand).
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auto *WFI = MF.getInfo<WebAssemblyFunctionInfo>();
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bool CanStackifyFI = findInsertPt(WFI, MBB, FIOperandNum, II);
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unsigned OffsetOp = MRI.createVirtualRegister(&WebAssembly::I32RegClass);
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BuildMI(MBB, *II, II->getDebugLoc(), TII->get(WebAssembly::CONST_I32),
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OffsetOp)
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.addImm(FrameOffset);
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BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(WebAssembly::ADD_I32),
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if (CanStackifyFI) {
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WFI->stackifyVReg(OffsetOp);
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FIRegOperand = MRI.createVirtualRegister(&WebAssembly::I32RegClass);
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WFI->stackifyVReg(FIRegOperand);
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} else {
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FIRegOperand = OffsetOp;
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}
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BuildMI(MBB, *II, II->getDebugLoc(), TII->get(WebAssembly::ADD_I32),
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FIRegOperand)
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.addReg(WebAssembly::SP32)
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.addReg(FIRegOperand);
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.addReg(OffsetOp);
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}
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MI.getOperand(FIOperandNum).ChangeToRegister(FIRegOperand, /*IsDef=*/false);
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}
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@ -35,15 +35,15 @@ define void @byval_arg(%SmallStruct* %ptr) {
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; CHECK-NEXT: i32.load $push[[L4:.+]]=, 0($0)
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; CHECK-NEXT: i32.store {{.*}}=, 12([[SP]]), $pop[[L4]]
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; Pass a pointer to the stack slot to the function
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; CHECK-NEXT: i32.const [[L5:.+]]=, 12
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; CHECK-NEXT: i32.add [[ARG:.+]]=, [[SP]], [[L5]]
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; CHECK-NEXT: call ext_byval_func@FUNCTION, [[L5]]
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; CHECK-NEXT: i32.const $push[[L5:.+]]=, 12
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; CHECK-NEXT: i32.add $push[[ARG:.+]]=, [[SP]], $pop[[L5]]
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; CHECK-NEXT: call ext_byval_func@FUNCTION, $pop[[ARG]]
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call void @ext_byval_func(%SmallStruct* byval %ptr)
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; Restore the stack
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; CHECK-NEXT: i32.const $push[[L6:.+]]=, 16
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; CHECK-NEXT: i32.add [[SP]]=, [[SP]], $pop[[L6]]
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; CHECK-NEXT: i32.const $push[[L7:.+]]=, __stack_pointer
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; CHECK-NEXT: i32.store {{.*}}=, 0($pop[[L7]]), [[SP]]
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; CHECK-NEXT: i32.const $push[[L6:.+]]=, 16
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; CHECK-NEXT: i32.add $push[[L8:.+]]=, [[SP]], $pop[[L6]]
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; CHECK-NEXT: i32.store {{.*}}=, 0($pop[[L7]]), $pop[[L8]]
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; CHECK-NEXT: return
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ret void
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}
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@ -58,9 +58,9 @@ define void @byval_arg_align8(%SmallStruct* %ptr) {
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; CHECK: i32.load $push[[L4:.+]]=, 0($0):p2align=3
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; CHECK-NEXT: i32.store {{.*}}=, 8([[SP]]):p2align=3, $pop[[L4]]
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; Pass a pointer to the stack slot to the function
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; CHECK-NEXT: i32.const [[L5:.+]]=, 8
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; CHECK-NEXT: i32.add [[ARG:.+]]=, [[SP]], [[L5]]
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; CHECK-NEXT: call ext_byval_func_align8@FUNCTION, [[L5]]
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; CHECK-NEXT: i32.const $push[[L5:.+]]=, 8
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; CHECK-NEXT: i32.add $push[[ARG:.+]]=, [[SP]], $pop[[L5]]
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; CHECK-NEXT: call ext_byval_func_align8@FUNCTION, $pop[[ARG]]
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call void @ext_byval_func_align8(%SmallStruct* byval align 8 %ptr)
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ret void
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}
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@ -61,8 +61,8 @@ define void @set_no(i8* %dst, i8 %src, i32 %len) {
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; CHECK-LABEL: frame_index:
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; CHECK: i32.call $discard=, memset@FUNCTION, $0, $pop1, $pop0{{$}}
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; CHECK: i32.call $discard=, memset@FUNCTION, $1, $pop3, $pop2{{$}}
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; CHECK: i32.call $discard=, memset@FUNCTION, $pop12, $pop1, $pop0{{$}}
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; CHECK: i32.call $discard=, memset@FUNCTION, $0, $pop3, $pop2{{$}}
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; CHECK: return{{$}}
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define void @frame_index() {
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entry:
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@ -22,10 +22,10 @@ define void @alloca32() noredzone {
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; CHECK: i32.const $push[[L0:.+]]=, 0
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; CHECK: i32.store {{.*}}=, 12([[SP]]), $pop[[L0]]
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store i32 0, i32* %retval
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; CHECK: i32.const $push[[L5:.+]]=, 16
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; CHECK-NEXT: i32.add [[SP]]=, [[SP]], $pop[[L5]]
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; CHECK-NEXT: i32.const $push[[L6:.+]]=, __stack_pointer
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; CHECK-NEXT: i32.store $discard=, 0($pop[[L6]]), [[SP]]
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; CHECK: i32.const $push[[L6:.+]]=, __stack_pointer
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; CHECK-NEXT: i32.const $push[[L5:.+]]=, 16
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; CHECK-NEXT: i32.add $push[[L7:.+]]=, [[SP]], $pop[[L5]]
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; CHECK-NEXT: i32.store $discard=, 0($pop[[L6]]), $pop[[L7]]
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ret void
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}
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@ -49,7 +49,7 @@ define void @alloca3264() {
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}
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; CHECK-LABEL: allocarray:
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; CHECK: .local i32, i32{{$}}
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; CHECK: .local i32{{$}}
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define void @allocarray() {
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; CHECK: i32.const $push[[L1:.+]]=, __stack_pointer
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; CHECK-NEXT: i32.load $push[[L2:.+]]=, 0($pop[[L1]])
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@ -59,10 +59,10 @@ define void @allocarray() {
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; CHECK-NEXT: i32.store $discard=, 0($pop[[L4]]), [[SP]]
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%r = alloca [33 x i32]
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; CHECK-NEXT: i32.const $push[[L5:.+]]=, 12
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; CHECK-NEXT: i32.add $push[[L7:.+]]=, [[SP]], $pop[[L5]]
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; CHECK-NEXT: i32.const $push[[L4:.+]]=, 12
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; CHECK-NEXT: i32.const [[L5:.+]]=, 12
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; CHECK-NEXT: i32.add [[L5]]=, [[SP]], [[L5]]
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; CHECK-NEXT: i32.add $push[[L6:.+]]=, [[L5]], $pop[[L4]]
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; CHECK-NEXT: i32.add $push[[L6:.+]]=, $pop[[L7]], $pop[[L4]]
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; CHECK-NEXT: i32.const $push[[L9:.+]]=, 1{{$}}
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; CHECK-NEXT: i32.store $push[[L10:.+]]=, 12([[SP]]), $pop[[L9]]{{$}}
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; CHECK-NEXT: i32.store $discard=, 0($pop3), $pop[[L10]]{{$}}
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@ -71,10 +71,10 @@ define void @allocarray() {
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%p2 = getelementptr [33 x i32], [33 x i32]* %r, i32 0, i32 3
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store i32 1, i32* %p2
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; CHECK: i32.const $push[[L11:.+]]=, 144
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; CHECK-NEXT: i32.add [[SP]]=, [[SP]], $pop[[L11]]
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; CHECK-NEXT: i32.const $push[[L12:.+]]=, __stack_pointer
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; CHECK-NEXT: i32.store $discard=, 0($pop[[L12]]), [[SP]]
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; CHECK: i32.const $push[[L12:.+]]=, __stack_pointer
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; CHECK-NEXT: i32.const $push[[L11:.+]]=, 144
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; CHECK-NEXT: i32.add $push[[L13:.+]]=, [[SP]], $pop[[L11]]
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; CHECK-NEXT: i32.store $discard=, 0($pop[[L12]]), $pop[[L13]]
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ret void
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}
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@ -86,18 +86,18 @@ define void @non_mem_use(i8** %addr) {
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%r = alloca i64
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%r2 = alloca i64
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; %r is at SP+8
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; CHECK: i32.const [[OFF:.+]]=, 8
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; CHECK-NEXT: i32.add [[ARG1:.+]]=, [[SP]], [[OFF]]
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; CHECK-NEXT: call ext_func@FUNCTION, [[ARG1]]
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; CHECK: i32.const $push[[OFF:.+]]=, 8
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; CHECK-NEXT: i32.add $push[[ARG1:.+]]=, [[SP]], $pop[[OFF]]
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; CHECK-NEXT: call ext_func@FUNCTION, $pop[[ARG1]]
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call void @ext_func(i64* %r)
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; %r2 is at SP+0, no add needed
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; CHECK-NEXT: call ext_func@FUNCTION, [[SP]]
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call void @ext_func(i64* %r2)
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; Use as a value, but in a store
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; %buf is at SP+16
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; CHECK: i32.const [[OFF:.+]]=, 16
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; CHECK-NEXT: i32.add [[VAL:.+]]=, [[SP]], [[OFF]]
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; CHECK-NEXT: i32.store {{.*}}=, 0($0), [[VAL]]
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; CHECK: i32.const $push[[OFF:.+]]=, 16
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; CHECK-NEXT: i32.add $push[[VAL:.+]]=, [[SP]], $pop[[OFF]]
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; CHECK-NEXT: i32.store {{.*}}=, 0($0), $pop[[VAL]]
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%gep = getelementptr inbounds [27 x i8], [27 x i8]* %buf, i32 0, i32 0
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store i8* %gep, i8** %addr
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ret void
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@ -120,10 +120,10 @@ define void @allocarray_inbounds() {
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%p2 = getelementptr inbounds [5 x i32], [5 x i32]* %r, i32 0, i32 3
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store i32 1, i32* %p2
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call void @ext_func(i64* null);
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; CHECK: i32.const $push[[L5:.+]]=, 32
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; CHECK-NEXT: i32.add [[SP]]=, [[SP]], $pop[[L5]]
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; CHECK-NEXT: i32.const $push[[L6:.+]]=, __stack_pointer
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; CHECK-NEXT: i32.store $discard=, 0($pop[[L6]]), [[SP]]
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; CHECK: i32.const $push[[L6:.+]]=, __stack_pointer
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; CHECK-NEXT: i32.const $push[[L5:.+]]=, 32
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; CHECK-NEXT: i32.add $push[[L7:.+]]=, [[SP]], $pop[[L5]]
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; CHECK-NEXT: i32.store $discard=, 0($pop[[L6]]), $pop[[L7]]
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ret void
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}
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@ -143,7 +143,7 @@ define void @dynamic_alloca(i32 %alloc) {
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; CHECK: call ext_func_i32@FUNCTION
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call void @ext_func_i32(i32* %r)
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; CHECK: i32.const $push[[L3:.+]]=, __stack_pointer
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; CHECK-NEXT: i32.store [[SP]]=, 0($pop[[L3]]), [[FP]]
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; CHECK-NEXT: i32.store $discard=, 0($pop[[L3]]), [[FP]]
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ret void
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}
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@ -183,10 +183,10 @@ define void @dynamic_static_alloca(i32 %alloc) noredzone {
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%r1 = alloca i32
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%r = alloca i32, i32 %alloc
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store i32 0, i32* %r
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; CHECK: i32.const $push[[L5:.+]]=, 16
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; CHECK-NEXT: i32.add [[SP]]=, [[FP]], $pop[[L5]]
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; CHECK-NEXT: i32.const $push[[L6:.+]]=, __stack_pointer
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; CHECK-NEXT: i32.store $discard=, 0($pop[[L6]]), [[SP]]
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; CHECK: i32.const $push[[L6:.+]]=, __stack_pointer
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; CHECK-NEXT: i32.const $push[[L5:.+]]=, 16
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; CHECK-NEXT: i32.add $push[[L7:.+]]=, [[FP]], $pop[[L5]]
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; CHECK-NEXT: i32.store $discard=, 0($pop[[L6]]), $pop[[L7]]
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ret void
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}
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@ -198,9 +198,9 @@ entry:
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; CHECK: i32.const $push[[L1:.+]]=, 16
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; CHECK-NEXT: i32.sub [[SP:.+]]=, {{.+}}, $pop[[L1]]
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%addr = alloca i32
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; CHECK: i32.const [[OFF:.+]]=, 12
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; CHECK-NEXT: i32.add [[ADDR:.+]]=, [[SP]], [[OFF]]
|
||||
; CHECK-NEXT: copy_local [[COPY:.+]]=, [[ADDR]]
|
||||
; CHECK: i32.const $push[[OFF:.+]]=, 12
|
||||
; CHECK-NEXT: i32.add $push[[ADDR:.+]]=, [[SP]], $pop[[OFF]]
|
||||
; CHECK-NEXT: copy_local [[COPY:.+]]=, $pop[[ADDR]]
|
||||
br label %body
|
||||
body:
|
||||
%a = phi i32* [%addr, %entry], [%b, %body]
|
||||
|
|
|
|||
Loading…
Reference in New Issue