forked from OSchip/llvm-project
[X86][AVX1] Account for cost of extract/insert of 256-bit SDIV/UDIV by mul sequences
llvm-svn: 303017
This commit is contained in:
Simon Pilgrim
parent
c1c78617e7
commit
d3f0d03cc5
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@ -247,29 +247,29 @@ int X86TTIImpl::getArithmeticInstrCost(
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}
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static const CostTblEntry SSE2UniformConstCostTable[] = {
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{ ISD::SHL, MVT::v16i8, 2 }, // psllw + pand.
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{ ISD::SRL, MVT::v16i8, 2 }, // psrlw + pand.
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{ ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb.
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{ ISD::SHL, MVT::v16i8, 2 }, // psllw + pand.
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{ ISD::SRL, MVT::v16i8, 2 }, // psrlw + pand.
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{ ISD::SRA, MVT::v16i8, 4 }, // psrlw, pand, pxor, psubb.
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{ ISD::SHL, MVT::v32i8, 4+2 }, // 2*(psllw + pand) + split.
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{ ISD::SRL, MVT::v32i8, 4+2 }, // 2*(psrlw + pand) + split.
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{ ISD::SRA, MVT::v32i8, 8+2 }, // 2*(psrlw, pand, pxor, psubb) + split.
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{ ISD::SHL, MVT::v32i8, 4+2 }, // 2*(psllw + pand) + split.
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{ ISD::SRL, MVT::v32i8, 4+2 }, // 2*(psrlw + pand) + split.
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{ ISD::SRA, MVT::v32i8, 8+2 }, // 2*(psrlw, pand, pxor, psubb) + split.
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{ ISD::SDIV, MVT::v16i16, 12 }, // pmulhw sequence
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{ ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence
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{ ISD::UDIV, MVT::v16i16, 12 }, // pmulhuw sequence
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{ ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence
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{ ISD::SDIV, MVT::v8i32, 38 }, // pmuludq sequence
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{ ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence
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{ ISD::UDIV, MVT::v8i32, 30 }, // pmuludq sequence
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{ ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence
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{ ISD::SDIV, MVT::v16i16, 12+2 }, // 2*pmulhw sequence + split.
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{ ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence
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{ ISD::UDIV, MVT::v16i16, 12+2 }, // 2*pmulhuw sequence + split.
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{ ISD::UDIV, MVT::v8i16, 6 }, // pmulhuw sequence
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{ ISD::SDIV, MVT::v8i32, 38+2 }, // 2*pmuludq sequence + split.
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{ ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence
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{ ISD::UDIV, MVT::v8i32, 30+2 }, // 2*pmuludq sequence + split.
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{ ISD::UDIV, MVT::v4i32, 15 }, // pmuludq sequence
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};
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if (Op2Info == TargetTransformInfo::OK_UniformConstantValue &&
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ST->hasSSE2()) {
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// pmuldq sequence.
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if (ISD == ISD::SDIV && LT.second == MVT::v8i32 && ST->hasAVX())
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return LT.first * 30;
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return LT.first * 32;
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if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41())
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return LT.first * 15;
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@ -139,14 +139,14 @@ define i32 @sdiv_uniformconst() {
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; SSE2: cost of 38 {{.*}} %V8i32 = sdiv
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; SSSE3: cost of 38 {{.*}} %V8i32 = sdiv
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; SSE42: cost of 30 {{.*}} %V8i32 = sdiv
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; AVX1: cost of 30 {{.*}} %V8i32 = sdiv
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; AVX1: cost of 32 {{.*}} %V8i32 = sdiv
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; AVX2: cost of 15 {{.*}} %V8i32 = sdiv
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; AVX512: cost of 15 {{.*}} %V8i32 = sdiv
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%V8i32 = sdiv <8 x i32> undef, <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>
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; SSE2: cost of 76 {{.*}} %V16i32 = sdiv
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; SSSE3: cost of 76 {{.*}} %V16i32 = sdiv
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; SSE42: cost of 60 {{.*}} %V16i32 = sdiv
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; AVX1: cost of 60 {{.*}} %V16i32 = sdiv
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; AVX1: cost of 64 {{.*}} %V16i32 = sdiv
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; AVX2: cost of 30 {{.*}} %V16i32 = sdiv
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; AVX512: cost of 15 {{.*}} %V16i32 = sdiv
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%V16i32 = sdiv <16 x i32> undef, <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>
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@ -157,12 +157,12 @@ define i32 @sdiv_uniformconst() {
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; AVX: cost of 6 {{.*}} %V8i16 = sdiv
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%V8i16 = sdiv <8 x i16> undef, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
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; SSE: cost of 12 {{.*}} %V16i16 = sdiv
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; AVX1: cost of 12 {{.*}} %V16i16 = sdiv
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; AVX1: cost of 14 {{.*}} %V16i16 = sdiv
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; AVX2: cost of 6 {{.*}} %V16i16 = sdiv
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; AVX512: cost of 6 {{.*}} %V16i16 = sdiv
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%V16i16 = sdiv <16 x i16> undef, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
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; SSE: cost of 24 {{.*}} %V32i16 = sdiv
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; AVX1: cost of 24 {{.*}} %V32i16 = sdiv
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; AVX1: cost of 28 {{.*}} %V32i16 = sdiv
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; AVX2: cost of 12 {{.*}} %V32i16 = sdiv
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; AVX512F: cost of 12 {{.*}} %V32i16 = sdiv
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; AVX512BW: cost of 6 {{.*}} %V32i16 = sdiv
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@ -203,12 +203,12 @@ define i32 @udiv_uniformconst() {
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; AVX: cost of 15 {{.*}} %V4i32 = udiv
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%V4i32 = udiv <4 x i32> undef, <i32 7, i32 7, i32 7, i32 7>
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; SSE: cost of 30 {{.*}} %V8i32 = udiv
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; AVX1: cost of 30 {{.*}} %V8i32 = udiv
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; AVX1: cost of 32 {{.*}} %V8i32 = udiv
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; AVX2: cost of 15 {{.*}} %V8i32 = udiv
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; AVX512: cost of 15 {{.*}} %V8i32 = udiv
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%V8i32 = udiv <8 x i32> undef, <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>
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; SSE: cost of 60 {{.*}} %V16i32 = udiv
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; AVX1: cost of 60 {{.*}} %V16i32 = udiv
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; AVX1: cost of 64 {{.*}} %V16i32 = udiv
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; AVX2: cost of 30 {{.*}} %V16i32 = udiv
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; AVX512: cost of 15 {{.*}} %V16i32 = udiv
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%V16i32 = udiv <16 x i32> undef, <i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7, i32 7>
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@ -219,12 +219,12 @@ define i32 @udiv_uniformconst() {
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; AVX: cost of 6 {{.*}} %V8i16 = udiv
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%V8i16 = udiv <8 x i16> undef, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
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; SSE: cost of 12 {{.*}} %V16i16 = udiv
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; AVX1: cost of 12 {{.*}} %V16i16 = udiv
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; AVX1: cost of 14 {{.*}} %V16i16 = udiv
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; AVX2: cost of 6 {{.*}} %V16i16 = udiv
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; AVX512: cost of 6 {{.*}} %V16i16 = udiv
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%V16i16 = udiv <16 x i16> undef, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
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; SSE: cost of 24 {{.*}} %V32i16 = udiv
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; AVX1: cost of 24 {{.*}} %V32i16 = udiv
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; AVX1: cost of 28 {{.*}} %V32i16 = udiv
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; AVX2: cost of 12 {{.*}} %V32i16 = udiv
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; AVX512F: cost of 12 {{.*}} %V32i16 = udiv
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; AVX512BW: cost of 6 {{.*}} %V32i16 = udiv
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@ -269,14 +269,14 @@ define i32 @sdiv_uniformconstpow2() {
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; SSE2: cost of 38 {{.*}} %V8i32 = sdiv
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; SSSE3: cost of 38 {{.*}} %V8i32 = sdiv
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; SSE42: cost of 30 {{.*}} %V8i32 = sdiv
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; AVX1: cost of 30 {{.*}} %V8i32 = sdiv
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; AVX1: cost of 32 {{.*}} %V8i32 = sdiv
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; AVX2: cost of 15 {{.*}} %V8i32 = sdiv
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; AVX512: cost of 15 {{.*}} %V8i32 = sdiv
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%V8i32 = sdiv <8 x i32> undef, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
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; SSE2: cost of 76 {{.*}} %V16i32 = sdiv
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; SSSE3: cost of 76 {{.*}} %V16i32 = sdiv
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; SSE42: cost of 60 {{.*}} %V16i32 = sdiv
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; AVX1: cost of 60 {{.*}} %V16i32 = sdiv
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; AVX1: cost of 64 {{.*}} %V16i32 = sdiv
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; AVX2: cost of 30 {{.*}} %V16i32 = sdiv
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; AVX512: cost of 15 {{.*}} %V16i32 = sdiv
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%V16i32 = sdiv <16 x i32> undef, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
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@ -287,12 +287,12 @@ define i32 @sdiv_uniformconstpow2() {
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; AVX: cost of 6 {{.*}} %V8i16 = sdiv
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%V8i16 = sdiv <8 x i16> undef, <i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16>
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; SSE: cost of 12 {{.*}} %V16i16 = sdiv
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; AVX1: cost of 12 {{.*}} %V16i16 = sdiv
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; AVX1: cost of 14 {{.*}} %V16i16 = sdiv
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; AVX2: cost of 6 {{.*}} %V16i16 = sdiv
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; AVX512: cost of 6 {{.*}} %V16i16 = sdiv
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%V16i16 = sdiv <16 x i16> undef, <i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16>
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; SSE: cost of 24 {{.*}} %V32i16 = sdiv
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; AVX1: cost of 24 {{.*}} %V32i16 = sdiv
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; AVX1: cost of 28 {{.*}} %V32i16 = sdiv
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; AVX2: cost of 12 {{.*}} %V32i16 = sdiv
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; AVX512F: cost of 12 {{.*}} %V32i16 = sdiv
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; AVX512BW: cost of 6 {{.*}} %V32i16 = sdiv
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@ -333,12 +333,12 @@ define i32 @udiv_uniformconstpow2() {
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; AVX: cost of 15 {{.*}} %V4i32 = udiv
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%V4i32 = udiv <4 x i32> undef, <i32 16, i32 16, i32 16, i32 16>
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; SSE: cost of 30 {{.*}} %V8i32 = udiv
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; AVX1: cost of 30 {{.*}} %V8i32 = udiv
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; AVX1: cost of 32 {{.*}} %V8i32 = udiv
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; AVX2: cost of 15 {{.*}} %V8i32 = udiv
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; AVX512: cost of 15 {{.*}} %V8i32 = udiv
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%V8i32 = udiv <8 x i32> undef, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
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; SSE: cost of 60 {{.*}} %V16i32 = udiv
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; AVX1: cost of 60 {{.*}} %V16i32 = udiv
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; AVX1: cost of 64 {{.*}} %V16i32 = udiv
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; AVX2: cost of 30 {{.*}} %V16i32 = udiv
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; AVX512: cost of 15 {{.*}} %V16i32 = udiv
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%V16i32 = udiv <16 x i32> undef, <i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16, i32 16>
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@ -349,12 +349,12 @@ define i32 @udiv_uniformconstpow2() {
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; AVX: cost of 6 {{.*}} %V8i16 = udiv
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%V8i16 = udiv <8 x i16> undef, <i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16>
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; SSE: cost of 12 {{.*}} %V16i16 = udiv
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; AVX1: cost of 12 {{.*}} %V16i16 = udiv
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; AVX1: cost of 14 {{.*}} %V16i16 = udiv
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; AVX2: cost of 6 {{.*}} %V16i16 = udiv
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; AVX512: cost of 6 {{.*}} %V16i16 = udiv
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%V16i16 = udiv <16 x i16> undef, <i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16>
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; SSE: cost of 24 {{.*}} %V32i16 = udiv
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; AVX1: cost of 24 {{.*}} %V32i16 = udiv
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; AVX1: cost of 28 {{.*}} %V32i16 = udiv
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; AVX2: cost of 12 {{.*}} %V32i16 = udiv
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; AVX512F: cost of 12 {{.*}} %V32i16 = udiv
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; AVX512BW: cost of 6 {{.*}} %V32i16 = udiv
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