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[AArch64] Remove inexistent system register ERXTS_EL1 

Summary:
AArch64's system register ERXTS_EL1 is present in the backend as a
component of the Arm Reliability, Availability and Serviceability (RAS)
extension. However, it has been removed from the specification before
its final release.

This patch removes the register.

Reviewers: SjoerdMeijer, DavidSpickett

Reviewed By: DavidSpickett

Subscribers: DavidSpickett, kristof.beyls, hiraditya, danielkiss, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D79007
This commit is contained in:
Victor Campos 2020-04-15 16:51:00 +01:00
parent e61247c0a8
commit d3dc4c32af
3 changed files with 0 additions and 13 deletions
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1
llvm/lib/Target/AArch64/AArch64SystemOperands.td
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@ -1331,7 +1331,6 @@ def : RWSysReg<"PMMIR_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b110>;
let Requires = [{ {AArch64::FeatureRASv8_4} }] in {
def : RWSysReg<"ERXPFGCTL_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b101>;
def : RWSysReg<"ERXPFGCDN_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b110>;
def : RWSysReg<"ERXTS_EL1", 0b11, 0b000, 0b0101, 0b0101, 0b111>;
def : RWSysReg<"ERXMISC2_EL1", 0b11, 0b000, 0b0101, 0b0101, 0b010>;
def : RWSysReg<"ERXMISC3_EL1", 0b11, 0b000, 0b0101, 0b0101, 0b011>;
def : ROSysReg<"ERXPFGF_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b100>;

8
llvm/test/MC/AArch64/armv8.4a-ras.s
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@ -23,14 +23,6 @@
//CHECK: msr ERXPFGCDN_EL1, x0 // encoding: [0xc0,0x54,0x18,0xd5]
//CHECK: mrs x0, ERXPFGCDN_EL1 // encoding: [0xc0,0x54,0x38,0xd5]
//CHECK-ERROR: error: expected writable system register or pstate
//CHECK-ERROR: error: expected readable system register
msr ERXTS_EL1, x0
mrs x0,ERXTS_EL1
//CHECK: msr ERXTS_EL1, x0 // encoding: [0xe0,0x55,0x18,0xd5]
//CHECK: mrs x0, ERXTS_EL1 // encoding: [0xe0,0x55,0x38,0xd5]
//CHECK-ERROR: error: expected writable system register or pstate
//CHECK-ERROR: error: expected readable system register
msr ERXMISC2_EL1, x0

4
llvm/test/MC/Disassembler/AArch64/armv8.4a-ras.txt
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@ -4,8 +4,6 @@
0xa0,0x54,0x38,0xd5
0xc0,0x54,0x18,0xd5
0xc0,0x54,0x38,0xd5
0xe0,0x55,0x18,0xd5
0xe0,0x55,0x38,0xd5
0x80,0x54,0x38,0xd5
0x40,0x55,0x18,0xd5
@ -17,8 +15,6 @@
#CHECK: mrs x0, ERXPFGCTL_EL1
#CHECK: msr ERXPFGCDN_EL1, x0
#CHECK: mrs x0, ERXPFGCDN_EL1
#CHECK: msr ERXTS_EL1, x0
#CHECK: mrs x0, ERXTS_EL1
#CHECK: mrs x0, ERXPFGF_EL1
#CHECK: msr ERXMISC2_EL1, x0