forked from OSchip/llvm-project
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62c5b5713c
commit
d3ab37cfeb
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@ -17943,12 +17943,12 @@ static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG,
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MachineFunction &MF = DAG.getMachineFunction();
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bool OptForSize = MF.getFunction()->getAttributes().
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hasAttribute(AttributeSet::FunctionIndex, Attribute::OptimizeForSize);
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// SHLD/SHRD instructions have lower register pressure, but on some
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// platforms they have higher latency than the equivalent
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// series of shifts/or that would otherwise be generated.
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// SHLD/SHRD instructions have lower register pressure, but on some
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// platforms they have higher latency than the equivalent
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// series of shifts/or that would otherwise be generated.
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// Don't fold (or (x << c) | (y >> (64 - c))) if SHLD/SHRD instructions
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// have higer latencies and we are not optimizing for size.
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// have higher latencies and we are not optimizing for size.
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if (!OptForSize && Subtarget->isSHLDSlow())
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return SDValue();
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