forked from OSchip/llvm-project
parent
daa72f5120
commit
d399d94837
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@ -2154,7 +2154,7 @@ SDValue DAGCombiner::visitSDIV(SDNode *N) {
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return DAG.getNode(ISD::SUB, SDLoc(N), VT, DAG.getConstant(0, VT), SRA);
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}
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// if integer divide is expensive and we satisfy the requirements, emit an
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// If integer divide is expensive and we satisfy the requirements, emit an
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// alternate sequence.
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if (N1C && !TLI.isIntDivCheap()) {
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SDValue Op = BuildSDIV(N);
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@ -2449,8 +2449,8 @@ SDValue DAGCombiner::visitSMUL_LOHI(SDNode *N) {
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EVT VT = N->getValueType(0);
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SDLoc DL(N);
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// If the type twice as wide is legal, transform the mulhu to a wider multiply
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// plus a shift.
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// If the type is twice as wide is legal, transform the mulhu to a wider
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// multiply plus a shift.
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if (VT.isSimple() && !VT.isVector()) {
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MVT Simple = VT.getSimpleVT();
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unsigned SimpleSize = Simple.getSizeInBits();
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@ -2479,8 +2479,8 @@ SDValue DAGCombiner::visitUMUL_LOHI(SDNode *N) {
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EVT VT = N->getValueType(0);
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SDLoc DL(N);
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// If the type twice as wide is legal, transform the mulhu to a wider multiply
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// plus a shift.
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// If the type is twice as wide is legal, transform the mulhu to a wider
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// multiply plus a shift.
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if (VT.isSimple() && !VT.isVector()) {
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MVT Simple = VT.getSimpleVT();
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unsigned SimpleSize = Simple.getSizeInBits();
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