forked from OSchip/llvm-project
Better interface to generating machine instr for common cases
(many places still need to be updated to use this interface). llvm-svn: 2648
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@ -92,6 +92,133 @@ void Set3OperandsFromInstr (MachineInstr* minstr,
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int resultPosition = 2);
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//------------------------------------------------------------------------
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// Common machine instruction operand combinations
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// to simplify code generation.
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//------------------------------------------------------------------------
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inline MachineInstr*
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Create1OperandInstr(MachineOpCode opCode, Value* argVal1)
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{
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MachineInstr* M = new MachineInstr(opCode);
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M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, argVal1);
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return M;
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}
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inline MachineInstr*
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Create2OperandInstr(MachineOpCode opCode, Value* argVal1, Value* argVal2)
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{
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MachineInstr* M = new MachineInstr(opCode);
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M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, argVal1);
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M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, argVal2);
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return M;
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}
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inline MachineInstr*
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Create2OperandInstr_UImmed(MachineOpCode opCode,
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unsigned int unextendedImmed, Value* argVal2)
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{
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MachineInstr* M = new MachineInstr(opCode);
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M->SetMachineOperandConst(0, MachineOperand::MO_UnextendedImmed,
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unextendedImmed);
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M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, argVal2);
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return M;
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}
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inline MachineInstr*
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Create2OperandInstr_SImmed(MachineOpCode opCode,
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int signExtendedImmed, Value* argVal2)
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{
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MachineInstr* M = new MachineInstr(opCode);
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M->SetMachineOperandConst(0, MachineOperand::MO_SignExtendedImmed,
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signExtendedImmed);
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M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, argVal2);
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return M;
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}
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inline MachineInstr*
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Create3OperandInstr(MachineOpCode opCode,
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Value* argVal1, MachineOperand::MachineOperandType type1,
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Value* argVal2, MachineOperand::MachineOperandType type2,
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Value* argVal3, MachineOperand::MachineOperandType type3)
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{
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MachineInstr* M = new MachineInstr(opCode);
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M->SetMachineOperandVal(0, type1, argVal1);
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M->SetMachineOperandVal(1, type2, argVal2);
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M->SetMachineOperandVal(2, type3, argVal3);
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return M;
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}
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inline MachineInstr*
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Create3OperandInstr(MachineOpCode opCode, Value* argVal1,
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Value* argVal2, Value* argVal3)
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{
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return Create3OperandInstr(opCode,
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argVal1, MachineOperand::MO_VirtualRegister,
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argVal2, MachineOperand::MO_VirtualRegister,
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argVal3, MachineOperand::MO_VirtualRegister);
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}
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inline MachineInstr*
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Create3OperandInstr_UImmed(MachineOpCode opCode, Value* argVal1,
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unsigned int unextendedImmed, Value* argVal3)
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{
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MachineInstr* M = new MachineInstr(opCode);
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M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, argVal1);
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M->SetMachineOperandConst(1, MachineOperand::MO_UnextendedImmed,
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unextendedImmed);
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M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, argVal3);
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return M;
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}
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inline MachineInstr*
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Create3OperandInstr_SImmed(MachineOpCode opCode, Value* argVal1,
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int signExtendedImmed, Value* argVal3)
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{
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MachineInstr* M = new MachineInstr(opCode);
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M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, argVal1);
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M->SetMachineOperandConst(1, MachineOperand::MO_SignExtendedImmed,
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signExtendedImmed);
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M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, argVal3);
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return M;
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}
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inline MachineInstr*
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Create3OperandInstr_Reg(MachineOpCode opCode, Value* argVal1,
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unsigned int regNum, Value* argVal3)
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{
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MachineInstr* M = new MachineInstr(opCode);
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M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, argVal1);
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M->SetMachineOperandReg(1, regNum);
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M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, argVal3);
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return M;
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}
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inline MachineInstr*
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Create3OperandInstr_Reg(MachineOpCode opCode, unsigned int regNum1,
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unsigned int regNum2, Value* argVal3)
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{
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MachineInstr* M = new MachineInstr(opCode);
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M->SetMachineOperandReg(0, regNum1);
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M->SetMachineOperandReg(1, regNum2);
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M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, argVal3);
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return M;
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}
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inline MachineInstr*
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Create3OperandInstr_Reg(MachineOpCode opCode, unsigned int regNum1,
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unsigned int regNum2, unsigned int regNum3)
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{
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MachineInstr* M = new MachineInstr(opCode);
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M->SetMachineOperandReg(0, regNum1);
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M->SetMachineOperandReg(1, regNum2);
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M->SetMachineOperandReg(2, regNum3);
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return M;
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}
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//---------------------------------------------------------------------------
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// Function: ChooseRegOrImmed
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//
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