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[RISCV] Add mcountinhibit CSR 

Summary:
The mcountinhibit CSR is defined in the ratified 1.11 version of the privileged
spec.

Reviewers: apazos, asb, lenary, luismarques

Reviewed By: asb

Subscribers: hiraditya, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, sameer.abuasal, evandro, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D82913
This commit is contained in:
Pengxuan Zheng 2020-06-30 14:32:37 -07:00
parent b2aa546b07
commit d36f2c6a6c
2 changed files with 15 additions and 0 deletions
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1
llvm/lib/Target/RISCV/RISCVSystemOperands.td
View File

@ -310,6 +310,7 @@ def: SysReg<"mhpmcounter31h", 0xB9F>;
//===--------------------------
// Machine Counter Setup
//===--------------------------
def : SysReg<"mcountinhibit", 0x320>;
def : SysReg<"mhpmevent3", 0x323>;
def : SysReg<"mhpmevent4", 0x324>;
def : SysReg<"mhpmevent5", 0x325>;

14
llvm/test/MC/RISCV/machine-csr-names.s
View File

@ -849,6 +849,20 @@ csrrs t2, 0xB1F, zero
######################################
# Machine Counter Setup
######################################
# mcountinhibit
# name
# CHECK-INST: csrrs t1, mcountinhibit, zero
# CHECK-ENC: encoding: [0x73,0x23,0x00,0x32]
# CHECK-INST-ALIAS: csrr t1, mcountinhibit
# uimm12
# CHECK-INST: csrrs t2, mcountinhibit, zero
# CHECK-ENC: encoding: [0xf3,0x23,0x00,0x32]
# CHECK-INST-ALIAS: csrr t2, mcountinhibit
# name
csrrs t1, mcountinhibit, zero
# uimm12
csrrs t2, 0x320, zero
# mhpmevent3
# name
# CHECK-INST: csrrs t1, mhpmevent3, zero