[AArch64] NFC: Add test for access to fixed-width stack object when stack has SVE.

In this case, the access would benefit from being accessed from the SP, as that
would avoid the redundant ADDVL, since most of the offset can currently be
folded into the addressing mode.

llvm/test/CodeGen/AArch64/framelayout-sve-fixed-width-access.mir

@@ -0,0 +1,34 @@
+# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+# RUN: llc -mattr=+sve -mtriple=aarch64-none-linux-gnu -start-before=prologepilog %s -o - | FileCheck %s
+
+--- |
+  define aarch64_sve_vector_pcs void @access_large_stack() nounwind { entry: unreachable }
+  ; CHECK-LABEL: access_large_stack:
+  ; CHECK:       // %bb.0: // %entry
+  ; CHECK-NEXT:    stp x29, x30, [sp, #-16]! // 16-byte Folded Spill
+  ; CHECK-NEXT:    mov x29, sp
+  ; CHECK-NEXT:    addvl sp, sp, #-32
+  ; CHECK-NEXT:    addvl sp, sp, #-28
+  ; CHECK-NEXT:    sub sp, sp, #2064
+  ; CHECK-NEXT:    addvl x8, x29, #-32
+  ; CHECK-NEXT:    addvl x8, x8, #-28
+  ; CHECK-NEXT:    ldur x8, [x8, #-16]
+  ; CHECK-NEXT:    addvl sp, sp, #31
+  ; CHECK-NEXT:    addvl sp, sp, #29
+  ; CHECK-NEXT:    add sp, sp, #2064
+  ; CHECK-NEXT:    ldp x29, x30, [sp], #16 // 16-byte Folded Reload
+  ; CHECK-NEXT:    ret
+...
+name: access_large_stack
+frameInfo:
+  maxAlignment:  16
+  isFrameAddressTaken: true
+stack:
+  - { id: 0, stack-id: default, size: 16, alignment: 16 }
+  - { id: 1, stack-id: default, size: 2048, alignment: 16 }
+  - { id: 2, stack-id: scalable-vector, size: 960, alignment: 16 }
+body:             |
+  bb.0.entry:
+    $x8 = LDRXui %stack.0, 0
+    RET_ReallyLR
+---