From d35da7f78a0b0c023ceaa224f2ea5825aa2d18b8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Amaury=20S=C3=A9chet?= Date: Sun, 12 Jun 2022 01:50:41 +0000 Subject: [PATCH] Autogenerate sve-fixed-length-bitselect.ll . NFC --- .../AArch64/sve-fixed-length-bitselect.ll | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-bitselect.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-bitselect.ll index c874a8ee501d..0d484c9324fd 100644 --- a/llvm/test/CodeGen/AArch64/sve-fixed-length-bitselect.ll +++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-bitselect.ll @@ -1,3 +1,4 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s target triple = "aarch64" @@ -10,10 +11,19 @@ target triple = "aarch64" define <8 x i32> @fixed_bitselect_v8i32(<8 x i32>* %pre_cond_ptr, <8 x i32>* %left_ptr, <8 x i32>* %right_ptr) #0 { ; CHECK-LABEL: fixed_bitselect_v8i32: -; CHECK-NOT: bsl {{.*}}, {{.*}}, {{.*}} -; CHECK-NOT: bit {{.*}}, {{.*}}, {{.*}} -; CHECK-NOT: bif {{.*}}, {{.*}}, {{.*}} -; CHECK: ret +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s, vl8 +; CHECK-NEXT: mov z3.s, #-1 // =0xffffffffffffffff +; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0] +; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1] +; CHECK-NEXT: ld1w { z2.s }, p0/z, [x2] +; CHECK-NEXT: add z3.s, z0.s, z3.s +; CHECK-NEXT: subr z0.s, z0.s, #0 // =0x0 +; CHECK-NEXT: and z0.d, z0.d, z1.d +; CHECK-NEXT: and z1.d, z3.d, z2.d +; CHECK-NEXT: orr z0.d, z1.d, z0.d +; CHECK-NEXT: st1w { z0.s }, p0, [x8] +; CHECK-NEXT: ret %pre_cond = load <8 x i32>, <8 x i32>* %pre_cond_ptr %left = load <8 x i32>, <8 x i32>* %left_ptr %right = load <8 x i32>, <8 x i32>* %right_ptr