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Naming consistency. 

llvm-svn: 30878
This commit is contained in:
Evan Cheng 2006-10-11 07:10:22 +00:00
parent ac72dc81f4
commit d35734bd1f
8 changed files with 40 additions and 40 deletions
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12
llvm/include/llvm/CodeGen/SelectionDAGNodes.h
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@ -1383,8 +1383,8 @@ class LoadSDNode : public SDNode {
// ExtType - non-ext, anyext, sext, zext. // ExtType - non-ext, anyext, sext, zext.
ISD::LoadExtType ExtType; ISD::LoadExtType ExtType;
// LoadVT - VT of loaded value before extension. // LoadedVT - VT of loaded value before extension.
MVT::ValueType LoadVT; MVT::ValueType LoadedVT;
// SrcValue - Memory location for alias analysis. // SrcValue - Memory location for alias analysis.
const Value *SrcValue; const Value *SrcValue;
@ -1403,7 +1403,7 @@ protected:
ISD::MemOpAddrMode AM, ISD::LoadExtType ETy, MVT::ValueType LVT, ISD::MemOpAddrMode AM, ISD::LoadExtType ETy, MVT::ValueType LVT,
const Value *SV, int O=0, unsigned Align=1, bool Vol=false) const Value *SV, int O=0, unsigned Align=1, bool Vol=false)
: SDNode(ISD::LOAD, Chain, Ptr, Off), : SDNode(ISD::LOAD, Chain, Ptr, Off),
AddrMode(AM), ExtType(ETy), LoadVT(LVT), SrcValue(SV), SVOffset(O), AddrMode(AM), ExtType(ETy), LoadedVT(LVT), SrcValue(SV), SVOffset(O),
Alignment(Align), IsVolatile(Vol) { Alignment(Align), IsVolatile(Vol) {
assert((Off.getOpcode() == ISD::UNDEF || AddrMode == ISD::POST_INDEXED) && assert((Off.getOpcode() == ISD::UNDEF || AddrMode == ISD::POST_INDEXED) &&
"Only post-indexed load has a non-undef offset operand"); "Only post-indexed load has a non-undef offset operand");
@ -1412,7 +1412,7 @@ protected:
ISD::LoadExtType ETy, MVT::ValueType LVT, ISD::LoadExtType ETy, MVT::ValueType LVT,
const Value *SV, int O=0, unsigned Align=1, bool Vol=false) const Value *SV, int O=0, unsigned Align=1, bool Vol=false)
: SDNode(ISD::LOAD, Chain, Ptr, Off), : SDNode(ISD::LOAD, Chain, Ptr, Off),
AddrMode(ISD::UNINDEXED), ExtType(ETy), LoadVT(LVT), SrcValue(SV), AddrMode(ISD::UNINDEXED), ExtType(ETy), LoadedVT(LVT), SrcValue(SV),
SVOffset(O), Alignment(Align), IsVolatile(Vol) { SVOffset(O), Alignment(Align), IsVolatile(Vol) {
assert((Off.getOpcode() == ISD::UNDEF || AddrMode == ISD::POST_INDEXED) && assert((Off.getOpcode() == ISD::UNDEF || AddrMode == ISD::POST_INDEXED) &&
"Only post-indexed load has a non-undef offset operand"); "Only post-indexed load has a non-undef offset operand");
@ -1424,7 +1424,7 @@ public:
const SDOperand getOffset() const { return getOperand(2); } const SDOperand getOffset() const { return getOperand(2); }
ISD::MemOpAddrMode getAddressingMode() const { return AddrMode; } ISD::MemOpAddrMode getAddressingMode() const { return AddrMode; }
ISD::LoadExtType getExtensionType() const { return ExtType; } ISD::LoadExtType getExtensionType() const { return ExtType; }
MVT::ValueType getLoadVT() const { return LoadVT; } MVT::ValueType getLoadedVT() const { return LoadedVT; }
const Value *getSrcValue() const { return SrcValue; } const Value *getSrcValue() const { return SrcValue; }
int getSrcValueOffset() const { return SVOffset; } int getSrcValueOffset() const { return SVOffset; }
unsigned getAlignment() const { return Alignment; } unsigned getAlignment() const { return Alignment; }
@ -1445,7 +1445,7 @@ class StoreSDNode : public SDNode {
// IsTruncStore - True is the op does a truncation before store. // IsTruncStore - True is the op does a truncation before store.
bool IsTruncStore; bool IsTruncStore;
// StoreVT - VT of the value after truncation. // StoredVT - VT of the value after truncation.
MVT::ValueType StoredVT; MVT::ValueType StoredVT;
// SrcValue - Memory location for alias analysis. // SrcValue - Memory location for alias analysis.

20
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -1077,7 +1077,7 @@ SDOperand DAGCombiner::visitAND(SDNode *N) {
// fold (zext_inreg (extload x)) -> (zextload x) // fold (zext_inreg (extload x)) -> (zextload x)
if (ISD::isEXTLoad(N0.Val)) { if (ISD::isEXTLoad(N0.Val)) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0); LoadSDNode *LN0 = cast<LoadSDNode>(N0);
MVT::ValueType EVT = LN0->getLoadVT(); MVT::ValueType EVT = LN0->getLoadedVT();
// If we zero all the possible extended bits, then we can turn this into // If we zero all the possible extended bits, then we can turn this into
// a zextload if we are running before legalize or the operation is legal. // a zextload if we are running before legalize or the operation is legal.
if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
@ -1093,7 +1093,7 @@ SDOperand DAGCombiner::visitAND(SDNode *N) {
// fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use // fold (zext_inreg (sextload x)) -> (zextload x) iff load has one use
if (ISD::isSEXTLoad(N0.Val) && N0.hasOneUse()) { if (ISD::isSEXTLoad(N0.Val) && N0.hasOneUse()) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0); LoadSDNode *LN0 = cast<LoadSDNode>(N0);
MVT::ValueType EVT = LN0->getLoadVT(); MVT::ValueType EVT = LN0->getLoadedVT();
// If we zero all the possible extended bits, then we can turn this into // If we zero all the possible extended bits, then we can turn this into
// a zextload if we are running before legalize or the operation is legal. // a zextload if we are running before legalize or the operation is legal.
if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) && if (TLI.MaskedValueIsZero(N1, ~0ULL << MVT::getSizeInBits(EVT)) &&
@ -1123,7 +1123,7 @@ SDOperand DAGCombiner::visitAND(SDNode *N) {
else else
EVT = MVT::Other; EVT = MVT::Other;
LoadedVT = LN0->getLoadVT(); LoadedVT = LN0->getLoadedVT();
if (EVT != MVT::Other && LoadedVT > EVT && if (EVT != MVT::Other && LoadedVT > EVT &&
(!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) { (!AfterLegalize || TLI.isLoadXLegal(ISD::ZEXTLOAD, EVT))) {
MVT::ValueType PtrType = N0.getOperand(1).getValueType(); MVT::ValueType PtrType = N0.getOperand(1).getValueType();
@ -1874,7 +1874,7 @@ SDOperand DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
// fold (sext ( extload x)) -> (sext (truncate (sextload x))) // fold (sext ( extload x)) -> (sext (truncate (sextload x)))
if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && N0.hasOneUse()) { if ((ISD::isSEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && N0.hasOneUse()) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0); LoadSDNode *LN0 = cast<LoadSDNode>(N0);
MVT::ValueType EVT = LN0->getLoadVT(); MVT::ValueType EVT = LN0->getLoadedVT();
SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
LN0->getBasePtr(), LN0->getSrcValue(), LN0->getBasePtr(), LN0->getSrcValue(),
LN0->getSrcValueOffset(), EVT); LN0->getSrcValueOffset(), EVT);
@ -1943,7 +1943,7 @@ SDOperand DAGCombiner::visitZERO_EXTEND(SDNode *N) {
// fold (zext ( extload x)) -> (zext (truncate (zextload x))) // fold (zext ( extload x)) -> (zext (truncate (zextload x)))
if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && N0.hasOneUse()) { if ((ISD::isZEXTLoad(N0.Val) || ISD::isEXTLoad(N0.Val)) && N0.hasOneUse()) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0); LoadSDNode *LN0 = cast<LoadSDNode>(N0);
MVT::ValueType EVT = LN0->getLoadVT(); MVT::ValueType EVT = LN0->getLoadedVT();
SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(), SDOperand ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, VT, LN0->getChain(),
LN0->getBasePtr(), LN0->getSrcValue(), LN0->getBasePtr(), LN0->getSrcValue(),
LN0->getSrcValueOffset(), EVT); LN0->getSrcValueOffset(), EVT);
@ -2014,7 +2014,7 @@ SDOperand DAGCombiner::visitANY_EXTEND(SDNode *N) {
if (N0.getOpcode() == ISD::LOAD && !ISD::isNON_EXTLoad(N0.Val) && if (N0.getOpcode() == ISD::LOAD && !ISD::isNON_EXTLoad(N0.Val) &&
N0.hasOneUse()) { N0.hasOneUse()) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0); LoadSDNode *LN0 = cast<LoadSDNode>(N0);
MVT::ValueType EVT = LN0->getLoadVT(); MVT::ValueType EVT = LN0->getLoadedVT();
SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT, SDOperand ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), VT,
LN0->getChain(), LN0->getBasePtr(), LN0->getChain(), LN0->getBasePtr(),
LN0->getSrcValue(), LN0->getSrcValue(),
@ -2069,7 +2069,7 @@ SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
// fold (sext_inreg (extload x)) -> (sextload x) // fold (sext_inreg (extload x)) -> (sextload x)
if (ISD::isEXTLoad(N0.Val) && if (ISD::isEXTLoad(N0.Val) &&
EVT == cast<LoadSDNode>(N0)->getLoadVT() && EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
(!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0); LoadSDNode *LN0 = cast<LoadSDNode>(N0);
SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
@ -2081,7 +2081,7 @@ SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
} }
// fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use // fold (sext_inreg (zextload x)) -> (sextload x) iff load has one use
if (ISD::isZEXTLoad(N0.Val) && N0.hasOneUse() && if (ISD::isZEXTLoad(N0.Val) && N0.hasOneUse() &&
EVT == cast<LoadSDNode>(N0)->getLoadVT() && EVT == cast<LoadSDNode>(N0)->getLoadedVT() &&
(!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) { (!AfterLegalize || TLI.isLoadXLegal(ISD::SEXTLOAD, EVT))) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0); LoadSDNode *LN0 = cast<LoadSDNode>(N0);
SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(), SDOperand ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, VT, LN0->getChain(),
@ -3282,7 +3282,7 @@ bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS,
LoadSDNode *RLD = cast<LoadSDNode>(RHS); LoadSDNode *RLD = cast<LoadSDNode>(RHS);
// If this is an EXTLOAD, the VT's must match. // If this is an EXTLOAD, the VT's must match.
if (LLD->getLoadVT() == RLD->getLoadVT()) { if (LLD->getLoadedVT() == RLD->getLoadedVT()) {
// FIXME: this conflates two src values, discarding one. This is not // FIXME: this conflates two src values, discarding one. This is not
// the right thing to do, but nothing uses srcvalues now. When they do, // the right thing to do, but nothing uses srcvalues now. When they do,
// turn SrcValue into a list of locations. // turn SrcValue into a list of locations.
@ -3307,7 +3307,7 @@ bool DAGCombiner::SimplifySelectOps(SDNode *TheSelect, SDOperand LHS,
TheSelect->getValueType(0), TheSelect->getValueType(0),
LLD->getChain(), Addr, LLD->getSrcValue(), LLD->getChain(), Addr, LLD->getSrcValue(),
LLD->getSrcValueOffset(), LLD->getSrcValueOffset(),
LLD->getLoadVT()); LLD->getLoadedVT());
} }
// Users of the select now use the result of the load. // Users of the select now use the result of the load.
CombineTo(TheSelect, Load); CombineTo(TheSelect, Load);

6
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
View File

@ -1364,7 +1364,7 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
AddLegalizedOperand(SDOperand(Node, 1), Tmp4); AddLegalizedOperand(SDOperand(Node, 1), Tmp4);
return Op.ResNo ? Tmp4 : Tmp3; return Op.ResNo ? Tmp4 : Tmp3;
} else { } else {
MVT::ValueType SrcVT = LD->getLoadVT(); MVT::ValueType SrcVT = LD->getLoadedVT();
switch (TLI.getLoadXAction(ExtType, SrcVT)) { switch (TLI.getLoadXAction(ExtType, SrcVT)) {
default: assert(0 && "This action is not supported yet!"); default: assert(0 && "This action is not supported yet!");
case TargetLowering::Promote: case TargetLowering::Promote:
@ -3228,7 +3228,7 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
Result = DAG.getExtLoad(ExtType, NVT, Result = DAG.getExtLoad(ExtType, NVT,
LD->getChain(), LD->getBasePtr(), LD->getChain(), LD->getBasePtr(),
LD->getSrcValue(), LD->getSrcValueOffset(), LD->getSrcValue(), LD->getSrcValueOffset(),
LD->getLoadVT()); LD->getLoadedVT());
// Remember that we legalized the chain. // Remember that we legalized the chain.
AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1))); AddLegalizedOperand(Op.getValue(1), LegalizeOp(Result.getValue(1)));
break; break;
@ -4431,7 +4431,7 @@ void SelectionDAGLegalize::ExpandOp(SDOperand Op, SDOperand &Lo, SDOperand &Hi){
if (!TLI.isLittleEndian()) if (!TLI.isLittleEndian())
std::swap(Lo, Hi); std::swap(Lo, Hi);
} else { } else {
MVT::ValueType EVT = LD->getLoadVT(); MVT::ValueType EVT = LD->getLoadedVT();
if (EVT == NVT) if (EVT == NVT)
Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(), Lo = DAG.getLoad(NVT, Ch, Ptr, LD->getSrcValue(),

4
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -457,7 +457,7 @@ SDNode *SelectionDAG::FindModifiedNodeSlot(SDNode *N,
if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
ID.AddInteger(LD->getAddressingMode()); ID.AddInteger(LD->getAddressingMode());
ID.AddInteger(LD->getExtensionType()); ID.AddInteger(LD->getExtensionType());
ID.AddInteger(LD->getLoadVT()); ID.AddInteger(LD->getLoadedVT());
ID.AddPointer(LD->getSrcValue()); ID.AddPointer(LD->getSrcValue());
ID.AddInteger(LD->getSrcValueOffset()); ID.AddInteger(LD->getSrcValueOffset());
ID.AddInteger(LD->getAlignment()); ID.AddInteger(LD->getAlignment());
@ -2715,7 +2715,7 @@ void SDNode::dump(const SelectionDAG *G) const {
break; break;
} }
if (doExt) if (doExt)
std::cerr << MVT::getValueTypeString(LD->getLoadVT()) << ">"; std::cerr << MVT::getValueTypeString(LD->getLoadedVT()) << ">";
if (LD->getAddressingMode() == ISD::PRE_INDEXED) if (LD->getAddressingMode() == ISD::PRE_INDEXED)
std::cerr << " <pre>"; std::cerr << " <pre>";

2
llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
View File

@ -145,7 +145,7 @@ std::string DOTGraphTraits<SelectionDAG*>::getNodeLabel(const SDNode *Node,
break; break;
} }
if (doExt) if (doExt)
Op = Op + MVT::getValueTypeString(LD->getLoadVT()) + ">"; Op = Op + MVT::getValueTypeString(LD->getLoadedVT()) + ">";
if (LD->getAddressingMode() == ISD::PRE_INDEXED) if (LD->getAddressingMode() == ISD::PRE_INDEXED)
Op = Op + "<pre>"; Op = Op + "<pre>";

8
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
View File

@ -555,7 +555,7 @@ bool TargetLowering::SimplifyDemandedBits(SDOperand Op, uint64_t DemandedMask,
case ISD::LOAD: { case ISD::LOAD: {
if (ISD::isZEXTLoad(Op.Val)) { if (ISD::isZEXTLoad(Op.Val)) {
LoadSDNode *LD = cast<LoadSDNode>(Op); LoadSDNode *LD = cast<LoadSDNode>(Op);
MVT::ValueType VT = LD->getLoadVT(); MVT::ValueType VT = LD->getLoadedVT();
KnownZero |= ~MVT::getIntVTBitMask(VT) & DemandedMask; KnownZero |= ~MVT::getIntVTBitMask(VT) & DemandedMask;
} }
break; break;
@ -896,7 +896,7 @@ void TargetLowering::ComputeMaskedBits(SDOperand Op, uint64_t Mask,
case ISD::LOAD: { case ISD::LOAD: {
if (ISD::isZEXTLoad(Op.Val)) { if (ISD::isZEXTLoad(Op.Val)) {
LoadSDNode *LD = cast<LoadSDNode>(Op); LoadSDNode *LD = cast<LoadSDNode>(Op);
MVT::ValueType VT = LD->getLoadVT(); MVT::ValueType VT = LD->getLoadedVT();
KnownZero |= ~MVT::getIntVTBitMask(VT) & Mask; KnownZero |= ~MVT::getIntVTBitMask(VT) & Mask;
} }
return; return;
@ -1205,10 +1205,10 @@ unsigned TargetLowering::ComputeNumSignBits(SDOperand Op, unsigned Depth) const{
switch (ExtType) { switch (ExtType) {
default: break; default: break;
case ISD::SEXTLOAD: // '17' bits known case ISD::SEXTLOAD: // '17' bits known
Tmp = MVT::getSizeInBits(LD->getLoadVT()); Tmp = MVT::getSizeInBits(LD->getLoadedVT());
return VTBits-Tmp+1; return VTBits-Tmp+1;
case ISD::ZEXTLOAD: // '16' bits known case ISD::ZEXTLOAD: // '16' bits known
Tmp = MVT::getSizeInBits(LD->getLoadVT()); Tmp = MVT::getSizeInBits(LD->getLoadedVT());
return VTBits-Tmp; return VTBits-Tmp;
} }
} }

2
llvm/lib/Target/IA64/IA64ISelDAGToDAG.cpp
View File

@ -460,7 +460,7 @@ SDNode *IA64DAGToDAGISel::Select(SDOperand Op) {
AddToISelQueue(Chain); AddToISelQueue(Chain);
AddToISelQueue(Address); AddToISelQueue(Address);
MVT::ValueType TypeBeingLoaded = LD->getLoadVT(); MVT::ValueType TypeBeingLoaded = LD->getLoadedVT();
unsigned Opc; unsigned Opc;
switch (TypeBeingLoaded) { switch (TypeBeingLoaded) {
default: default:

26
llvm/lib/Target/TargetSelectionDAG.td
View File

@ -411,69 +411,69 @@ def load : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
// extending load & truncstore fragments. // extending load & truncstore fragments.
def extloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{ def extloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (ISD::isEXTLoad(N)) if (ISD::isEXTLoad(N))
return cast<LoadSDNode>(N)->getLoadVT() == MVT::i1; return cast<LoadSDNode>(N)->getLoadedVT() == MVT::i1;
return false; return false;
}]>; }]>;
def extloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{ def extloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (ISD::isEXTLoad(N)) if (ISD::isEXTLoad(N))
return cast<LoadSDNode>(N)->getLoadVT() == MVT::i8; return cast<LoadSDNode>(N)->getLoadedVT() == MVT::i8;
return false; return false;
}]>; }]>;
def extloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{ def extloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (ISD::isEXTLoad(N)) if (ISD::isEXTLoad(N))
return cast<LoadSDNode>(N)->getLoadVT() == MVT::i16; return cast<LoadSDNode>(N)->getLoadedVT() == MVT::i16;
return false; return false;
}]>; }]>;
def extloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{ def extloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (ISD::isEXTLoad(N)) if (ISD::isEXTLoad(N))
return cast<LoadSDNode>(N)->getLoadVT() == MVT::i32; return cast<LoadSDNode>(N)->getLoadedVT() == MVT::i32;
return false; return false;
}]>; }]>;
def extloadf32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{ def extloadf32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (ISD::isEXTLoad(N)) if (ISD::isEXTLoad(N))
return cast<LoadSDNode>(N)->getLoadVT() == MVT::f32; return cast<LoadSDNode>(N)->getLoadedVT() == MVT::f32;
return false; return false;
}]>; }]>;
def sextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{ def sextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (ISD::isSEXTLoad(N)) if (ISD::isSEXTLoad(N))
return cast<LoadSDNode>(N)->getLoadVT() == MVT::i1; return cast<LoadSDNode>(N)->getLoadedVT() == MVT::i1;
return false; return false;
}]>; }]>;
def sextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{ def sextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (ISD::isSEXTLoad(N)) if (ISD::isSEXTLoad(N))
return cast<LoadSDNode>(N)->getLoadVT() == MVT::i8; return cast<LoadSDNode>(N)->getLoadedVT() == MVT::i8;
return false; return false;
}]>; }]>;
def sextloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{ def sextloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (ISD::isSEXTLoad(N)) if (ISD::isSEXTLoad(N))
return cast<LoadSDNode>(N)->getLoadVT() == MVT::i16; return cast<LoadSDNode>(N)->getLoadedVT() == MVT::i16;
return false; return false;
}]>; }]>;
def sextloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{ def sextloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (ISD::isSEXTLoad(N)) if (ISD::isSEXTLoad(N))
return cast<LoadSDNode>(N)->getLoadVT() == MVT::i32; return cast<LoadSDNode>(N)->getLoadedVT() == MVT::i32;
return false; return false;
}]>; }]>;
def zextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{ def zextloadi1 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (ISD::isZEXTLoad(N)) if (ISD::isZEXTLoad(N))
return cast<LoadSDNode>(N)->getLoadVT() == MVT::i1; return cast<LoadSDNode>(N)->getLoadedVT() == MVT::i1;
return false; return false;
}]>; }]>;
def zextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{ def zextloadi8 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (ISD::isZEXTLoad(N)) if (ISD::isZEXTLoad(N))
return cast<LoadSDNode>(N)->getLoadVT() == MVT::i8; return cast<LoadSDNode>(N)->getLoadedVT() == MVT::i8;
return false; return false;
}]>; }]>;
def zextloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{ def zextloadi16 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (ISD::isZEXTLoad(N)) if (ISD::isZEXTLoad(N))
return cast<LoadSDNode>(N)->getLoadVT() == MVT::i16; return cast<LoadSDNode>(N)->getLoadedVT() == MVT::i16;
return false; return false;
}]>; }]>;
def zextloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{ def zextloadi32 : PatFrag<(ops node:$ptr), (ld node:$ptr), [{
if (ISD::isZEXTLoad(N)) if (ISD::isZEXTLoad(N))
return cast<LoadSDNode>(N)->getLoadVT() == MVT::i32; return cast<LoadSDNode>(N)->getLoadedVT() == MVT::i32;
return false; return false;
}]>; }]>;