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Rename DEBUG macro to LLVM_DEBUG. 

The DEBUG() macro is very generic so it might clash with other projects.
The renaming was done as follows:
- git grep -l 'DEBUG' | xargs sed -i 's/\bDEBUG\s\?(/LLVM_DEBUG(/g'
- git diff -U0 master | ../clang/tools/clang-format/clang-format-diff.py -i -p1 -style LLVM
- Manual change to APInt
- Manually chage DOCS as regex doesn't match it.

In the transition period the DEBUG() macro is still present and aliased
to the LLVM_DEBUG() one.

Differential Revision: https://reviews.llvm.org/D43624

llvm-svn: 332240
This commit is contained in:
Nicola Zaghen 2018-05-14 12:53:11 +00:00
parent affbc99bea
commit d34e60ca85
502 changed files with 9319 additions and 8806 deletions
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16
llvm/docs/Bugpoint.rst
View File

@ -198,14 +198,14 @@ desired ranges. For example:
static int calledCount = 0;
calledCount++;
DEBUG(if (calledCount < 212) return false);
DEBUG(if (calledCount > 217) return false);
DEBUG(if (calledCount == 213) return false);
DEBUG(if (calledCount == 214) return false);
DEBUG(if (calledCount == 215) return false);
DEBUG(if (calledCount == 216) return false);
DEBUG(dbgs() << "visitXOR calledCount: " << calledCount << "\n");
DEBUG(dbgs() << "I: "; I->dump());
LLVM_DEBUG(if (calledCount < 212) return false);
LLVM_DEBUG(if (calledCount > 217) return false);
LLVM_DEBUG(if (calledCount == 213) return false);
LLVM_DEBUG(if (calledCount == 214) return false);
LLVM_DEBUG(if (calledCount == 215) return false);
LLVM_DEBUG(if (calledCount == 216) return false);
LLVM_DEBUG(dbgs() << "visitXOR calledCount: " << calledCount << "\n");
LLVM_DEBUG(dbgs() << "I: "; I->dump());
could be added to ``visitXOR`` to limit ``visitXor`` to being applied only to
calls 212 and 217. This is from an actual test case and raises an important

2
llvm/docs/CommandGuide/opt.rst
View File

@ -96,7 +96,7 @@ OPTIONS
.. option:: -debug
If this is a debug build, this option will enable debug printouts from passes
which use the ``DEBUG()`` macro. See the `LLVM Programmer's Manual
which use the ``LLVM_DEBUG()`` macro. See the `LLVM Programmer's Manual
<../ProgrammersManual.html>`_, section ``#DEBUG`` for more information.
.. option:: -load=<plugin>

6
llvm/docs/CommandLine.rst
View File

@ -886,12 +886,12 @@ To do this, set up your .h file with your option, like this for example:
// debug build, then the code specified as the option to the macro will be
// executed. Otherwise it will not be.
#ifdef NDEBUG
#define DEBUG(X)
#define LLVM_DEBUG(X)
#else
#define DEBUG(X) do { if (DebugFlag) { X; } } while (0)
#define LLVM_DEBUG(X) do { if (DebugFlag) { X; } } while (0)
#endif
This allows clients to blissfully use the ``DEBUG()`` macro, or the
This allows clients to blissfully use the ``LLVM_DEBUG()`` macro, or the
``DebugFlag`` explicitly if they want to. Now we just need to be able to set
the ``DebugFlag`` boolean when the option is set. To do this, we pass an
additional argument to our command line argument processor, and we specify where

18
llvm/docs/ProgrammersManual.rst
View File

@ -1020,7 +1020,7 @@ be passed by value.
.. _DEBUG:
The ``DEBUG()`` macro and ``-debug`` option
The ``LLVM_DEBUG()`` macro and ``-debug`` option
-------------------------------------------
Often when working on your pass you will put a bunch of debugging printouts and
@ -1033,14 +1033,14 @@ them out, allowing you to enable them if you need them in the future.
The ``llvm/Support/Debug.h`` (`doxygen
<http://llvm.org/doxygen/Debug_8h_source.html>`__) file provides a macro named
``DEBUG()`` that is a much nicer solution to this problem. Basically, you can
put arbitrary code into the argument of the ``DEBUG`` macro, and it is only
``LLVM_DEBUG()`` that is a much nicer solution to this problem. Basically, you can
put arbitrary code into the argument of the ``LLVM_DEBUG`` macro, and it is only
executed if '``opt``' (or any other tool) is run with the '``-debug``' command
line argument:
.. code-block:: c++
DEBUG(dbgs() << "I am here!\n");
LLVM_DEBUG(dbgs() << "I am here!\n");
Then you can run your pass like this:
@ -1051,13 +1051,13 @@ Then you can run your pass like this:
$ opt < a.bc > /dev/null -mypass -debug
I am here!
Using the ``DEBUG()`` macro instead of a home-brewed solution allows you to not
Using the ``LLVM_DEBUG()`` macro instead of a home-brewed solution allows you to not
have to create "yet another" command line option for the debug output for your
pass. Note that ``DEBUG()`` macros are disabled for non-asserts builds, so they
pass. Note that ``LLVM_DEBUG()`` macros are disabled for non-asserts builds, so they
do not cause a performance impact at all (for the same reason, they should also
not contain side-effects!).
One additional nice thing about the ``DEBUG()`` macro is that you can enable or
One additional nice thing about the ``LLVM_DEBUG()`` macro is that you can enable or
disable it directly in gdb. Just use "``set DebugFlag=0``" or "``set
DebugFlag=1``" from the gdb if the program is running. If the program hasn't
been started yet, you can always just run it with ``-debug``.
@ -1076,10 +1076,10 @@ follows:
.. code-block:: c++
#define DEBUG_TYPE "foo"
DEBUG(dbgs() << "'foo' debug type\n");
LLVM_DEBUG(dbgs() << "'foo' debug type\n");
#undef DEBUG_TYPE
#define DEBUG_TYPE "bar"
DEBUG(dbgs() << "'bar' debug type\n");
LLVM_DEBUG(dbgs() << "'bar' debug type\n");
#undef DEBUG_TYPE
Then you can run your pass like this:

47
llvm/include/llvm/Analysis/BlockFrequencyInfoImpl.h
View File

@ -1030,8 +1030,9 @@ void BlockFrequencyInfoImpl<BT>::calculate(const FunctionT &F,
Nodes.clear();
// Initialize.
DEBUG(dbgs() << "\nblock-frequency: " << F.getName() << "\n================="
<< std::string(F.getName().size(), '=') << "\n");
LLVM_DEBUG(dbgs() << "\nblock-frequency: " << F.getName()
<< "\n================="
<< std::string(F.getName().size(), '=') << "\n");
initializeRPOT();
initializeLoops();
@ -1067,10 +1068,11 @@ template <class BT> void BlockFrequencyInfoImpl<BT>::initializeRPOT() {
assert(RPOT.size() - 1 <= BlockNode::getMaxIndex() &&
"More nodes in function than Block Frequency Info supports");
DEBUG(dbgs() << "reverse-post-order-traversal\n");
LLVM_DEBUG(dbgs() << "reverse-post-order-traversal\n");
for (rpot_iterator I = rpot_begin(), E = rpot_end(); I != E; ++I) {
BlockNode Node = getNode(I);
DEBUG(dbgs() << " - " << getIndex(I) << ": " << getBlockName(Node) << "\n");
LLVM_DEBUG(dbgs() << " - " << getIndex(I) << ": " << getBlockName(Node)
<< "\n");
Nodes[*I] = Node;
}
@ -1081,7 +1083,7 @@ template <class BT> void BlockFrequencyInfoImpl<BT>::initializeRPOT() {
}
template <class BT> void BlockFrequencyInfoImpl<BT>::initializeLoops() {
DEBUG(dbgs() << "loop-detection\n");
LLVM_DEBUG(dbgs() << "loop-detection\n");
if (LI->empty())
return;
@ -1099,7 +1101,7 @@ template <class BT> void BlockFrequencyInfoImpl<BT>::initializeLoops() {
Loops.emplace_back(Parent, Header);
Working[Header.Index].Loop = &Loops.back();
DEBUG(dbgs() << " - loop = " << getBlockName(Header) << "\n");
LLVM_DEBUG(dbgs() << " - loop = " << getBlockName(Header) << "\n");
for (const LoopT *L : *Loop)
Q.emplace_back(L, &Loops.back());
@ -1128,8 +1130,8 @@ template <class BT> void BlockFrequencyInfoImpl<BT>::initializeLoops() {
Working[Index].Loop = HeaderData.Loop;
HeaderData.Loop->Nodes.push_back(Index);
DEBUG(dbgs() << " - loop = " << getBlockName(Header)
<< ": member = " << getBlockName(Index) << "\n");
LLVM_DEBUG(dbgs() << " - loop = " << getBlockName(Header)
<< ": member = " << getBlockName(Index) << "\n");
}
}
@ -1150,10 +1152,10 @@ template <class BT> void BlockFrequencyInfoImpl<BT>::computeMassInLoops() {
template <class BT>
bool BlockFrequencyInfoImpl<BT>::computeMassInLoop(LoopData &Loop) {
// Compute mass in loop.
DEBUG(dbgs() << "compute-mass-in-loop: " << getLoopName(Loop) << "\n");
LLVM_DEBUG(dbgs() << "compute-mass-in-loop: " << getLoopName(Loop) << "\n");
if (Loop.isIrreducible()) {
DEBUG(dbgs() << "isIrreducible = true\n");
LLVM_DEBUG(dbgs() << "isIrreducible = true\n");
Distribution Dist;
unsigned NumHeadersWithWeight = 0;
Optional<uint64_t> MinHeaderWeight;
@ -1165,14 +1167,14 @@ bool BlockFrequencyInfoImpl<BT>::computeMassInLoop(LoopData &Loop) {
IsIrrLoopHeader.set(Loop.Nodes[H].Index);
Optional<uint64_t> HeaderWeight = Block->getIrrLoopHeaderWeight();
if (!HeaderWeight) {
DEBUG(dbgs() << "Missing irr loop header metadata on "
<< getBlockName(HeaderNode) << "\n");
LLVM_DEBUG(dbgs() << "Missing irr loop header metadata on "
<< getBlockName(HeaderNode) << "\n");
HeadersWithoutWeight.insert(H);
continue;
}
DEBUG(dbgs() << getBlockName(HeaderNode)
<< " has irr loop header weight " << HeaderWeight.getValue()
<< "\n");
LLVM_DEBUG(dbgs() << getBlockName(HeaderNode)
<< " has irr loop header weight "
<< HeaderWeight.getValue() << "\n");
NumHeadersWithWeight++;
uint64_t HeaderWeightValue = HeaderWeight.getValue();
if (!MinHeaderWeight || HeaderWeightValue < MinHeaderWeight)
@ -1194,8 +1196,8 @@ bool BlockFrequencyInfoImpl<BT>::computeMassInLoop(LoopData &Loop) {
assert(!getBlock(HeaderNode)->getIrrLoopHeaderWeight() &&
"Shouldn't have a weight metadata");
uint64_t MinWeight = MinHeaderWeight.getValue();
DEBUG(dbgs() << "Giving weight " << MinWeight
<< " to " << getBlockName(HeaderNode) << "\n");
LLVM_DEBUG(dbgs() << "Giving weight " << MinWeight << " to "
<< getBlockName(HeaderNode) << "\n");
if (MinWeight)
Dist.addLocal(HeaderNode, MinWeight);
}
@ -1224,7 +1226,7 @@ bool BlockFrequencyInfoImpl<BT>::computeMassInLoop(LoopData &Loop) {
template <class BT>
bool BlockFrequencyInfoImpl<BT>::tryToComputeMassInFunction() {
// Compute mass in function.
DEBUG(dbgs() << "compute-mass-in-function\n");
LLVM_DEBUG(dbgs() << "compute-mass-in-function\n");
assert(!Working.empty() && "no blocks in function");
assert(!Working[0].isLoopHeader() && "entry block is a loop header");
@ -1276,9 +1278,10 @@ template <class BT> struct BlockEdgesAdder {
template <class BT>
void BlockFrequencyInfoImpl<BT>::computeIrreducibleMass(
LoopData *OuterLoop, std::list<LoopData>::iterator Insert) {
DEBUG(dbgs() << "analyze-irreducible-in-";
if (OuterLoop) dbgs() << "loop: " << getLoopName(*OuterLoop) << "\n";
else dbgs() << "function\n");
LLVM_DEBUG(dbgs() << "analyze-irreducible-in-";
if (OuterLoop) dbgs()
<< "loop: " << getLoopName(*OuterLoop) << "\n";
else dbgs() << "function\n");
using namespace bfi_detail;
@ -1304,7 +1307,7 @@ template <class BT>
bool
BlockFrequencyInfoImpl<BT>::propagateMassToSuccessors(LoopData *OuterLoop,
const BlockNode &Node) {
DEBUG(dbgs() << " - node: " << getBlockName(Node) << "\n");
LLVM_DEBUG(dbgs() << " - node: " << getBlockName(Node) << "\n");
// Calculate probability for successors.
Distribution Dist;
if (auto *Loop = Working[Node.Index].getPackagedLoop()) {

46
llvm/include/llvm/Analysis/CGSCCPassManager.h
View File

@ -387,15 +387,15 @@ public:
do {
LazyCallGraph::RefSCC *RC = RCWorklist.pop_back_val();
if (InvalidRefSCCSet.count(RC)) {
DEBUG(dbgs() << "Skipping an invalid RefSCC...\n");
LLVM_DEBUG(dbgs() << "Skipping an invalid RefSCC...\n");
continue;
}
assert(CWorklist.empty() &&
"Should always start with an empty SCC worklist");
DEBUG(dbgs() << "Running an SCC pass across the RefSCC: " << *RC
<< "\n");
LLVM_DEBUG(dbgs() << "Running an SCC pass across the RefSCC: " << *RC
<< "\n");
// Push the initial SCCs in reverse post-order as we'll pop off the
// back and so see this in post-order.
@ -409,12 +409,13 @@ public:
// other RefSCCs should be queued above, so we just need to skip both
// scenarios here.
if (InvalidSCCSet.count(C)) {
DEBUG(dbgs() << "Skipping an invalid SCC...\n");
LLVM_DEBUG(dbgs() << "Skipping an invalid SCC...\n");
continue;
}
if (&C->getOuterRefSCC() != RC) {
DEBUG(dbgs() << "Skipping an SCC that is now part of some other "
"RefSCC...\n");
LLVM_DEBUG(dbgs()
<< "Skipping an SCC that is now part of some other "
"RefSCC...\n");
continue;
}
@ -436,7 +437,8 @@ public:
// If the CGSCC pass wasn't able to provide a valid updated SCC,
// the current SCC may simply need to be skipped if invalid.
if (UR.InvalidatedSCCs.count(C)) {
DEBUG(dbgs() << "Skipping invalidated root or island SCC!\n");
LLVM_DEBUG(dbgs()
<< "Skipping invalidated root or island SCC!\n");
break;
}
// Check that we didn't miss any update scenario.
@ -464,9 +466,10 @@ public:
// FIXME: If we ever start having RefSCC passes, we'll want to
// iterate there too.
if (UR.UpdatedC)
DEBUG(dbgs() << "Re-running SCC passes after a refinement of the "
"current SCC: "
<< *UR.UpdatedC << "\n");
LLVM_DEBUG(dbgs()
<< "Re-running SCC passes after a refinement of the "
"current SCC: "
<< *UR.UpdatedC << "\n");
// Note that both `C` and `RC` may at this point refer to deleted,
// invalid SCC and RefSCCs respectively. But we will short circuit
@ -601,7 +604,8 @@ public:
// a pointer we can overwrite.
LazyCallGraph::SCC *CurrentC = &C;
DEBUG(dbgs() << "Running function passes across an SCC: " << C << "\n");
LLVM_DEBUG(dbgs() << "Running function passes across an SCC: " << C
<< "\n");
PreservedAnalyses PA = PreservedAnalyses::all();
for (LazyCallGraph::Node *N : Nodes) {
@ -757,9 +761,9 @@ public:
if (!F)
return false;
DEBUG(dbgs() << "Found devirutalized call from "
<< CS.getParent()->getParent()->getName() << " to "
<< F->getName() << "\n");
LLVM_DEBUG(dbgs() << "Found devirutalized call from "
<< CS.getParent()->getParent()->getName() << " to "
<< F->getName() << "\n");
// We now have a direct call where previously we had an indirect call,
// so iterate to process this devirtualization site.
@ -793,16 +797,18 @@ public:
// Otherwise, if we've already hit our max, we're done.
if (Iteration >= MaxIterations) {
DEBUG(dbgs() << "Found another devirtualization after hitting the max "
"number of repetitions ("
<< MaxIterations << ") on SCC: " << *C << "\n");
LLVM_DEBUG(
dbgs() << "Found another devirtualization after hitting the max "
"number of repetitions ("
<< MaxIterations << ") on SCC: " << *C << "\n");
PA.intersect(std::move(PassPA));
break;
}
DEBUG(dbgs()
<< "Repeating an SCC pass after finding a devirtualization in: "
<< *C << "\n");
LLVM_DEBUG(
dbgs()
<< "Repeating an SCC pass after finding a devirtualization in: " << *C
<< "\n");
// Move over the new call counts in preparation for iterating.
CallCounts = std::move(NewCallCounts);

2
llvm/include/llvm/Analysis/RegionInfoImpl.h
View File

@ -675,7 +675,7 @@ typename Tr::RegionT *RegionInfoBase<Tr>::createRegion(BlockT *entry,
#ifdef EXPENSIVE_CHECKS
region->verifyRegion();
#else
DEBUG(region->verifyRegion());
LLVM_DEBUG(region->verifyRegion());
#endif
updateStatistics(region);

10
llvm/include/llvm/Analysis/SparsePropagation.h
View File

@ -260,7 +260,7 @@ void SparseSolver<LatticeKey, LatticeVal, KeyInfo>::MarkBlockExecutable(
BasicBlock *BB) {
if (!BBExecutable.insert(BB).second)
return;
DEBUG(dbgs() << "Marking Block Executable: " << BB->getName() << "\n");
LLVM_DEBUG(dbgs() << "Marking Block Executable: " << BB->getName() << "\n");
BBWorkList.push_back(BB); // Add the block to the work list!
}
@ -270,8 +270,8 @@ void SparseSolver<LatticeKey, LatticeVal, KeyInfo>::markEdgeExecutable(
if (!KnownFeasibleEdges.insert(Edge(Source, Dest)).second)
return; // This edge is already known to be executable!
DEBUG(dbgs() << "Marking Edge Executable: " << Source->getName() << " -> "
<< Dest->getName() << "\n");
LLVM_DEBUG(dbgs() << "Marking Edge Executable: " << Source->getName()
<< " -> " << Dest->getName() << "\n");
if (BBExecutable.count(Dest)) {
// The destination is already executable, but we just made an edge
@ -477,7 +477,7 @@ void SparseSolver<LatticeKey, LatticeVal, KeyInfo>::Solve() {
Value *V = ValueWorkList.back();
ValueWorkList.pop_back();
DEBUG(dbgs() << "\nPopped off V-WL: " << *V << "\n");
LLVM_DEBUG(dbgs() << "\nPopped off V-WL: " << *V << "\n");
// "V" got into the work list because it made a transition. See if any
// users are both live and in need of updating.
@ -492,7 +492,7 @@ void SparseSolver<LatticeKey, LatticeVal, KeyInfo>::Solve() {
BasicBlock *BB = BBWorkList.back();
BBWorkList.pop_back();
DEBUG(dbgs() << "\nPopped off BBWL: " << *BB);
LLVM_DEBUG(dbgs() << "\nPopped off BBWL: " << *BB);
// Notify all instructions in this basic block that they are newly
// executable.

8
llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
View File

@ -38,7 +38,7 @@ public:
return false;
if (MachineInstr *DefMI = getOpcodeDef(TargetOpcode::G_TRUNC,
MI.getOperand(1).getReg(), MRI)) {
DEBUG(dbgs() << ".. Combine MI: " << MI;);
LLVM_DEBUG(dbgs() << ".. Combine MI: " << MI;);
unsigned DstReg = MI.getOperand(0).getReg();
unsigned SrcReg = DefMI->getOperand(1).getReg();
Builder.setInstr(MI);
@ -62,7 +62,7 @@ public:
if (isInstUnsupported({TargetOpcode::G_AND, {DstTy}}) ||
isInstUnsupported({TargetOpcode::G_CONSTANT, {DstTy}}))
return false;
DEBUG(dbgs() << ".. Combine MI: " << MI;);
LLVM_DEBUG(dbgs() << ".. Combine MI: " << MI;);
Builder.setInstr(MI);
unsigned ZExtSrc = MI.getOperand(1).getReg();
LLT ZExtSrcTy = MRI.getType(ZExtSrc);
@ -91,7 +91,7 @@ public:
isInstUnsupported({TargetOpcode::G_ASHR, {DstTy}}) ||
isInstUnsupported({TargetOpcode::G_CONSTANT, {DstTy}}))
return false;
DEBUG(dbgs() << ".. Combine MI: " << MI;);
LLVM_DEBUG(dbgs() << ".. Combine MI: " << MI;);
Builder.setInstr(MI);
unsigned SExtSrc = MI.getOperand(1).getReg();
LLT SExtSrcTy = MRI.getType(SExtSrc);
@ -123,7 +123,7 @@ public:
LLT DstTy = MRI.getType(DstReg);
if (isInstUnsupported({TargetOpcode::G_IMPLICIT_DEF, {DstTy}}))
return false;
DEBUG(dbgs() << ".. Combine EXT(IMPLICIT_DEF) " << MI;);
LLVM_DEBUG(dbgs() << ".. Combine EXT(IMPLICIT_DEF) " << MI;);
Builder.setInstr(MI);
Builder.buildInstr(TargetOpcode::G_IMPLICIT_DEF, DstReg);
markInstAndDefDead(MI, *DefMI, DeadInsts);

89
llvm/include/llvm/ExecutionEngine/Orc/OrcRemoteTargetClient.h
View File

@ -63,7 +63,7 @@ public:
public:
~RemoteRTDyldMemoryManager() {
Client.destroyRemoteAllocator(Id);
DEBUG(dbgs() << "Destroyed remote allocator " << Id << "\n");
LLVM_DEBUG(dbgs() << "Destroyed remote allocator " << Id << "\n");
}
RemoteRTDyldMemoryManager(const RemoteRTDyldMemoryManager &) = delete;
@ -79,9 +79,9 @@ public:
Unmapped.back().CodeAllocs.emplace_back(Size, Alignment);
uint8_t *Alloc = reinterpret_cast<uint8_t *>(
Unmapped.back().CodeAllocs.back().getLocalAddress());
DEBUG(dbgs() << "Allocator " << Id << " allocated code for "
<< SectionName << ": " << Alloc << " (" << Size
<< " bytes, alignment " << Alignment << ")\n");
LLVM_DEBUG(dbgs() << "Allocator " << Id << " allocated code for "
<< SectionName << ": " << Alloc << " (" << Size
<< " bytes, alignment " << Alignment << ")\n");
return Alloc;
}
@ -92,18 +92,18 @@ public:
Unmapped.back().RODataAllocs.emplace_back(Size, Alignment);
uint8_t *Alloc = reinterpret_cast<uint8_t *>(
Unmapped.back().RODataAllocs.back().getLocalAddress());
DEBUG(dbgs() << "Allocator " << Id << " allocated ro-data for "
<< SectionName << ": " << Alloc << " (" << Size
<< " bytes, alignment " << Alignment << ")\n");
LLVM_DEBUG(dbgs() << "Allocator " << Id << " allocated ro-data for "
<< SectionName << ": " << Alloc << " (" << Size
<< " bytes, alignment " << Alignment << ")\n");
return Alloc;
} // else...
Unmapped.back().RWDataAllocs.emplace_back(Size, Alignment);
uint8_t *Alloc = reinterpret_cast<uint8_t *>(
Unmapped.back().RWDataAllocs.back().getLocalAddress());
DEBUG(dbgs() << "Allocator " << Id << " allocated rw-data for "
<< SectionName << ": " << Alloc << " (" << Size
<< " bytes, alignment " << Alignment << ")\n");
LLVM_DEBUG(dbgs() << "Allocator " << Id << " allocated rw-data for "
<< SectionName << ": " << Alloc << " (" << Size
<< " bytes, alignment " << Alignment << ")\n");
return Alloc;
}
@ -113,36 +113,36 @@ public:
uint32_t RWDataAlign) override {
Unmapped.push_back(ObjectAllocs());
DEBUG(dbgs() << "Allocator " << Id << " reserved:\n");
LLVM_DEBUG(dbgs() << "Allocator " << Id << " reserved:\n");
if (CodeSize != 0) {
Unmapped.back().RemoteCodeAddr =
Client.reserveMem(Id, CodeSize, CodeAlign);
DEBUG(dbgs() << " code: "
<< format("0x%016x", Unmapped.back().RemoteCodeAddr)
<< " (" << CodeSize << " bytes, alignment " << CodeAlign
<< ")\n");
LLVM_DEBUG(dbgs() << " code: "
<< format("0x%016x", Unmapped.back().RemoteCodeAddr)
<< " (" << CodeSize << " bytes, alignment "
<< CodeAlign << ")\n");
}
if (RODataSize != 0) {
Unmapped.back().RemoteRODataAddr =
Client.reserveMem(Id, RODataSize, RODataAlign);
DEBUG(dbgs() << " ro-data: "
<< format("0x%016x", Unmapped.back().RemoteRODataAddr)
<< " (" << RODataSize << " bytes, alignment "
<< RODataAlign << ")\n");
LLVM_DEBUG(dbgs() << " ro-data: "
<< format("0x%016x", Unmapped.back().RemoteRODataAddr)
<< " (" << RODataSize << " bytes, alignment "
<< RODataAlign << ")\n");
}
if (RWDataSize != 0) {
Unmapped.back().RemoteRWDataAddr =
Client.reserveMem(Id, RWDataSize, RWDataAlign);
DEBUG(dbgs() << " rw-data: "
<< format("0x%016x", Unmapped.back().RemoteRWDataAddr)
<< " (" << RWDataSize << " bytes, alignment "
<< RWDataAlign << ")\n");
LLVM_DEBUG(dbgs() << " rw-data: "
<< format("0x%016x", Unmapped.back().RemoteRWDataAddr)
<< " (" << RWDataSize << " bytes, alignment "
<< RWDataAlign << ")\n");
}
}
@ -162,7 +162,7 @@ public:
void notifyObjectLoaded(RuntimeDyld &Dyld,
const object::ObjectFile &Obj) override {
DEBUG(dbgs() << "Allocator " << Id << " applied mappings:\n");
LLVM_DEBUG(dbgs() << "Allocator " << Id << " applied mappings:\n");
for (auto &ObjAllocs : Unmapped) {
mapAllocsToRemoteAddrs(Dyld, ObjAllocs.CodeAllocs,
ObjAllocs.RemoteCodeAddr);
@ -176,7 +176,7 @@ public:
}
bool finalizeMemory(std::string *ErrMsg = nullptr) override {
DEBUG(dbgs() << "Allocator " << Id << " finalizing:\n");
LLVM_DEBUG(dbgs() << "Allocator " << Id << " finalizing:\n");
for (auto &ObjAllocs : Unfinalized) {
if (copyAndProtect(ObjAllocs.CodeAllocs, ObjAllocs.RemoteCodeAddr,
@ -261,7 +261,7 @@ public:
RemoteRTDyldMemoryManager(OrcRemoteTargetClient &Client,
ResourceIdMgr::ResourceId Id)
: Client(Client), Id(Id) {
DEBUG(dbgs() << "Created remote allocator " << Id << "\n");
LLVM_DEBUG(dbgs() << "Created remote allocator " << Id << "\n");
}
// Maps all allocations in Allocs to aligned blocks
@ -270,8 +270,9 @@ public:
for (auto &Alloc : Allocs) {
NextAddr = alignTo(NextAddr, Alloc.getAlign());
Dyld.mapSectionAddress(Alloc.getLocalAddress(), NextAddr);
DEBUG(dbgs() << " " << static_cast<void *>(Alloc.getLocalAddress())
<< " -> " << format("0x%016x", NextAddr) << "\n");
LLVM_DEBUG(dbgs() << " "
<< static_cast<void *>(Alloc.getLocalAddress())
<< " -> " << format("0x%016x", NextAddr) << "\n");
Alloc.setRemoteAddress(NextAddr);
// Only advance NextAddr if it was non-null to begin with,
@ -290,22 +291,23 @@ public:
assert(!Allocs.empty() && "No sections in allocated segment");
for (auto &Alloc : Allocs) {
DEBUG(dbgs() << " copying section: "
<< static_cast<void *>(Alloc.getLocalAddress()) << " -> "
<< format("0x%016x", Alloc.getRemoteAddress()) << " ("
<< Alloc.getSize() << " bytes)\n";);
LLVM_DEBUG(dbgs() << " copying section: "
<< static_cast<void *>(Alloc.getLocalAddress())
<< " -> "
<< format("0x%016x", Alloc.getRemoteAddress())
<< " (" << Alloc.getSize() << " bytes)\n";);
if (Client.writeMem(Alloc.getRemoteAddress(), Alloc.getLocalAddress(),
Alloc.getSize()))
return true;
}
DEBUG(dbgs() << " setting "
<< (Permissions & sys::Memory::MF_READ ? 'R' : '-')
<< (Permissions & sys::Memory::MF_WRITE ? 'W' : '-')
<< (Permissions & sys::Memory::MF_EXEC ? 'X' : '-')
<< " permissions on block: "
<< format("0x%016x", RemoteSegmentAddr) << "\n");
LLVM_DEBUG(dbgs() << " setting "
<< (Permissions & sys::Memory::MF_READ ? 'R' : '-')
<< (Permissions & sys::Memory::MF_WRITE ? 'W' : '-')
<< (Permissions & sys::Memory::MF_EXEC ? 'X' : '-')
<< " permissions on block: "
<< format("0x%016x", RemoteSegmentAddr) << "\n");
if (Client.setProtections(Id, RemoteSegmentAddr, Permissions))
return true;
}
@ -487,7 +489,8 @@ public:
/// Call the int(void) function at the given address in the target and return
/// its result.
Expected<int> callIntVoid(JITTargetAddress Addr) {
DEBUG(dbgs() << "Calling int(*)(void) " << format("0x%016x", Addr) << "\n");
LLVM_DEBUG(dbgs() << "Calling int(*)(void) " << format("0x%016x", Addr)
<< "\n");
return callB<exec::CallIntVoid>(Addr);
}
@ -495,16 +498,16 @@ public:
/// return its result.
Expected<int> callMain(JITTargetAddress Addr,
const std::vector<std::string> &Args) {
DEBUG(dbgs() << "Calling int(*)(int, char*[]) " << format("0x%016x", Addr)
<< "\n");
LLVM_DEBUG(dbgs() << "Calling int(*)(int, char*[]) "
<< format("0x%016x", Addr) << "\n");
return callB<exec::CallMain>(Addr, Args);
}
/// Call the void() function at the given address in the target and wait for
/// it to finish.
Error callVoidVoid(JITTargetAddress Addr) {
DEBUG(dbgs() << "Calling void(*)(void) " << format("0x%016x", Addr)
<< "\n");
LLVM_DEBUG(dbgs() << "Calling void(*)(void) " << format("0x%016x", Addr)
<< "\n");
return callB<exec::CallVoidVoid>(Addr);
}

83
llvm/include/llvm/ExecutionEngine/Orc/OrcRemoteTargetServer.h
View File

@ -161,9 +161,9 @@ private:
IntVoidFnTy Fn =
reinterpret_cast<IntVoidFnTy>(static_cast<uintptr_t>(Addr));
DEBUG(dbgs() << " Calling " << format("0x%016x", Addr) << "\n");
LLVM_DEBUG(dbgs() << " Calling " << format("0x%016x", Addr) << "\n");
int Result = Fn();
DEBUG(dbgs() << " Result = " << Result << "\n");
LLVM_DEBUG(dbgs() << " Result = " << Result << "\n");
return Result;
}
@ -180,15 +180,13 @@ private:
for (auto &Arg : Args)
ArgV[Idx++] = Arg.c_str();
ArgV[ArgC] = 0;
DEBUG(
for (int Idx = 0; Idx < ArgC; ++Idx) {
llvm::dbgs() << "Arg " << Idx << ": " << ArgV[Idx] << "\n";
}
);
LLVM_DEBUG(for (int Idx = 0; Idx < ArgC; ++Idx) {
llvm::dbgs() << "Arg " << Idx << ": " << ArgV[Idx] << "\n";
});
DEBUG(dbgs() << " Calling " << format("0x%016x", Addr) << "\n");
LLVM_DEBUG(dbgs() << " Calling " << format("0x%016x", Addr) << "\n");
int Result = Fn(ArgC, ArgV.get());
DEBUG(dbgs() << " Result = " << Result << "\n");
LLVM_DEBUG(dbgs() << " Result = " << Result << "\n");
return Result;
}
@ -199,9 +197,9 @@ private:
VoidVoidFnTy Fn =
reinterpret_cast<VoidVoidFnTy>(static_cast<uintptr_t>(Addr));
DEBUG(dbgs() << " Calling " << format("0x%016x", Addr) << "\n");
LLVM_DEBUG(dbgs() << " Calling " << format("0x%016x", Addr) << "\n");
Fn();
DEBUG(dbgs() << " Complete.\n");
LLVM_DEBUG(dbgs() << " Complete.\n");
return Error::success();
}
@ -211,7 +209,7 @@ private:
if (I != Allocators.end())
return errorCodeToError(
orcError(OrcErrorCode::RemoteAllocatorIdAlreadyInUse));
DEBUG(dbgs() << " Created allocator " << Id << "\n");
LLVM_DEBUG(dbgs() << " Created allocator " << Id << "\n");
Allocators[Id] = Allocator();
return Error::success();
}
@ -221,15 +219,16 @@ private:
if (I != IndirectStubsOwners.end())
return errorCodeToError(
orcError(OrcErrorCode::RemoteIndirectStubsOwnerIdAlreadyInUse));
DEBUG(dbgs() << " Create indirect stubs owner " << Id << "\n");
LLVM_DEBUG(dbgs() << " Create indirect stubs owner " << Id << "\n");
IndirectStubsOwners[Id] = ISBlockOwnerList();
return Error::success();
}
Error handleDeregisterEHFrames(JITTargetAddress TAddr, uint32_t Size) {
uint8_t *Addr = reinterpret_cast<uint8_t *>(static_cast<uintptr_t>(TAddr));
DEBUG(dbgs() << " Registering EH frames at " << format("0x%016x", TAddr)
<< ", Size = " << Size << " bytes\n");
LLVM_DEBUG(dbgs() << " Registering EH frames at "
<< format("0x%016x", TAddr) << ", Size = " << Size
<< " bytes\n");
EHFramesDeregister(Addr, Size);
return Error::success();
}
@ -240,7 +239,7 @@ private:
return errorCodeToError(
orcError(OrcErrorCode::RemoteAllocatorDoesNotExist));
Allocators.erase(I);
DEBUG(dbgs() << " Destroyed allocator " << Id << "\n");
LLVM_DEBUG(dbgs() << " Destroyed allocator " << Id << "\n");
return Error::success();
}
@ -256,8 +255,8 @@ private:
Expected<std::tuple<JITTargetAddress, JITTargetAddress, uint32_t>>
handleEmitIndirectStubs(ResourceIdMgr::ResourceId Id,
uint32_t NumStubsRequired) {
DEBUG(dbgs() << " ISMgr " << Id << " request " << NumStubsRequired
<< " stubs.\n");
LLVM_DEBUG(dbgs() << " ISMgr " << Id << " request " << NumStubsRequired
<< " stubs.\n");
auto StubOwnerItr = IndirectStubsOwners.find(Id);
if (StubOwnerItr == IndirectStubsOwners.end())
@ -328,8 +327,8 @@ private:
Expected<JITTargetAddress> handleGetSymbolAddress(const std::string &Name) {
JITTargetAddress Addr = SymbolLookup(Name);
DEBUG(dbgs() << " Symbol '" << Name << "' = " << format("0x%016x", Addr)
<< "\n");
LLVM_DEBUG(dbgs() << " Symbol '" << Name
<< "' = " << format("0x%016x", Addr) << "\n");
return Addr;
}
@ -340,12 +339,13 @@ private:
uint32_t PageSize = sys::Process::getPageSize();
uint32_t TrampolineSize = TargetT::TrampolineSize;
uint32_t IndirectStubSize = TargetT::IndirectStubsInfo::StubSize;
DEBUG(dbgs() << " Remote info:\n"
<< " triple = '" << ProcessTriple << "'\n"
<< " pointer size = " << PointerSize << "\n"
<< " page size = " << PageSize << "\n"
<< " trampoline size = " << TrampolineSize << "\n"
<< " indirect stub size = " << IndirectStubSize << "\n");
LLVM_DEBUG(dbgs() << " Remote info:\n"
<< " triple = '" << ProcessTriple << "'\n"
<< " pointer size = " << PointerSize << "\n"
<< " page size = " << PageSize << "\n"
<< " trampoline size = " << TrampolineSize << "\n"
<< " indirect stub size = " << IndirectStubSize
<< "\n");
return std::make_tuple(ProcessTriple, PointerSize, PageSize, TrampolineSize,
IndirectStubSize);
}
@ -354,8 +354,8 @@ private:
uint64_t Size) {
uint8_t *Src = reinterpret_cast<uint8_t *>(static_cast<uintptr_t>(RSrc));
DEBUG(dbgs() << " Reading " << Size << " bytes from "
<< format("0x%016x", RSrc) << "\n");
LLVM_DEBUG(dbgs() << " Reading " << Size << " bytes from "
<< format("0x%016x", RSrc) << "\n");
std::vector<uint8_t> Buffer;
Buffer.resize(Size);
@ -367,8 +367,9 @@ private:
Error handleRegisterEHFrames(JITTargetAddress TAddr, uint32_t Size) {
uint8_t *Addr = reinterpret_cast<uint8_t *>(static_cast<uintptr_t>(TAddr));
DEBUG(dbgs() << " Registering EH frames at " << format("0x%016x", TAddr)
<< ", Size = " << Size << " bytes\n");
LLVM_DEBUG(dbgs() << " Registering EH frames at "
<< format("0x%016x", TAddr) << ", Size = " << Size
<< " bytes\n");
EHFramesRegister(Addr, Size);
return Error::success();
}
@ -384,8 +385,9 @@ private:
if (auto Err = Allocator.allocate(LocalAllocAddr, Size, Align))
return std::move(Err);
DEBUG(dbgs() << " Allocator " << Id << " reserved " << LocalAllocAddr
<< " (" << Size << " bytes, alignment " << Align << ")\n");
LLVM_DEBUG(dbgs() << " Allocator " << Id << " reserved " << LocalAllocAddr
<< " (" << Size << " bytes, alignment " << Align
<< ")\n");
JITTargetAddress AllocAddr = static_cast<JITTargetAddress>(
reinterpret_cast<uintptr_t>(LocalAllocAddr));
@ -401,10 +403,11 @@ private:
orcError(OrcErrorCode::RemoteAllocatorDoesNotExist));
auto &Allocator = I->second;
void *LocalAddr = reinterpret_cast<void *>(static_cast<uintptr_t>(Addr));
DEBUG(dbgs() << " Allocator " << Id << " set permissions on " << LocalAddr
<< " to " << (Flags & sys::Memory::MF_READ ? 'R' : '-')
<< (Flags & sys::Memory::MF_WRITE ? 'W' : '-')
<< (Flags & sys::Memory::MF_EXEC ? 'X' : '-') << "\n");
LLVM_DEBUG(dbgs() << " Allocator " << Id << " set permissions on "
<< LocalAddr << " to "
<< (Flags & sys::Memory::MF_READ ? 'R' : '-')
<< (Flags & sys::Memory::MF_WRITE ? 'W' : '-')
<< (Flags & sys::Memory::MF_EXEC ? 'X' : '-') << "\n");
return Allocator.setProtections(LocalAddr, Flags);
}
@ -414,14 +417,14 @@ private:
}
Error handleWriteMem(DirectBufferWriter DBW) {
DEBUG(dbgs() << " Writing " << DBW.getSize() << " bytes to "
<< format("0x%016x", DBW.getDst()) << "\n");
LLVM_DEBUG(dbgs() << " Writing " << DBW.getSize() << " bytes to "
<< format("0x%016x", DBW.getDst()) << "\n");
return Error::success();
}
Error handleWritePtr(JITTargetAddress Addr, JITTargetAddress PtrVal) {
DEBUG(dbgs() << " Writing pointer *" << format("0x%016x", Addr) << " = "
<< format("0x%016x", PtrVal) << "\n");
LLVM_DEBUG(dbgs() << " Writing pointer *" << format("0x%016x", Addr)
<< " = " << format("0x%016x", PtrVal) << "\n");
uintptr_t *Ptr =
reinterpret_cast<uintptr_t *>(static_cast<uintptr_t>(Addr));
*Ptr = static_cast<uintptr_t>(PtrVal);

25
llvm/include/llvm/Support/Debug.h
View File

@ -11,17 +11,18 @@
// code, without it being enabled all of the time, and without having to add
// command line options to enable it.
//
// In particular, just wrap your code with the DEBUG() macro, and it will be
// enabled automatically if you specify '-debug' on the command-line.
// DEBUG() requires the DEBUG_TYPE macro to be defined. Set it to "foo" specify
// that your debug code belongs to class "foo". Be careful that you only do
// this after including Debug.h and not around any #include of headers. Headers
// should define and undef the macro acround the code that needs to use the
// DEBUG() macro. Then, on the command line, you can specify '-debug-only=foo'
// to enable JUST the debug information for the foo class.
// In particular, just wrap your code with the LLVM_DEBUG() macro, and it will
// be enabled automatically if you specify '-debug' on the command-line.
// LLVM_DEBUG() requires the DEBUG_TYPE macro to be defined. Set it to "foo"
// specify that your debug code belongs to class "foo". Be careful that you only
// do this after including Debug.h and not around any #include of headers.
// Headers should define and undef the macro acround the code that needs to use
// the LLVM_DEBUG() macro. Then, on the command line, you can specify
// '-debug-only=foo' to enable JUST the debug information for the foo class.
//
// When compiling without assertions, the -debug-* options and all code in
// DEBUG() statements disappears, so it does not affect the runtime of the code.
// LLVM_DEBUG() statements disappears, so it does not affect the runtime of the
// code.
//
//===----------------------------------------------------------------------===//
@ -113,9 +114,11 @@ raw_ostream &dbgs();
// debug build, then the code specified as the option to the macro will be
// executed. Otherwise it will not be. Example:
//
// DEBUG(dbgs() << "Bitset contains: " << Bitset << "\n");
// LLVM_DEBUG(dbgs() << "Bitset contains: " << Bitset << "\n");
//
#define DEBUG(X) DEBUG_WITH_TYPE(DEBUG_TYPE, X)
#define LLVM_DEBUG(X) DEBUG_WITH_TYPE(DEBUG_TYPE, X)
#define DEBUG(X) LLVM_DEBUG(X)
} // end namespace llvm

251
llvm/include/llvm/Support/GenericDomTreeConstruction.h
View File

@ -146,15 +146,15 @@ struct SemiNCAInfo {
assert(llvm::find(Res, Child) != Res.end()
&& "Expected child not found in the CFG");
Res.erase(std::remove(Res.begin(), Res.end(), Child), Res.end());
DEBUG(dbgs() << "\tHiding edge " << BlockNamePrinter(N) << " -> "
<< BlockNamePrinter(Child) << "\n");
LLVM_DEBUG(dbgs() << "\tHiding edge " << BlockNamePrinter(N) << " -> "
<< BlockNamePrinter(Child) << "\n");
} else {
// If there's an deletion in the future, it means that the edge cannot
// exist in the current CFG, but existed in it before.
assert(llvm::find(Res, Child) == Res.end() &&
"Unexpected child found in the CFG");
DEBUG(dbgs() << "\tShowing virtual edge " << BlockNamePrinter(N)
<< " -> " << BlockNamePrinter(Child) << "\n");
LLVM_DEBUG(dbgs() << "\tShowing virtual edge " << BlockNamePrinter(N)
<< " -> " << BlockNamePrinter(Child) << "\n");
Res.push_back(Child);
}
}
@ -387,7 +387,7 @@ struct SemiNCAInfo {
SNCA.addVirtualRoot();
unsigned Num = 1;
DEBUG(dbgs() << "\t\tLooking for trivial roots\n");
LLVM_DEBUG(dbgs() << "\t\tLooking for trivial roots\n");
// Step #1: Find all the trivial roots that are going to will definitely
// remain tree roots.
@ -404,14 +404,14 @@ struct SemiNCAInfo {
Roots.push_back(N);
// Run DFS not to walk this part of CFG later.
Num = SNCA.runDFS(N, Num, AlwaysDescend, 1);
DEBUG(dbgs() << "Found a new trivial root: " << BlockNamePrinter(N)
<< "\n");
DEBUG(dbgs() << "Last visited node: "
<< BlockNamePrinter(SNCA.NumToNode[Num]) << "\n");
LLVM_DEBUG(dbgs() << "Found a new trivial root: " << BlockNamePrinter(N)
<< "\n");
LLVM_DEBUG(dbgs() << "Last visited node: "
<< BlockNamePrinter(SNCA.NumToNode[Num]) << "\n");
}
}
DEBUG(dbgs() << "\t\tLooking for non-trivial roots\n");
LLVM_DEBUG(dbgs() << "\t\tLooking for non-trivial roots\n");
// Step #2: Find all non-trivial root candidates. Those are CFG nodes that
// are reverse-unreachable were not visited by previous DFS walks (i.e. CFG
@ -431,8 +431,8 @@ struct SemiNCAInfo {
SmallPtrSet<NodePtr, 4> ConnectToExitBlock;
for (const NodePtr I : nodes(DT.Parent)) {
if (SNCA.NodeToInfo.count(I) == 0) {
DEBUG(dbgs() << "\t\t\tVisiting node " << BlockNamePrinter(I)
<< "\n");
LLVM_DEBUG(dbgs()
<< "\t\t\tVisiting node " << BlockNamePrinter(I) << "\n");
// Find the furthest away we can get by following successors, then
// follow them in reverse. This gives us some reasonable answer about
// the post-dom tree inside any infinite loop. In particular, it
@ -443,47 +443,49 @@ struct SemiNCAInfo {
// the lowest and highest points in the infinite loop. In theory, it
// would be nice to give the canonical backedge for the loop, but it's
// expensive and does not always lead to a minimal set of roots.
DEBUG(dbgs() << "\t\t\tRunning forward DFS\n");
LLVM_DEBUG(dbgs() << "\t\t\tRunning forward DFS\n");
const unsigned NewNum = SNCA.runDFS<true>(I, Num, AlwaysDescend, Num);
const NodePtr FurthestAway = SNCA.NumToNode[NewNum];
DEBUG(dbgs() << "\t\t\tFound a new furthest away node "
<< "(non-trivial root): "
<< BlockNamePrinter(FurthestAway) << "\n");
LLVM_DEBUG(dbgs() << "\t\t\tFound a new furthest away node "
<< "(non-trivial root): "
<< BlockNamePrinter(FurthestAway) << "\n");
ConnectToExitBlock.insert(FurthestAway);
Roots.push_back(FurthestAway);
DEBUG(dbgs() << "\t\t\tPrev DFSNum: " << Num << ", new DFSNum: "
<< NewNum << "\n\t\t\tRemoving DFS info\n");
LLVM_DEBUG(dbgs() << "\t\t\tPrev DFSNum: " << Num << ", new DFSNum: "
<< NewNum << "\n\t\t\tRemoving DFS info\n");
for (unsigned i = NewNum; i > Num; --i) {
const NodePtr N = SNCA.NumToNode[i];
DEBUG(dbgs() << "\t\t\t\tRemoving DFS info for "
<< BlockNamePrinter(N) << "\n");
LLVM_DEBUG(dbgs() << "\t\t\t\tRemoving DFS info for "
<< BlockNamePrinter(N) << "\n");
SNCA.NodeToInfo.erase(N);
SNCA.NumToNode.pop_back();
}
const unsigned PrevNum = Num;
DEBUG(dbgs() << "\t\t\tRunning reverse DFS\n");
LLVM_DEBUG(dbgs() << "\t\t\tRunning reverse DFS\n");
Num = SNCA.runDFS(FurthestAway, Num, AlwaysDescend, 1);
for (unsigned i = PrevNum + 1; i <= Num; ++i)
DEBUG(dbgs() << "\t\t\t\tfound node "
<< BlockNamePrinter(SNCA.NumToNode[i]) << "\n");
LLVM_DEBUG(dbgs() << "\t\t\t\tfound node "
<< BlockNamePrinter(SNCA.NumToNode[i]) << "\n");
}
}
}
DEBUG(dbgs() << "Total: " << Total << ", Num: " << Num << "\n");
DEBUG(dbgs() << "Discovered CFG nodes:\n");
DEBUG(for (size_t i = 0; i <= Num; ++i) dbgs()
<< i << ": " << BlockNamePrinter(SNCA.NumToNode[i]) << "\n");
LLVM_DEBUG(dbgs() << "Total: " << Total << ", Num: " << Num << "\n");
LLVM_DEBUG(dbgs() << "Discovered CFG nodes:\n");
LLVM_DEBUG(for (size_t i = 0; i <= Num; ++i) dbgs()
<< i << ": " << BlockNamePrinter(SNCA.NumToNode[i]) << "\n");
assert((Total + 1 == Num) && "Everything should have been visited");
// Step #3: If we found some non-trivial roots, make them non-redundant.
if (HasNonTrivialRoots) RemoveRedundantRoots(DT, BUI, Roots);
DEBUG(dbgs() << "Found roots: ");
DEBUG(for (auto *Root : Roots) dbgs() << BlockNamePrinter(Root) << " ");
DEBUG(dbgs() << "\n");
LLVM_DEBUG(dbgs() << "Found roots: ");
LLVM_DEBUG(for (auto *Root
: Roots) dbgs()
<< BlockNamePrinter(Root) << " ");
LLVM_DEBUG(dbgs() << "\n");
return Roots;
}
@ -499,7 +501,7 @@ struct SemiNCAInfo {
static void RemoveRedundantRoots(const DomTreeT &DT, BatchUpdatePtr BUI,
RootsT &Roots) {
assert(IsPostDom && "This function is for postdominators only");
DEBUG(dbgs() << "Removing redundant roots\n");
LLVM_DEBUG(dbgs() << "Removing redundant roots\n");
SemiNCAInfo SNCA(BUI);
@ -507,8 +509,8 @@ struct SemiNCAInfo {
auto &Root = Roots[i];
// Trivial roots are always non-redundant.
if (!HasForwardSuccessors(Root, BUI)) continue;
DEBUG(dbgs() << "\tChecking if " << BlockNamePrinter(Root)
<< " remains a root\n");
LLVM_DEBUG(dbgs() << "\tChecking if " << BlockNamePrinter(Root)
<< " remains a root\n");
SNCA.clear();
// Do a forward walk looking for the other roots.
const unsigned Num = SNCA.runDFS<true>(Root, 0, AlwaysDescend, 0);
@ -520,9 +522,9 @@ struct SemiNCAInfo {
// root from the set of roots, as it is reverse-reachable from the other
// one.
if (llvm::find(Roots, N) != Roots.end()) {
DEBUG(dbgs() << "\tForward DFS walk found another root "
<< BlockNamePrinter(N) << "\n\tRemoving root "
<< BlockNamePrinter(Root) << "\n");
LLVM_DEBUG(dbgs() << "\tForward DFS walk found another root "
<< BlockNamePrinter(N) << "\n\tRemoving root "
<< BlockNamePrinter(Root) << "\n");
std::swap(Root, Roots.back());
Roots.pop_back();
@ -563,7 +565,8 @@ struct SemiNCAInfo {
SNCA.runSemiNCA(DT);
if (BUI) {
BUI->IsRecalculated = true;
DEBUG(dbgs() << "DomTree recalculated, skipping future batch updates\n");
LLVM_DEBUG(
dbgs() << "DomTree recalculated, skipping future batch updates\n");
}
if (DT.Roots.empty()) return;
@ -585,8 +588,8 @@ struct SemiNCAInfo {
// Loop over all of the discovered blocks in the function...
for (size_t i = 1, e = NumToNode.size(); i != e; ++i) {
NodePtr W = NumToNode[i];
DEBUG(dbgs() << "\tdiscovered a new reachable node "
<< BlockNamePrinter(W) << "\n");
LLVM_DEBUG(dbgs() << "\tdiscovered a new reachable node "
<< BlockNamePrinter(W) << "\n");
// Don't replace this with 'count', the insertion side effect is important
if (DT.DomTreeNodes[W]) continue; // Haven't calculated this node yet?
@ -638,8 +641,8 @@ struct SemiNCAInfo {
assert((From || IsPostDom) &&
"From has to be a valid CFG node or a virtual root");
assert(To && "Cannot be a nullptr");
DEBUG(dbgs() << "Inserting edge " << BlockNamePrinter(From) << " -> "
<< BlockNamePrinter(To) << "\n");
LLVM_DEBUG(dbgs() << "Inserting edge " << BlockNamePrinter(From) << " -> "
<< BlockNamePrinter(To) << "\n");
TreeNodePtr FromTN = DT.getNode(From);
if (!FromTN) {
@ -678,8 +681,8 @@ struct SemiNCAInfo {
if (RIt == DT.Roots.end())
return false; // To is not a root, nothing to update.
DEBUG(dbgs() << "\t\tAfter the insertion, " << BlockNamePrinter(To)
<< " is no longer a root\n\t\tRebuilding the tree!!!\n");
LLVM_DEBUG(dbgs() << "\t\tAfter the insertion, " << BlockNamePrinter(To)
<< " is no longer a root\n\t\tRebuilding the tree!!!\n");
CalculateFromScratch(DT, BUI);
return true;
@ -706,8 +709,8 @@ struct SemiNCAInfo {
// can make a different (implicit) decision about which node within an
// infinite loop becomes a root.
DEBUG(dbgs() << "Roots are different in updated trees\n"
<< "The entire tree needs to be rebuilt\n");
LLVM_DEBUG(dbgs() << "Roots are different in updated trees\n"
<< "The entire tree needs to be rebuilt\n");
// It may be possible to update the tree without recalculating it, but
// we do not know yet how to do it, and it happens rarely in practise.
CalculateFromScratch(DT, BUI);
@ -718,8 +721,8 @@ struct SemiNCAInfo {
// Handles insertion to a node already in the dominator tree.
static void InsertReachable(DomTreeT &DT, const BatchUpdatePtr BUI,
const TreeNodePtr From, const TreeNodePtr To) {
DEBUG(dbgs() << "\tReachable " << BlockNamePrinter(From->getBlock())
<< " -> " << BlockNamePrinter(To->getBlock()) << "\n");
LLVM_DEBUG(dbgs() << "\tReachable " << BlockNamePrinter(From->getBlock())
<< " -> " << BlockNamePrinter(To->getBlock()) << "\n");
if (IsPostDom && UpdateRootsBeforeInsertion(DT, BUI, From, To)) return;
// DT.findNCD expects both pointers to be valid. When From is a virtual
// root, then its CFG block pointer is a nullptr, so we have to 'compute'
@ -732,7 +735,7 @@ struct SemiNCAInfo {
const TreeNodePtr NCD = DT.getNode(NCDBlock);
assert(NCD);
DEBUG(dbgs() << "\t\tNCA == " << BlockNamePrinter(NCD) << "\n");
LLVM_DEBUG(dbgs() << "\t\tNCA == " << BlockNamePrinter(NCD) << "\n");
const TreeNodePtr ToIDom = To->getIDom();
// Nothing affected -- NCA property holds.
@ -741,18 +744,20 @@ struct SemiNCAInfo {
// Identify and collect affected nodes.
InsertionInfo II;
DEBUG(dbgs() << "Marking " << BlockNamePrinter(To) << " as affected\n");
LLVM_DEBUG(dbgs() << "Marking " << BlockNamePrinter(To)
<< " as affected\n");
II.Affected.insert(To);
const unsigned ToLevel = To->getLevel();
DEBUG(dbgs() << "Putting " << BlockNamePrinter(To) << " into a Bucket\n");
LLVM_DEBUG(dbgs() << "Putting " << BlockNamePrinter(To)
<< " into a Bucket\n");
II.Bucket.push({ToLevel, To});
while (!II.Bucket.empty()) {
const TreeNodePtr CurrentNode = II.Bucket.top().second;
const unsigned CurrentLevel = CurrentNode->getLevel();
II.Bucket.pop();
DEBUG(dbgs() << "\tAdding to Visited and AffectedQueue: "
<< BlockNamePrinter(CurrentNode) << "\n");
LLVM_DEBUG(dbgs() << "\tAdding to Visited and AffectedQueue: "
<< BlockNamePrinter(CurrentNode) << "\n");
II.Visited.insert({CurrentNode, CurrentLevel});
II.AffectedQueue.push_back(CurrentNode);
@ -770,8 +775,8 @@ struct SemiNCAInfo {
const TreeNodePtr TN, const unsigned RootLevel,
const TreeNodePtr NCD, InsertionInfo &II) {
const unsigned NCDLevel = NCD->getLevel();
DEBUG(dbgs() << "Visiting " << BlockNamePrinter(TN) << ", RootLevel "
<< RootLevel << "\n");
LLVM_DEBUG(dbgs() << "Visiting " << BlockNamePrinter(TN) << ", RootLevel "
<< RootLevel << "\n");
SmallVector<TreeNodePtr, 8> Stack = {TN};
assert(TN->getBlock() && II.Visited.count(TN) && "Preconditions!");
@ -780,7 +785,7 @@ struct SemiNCAInfo {
do {
TreeNodePtr Next = Stack.pop_back_val();
DEBUG(dbgs() << " Next: " << BlockNamePrinter(Next) << "\n");
LLVM_DEBUG(dbgs() << " Next: " << BlockNamePrinter(Next) << "\n");
for (const NodePtr Succ :
ChildrenGetter<IsPostDom>::Get(Next->getBlock(), BUI)) {
@ -788,8 +793,8 @@ struct SemiNCAInfo {
assert(SuccTN && "Unreachable successor found at reachable insertion");
const unsigned SuccLevel = SuccTN->getLevel();
DEBUG(dbgs() << "\tSuccessor " << BlockNamePrinter(Succ) << ", level = "
<< SuccLevel << "\n");
LLVM_DEBUG(dbgs() << "\tSuccessor " << BlockNamePrinter(Succ)
<< ", level = " << SuccLevel << "\n");
// Do not process the same node multiple times.
if (Processed.count(Next) > 0)
@ -798,11 +803,11 @@ struct SemiNCAInfo {
// Succ dominated by subtree From -- not affected.
// (Based on the lemma 2.5 from the second paper.)
if (SuccLevel > RootLevel) {
DEBUG(dbgs() << "\t\tDominated by subtree From\n");
LLVM_DEBUG(dbgs() << "\t\tDominated by subtree From\n");
if (II.Visited.count(SuccTN) != 0) {
DEBUG(dbgs() << "\t\t\talready visited at level "
<< II.Visited[SuccTN] << "\n\t\t\tcurrent level "
<< RootLevel << ")\n");
LLVM_DEBUG(dbgs() << "\t\t\talready visited at level "
<< II.Visited[SuccTN] << "\n\t\t\tcurrent level "
<< RootLevel << ")\n");
// A node can be necessary to visit again if we see it again at
// a lower level than before.
@ -810,15 +815,15 @@ struct SemiNCAInfo {
continue;
}
DEBUG(dbgs() << "\t\tMarking visited not affected "
<< BlockNamePrinter(Succ) << "\n");
LLVM_DEBUG(dbgs() << "\t\tMarking visited not affected "
<< BlockNamePrinter(Succ) << "\n");
II.Visited.insert({SuccTN, RootLevel});
II.VisitedNotAffectedQueue.push_back(SuccTN);
Stack.push_back(SuccTN);
} else if ((SuccLevel > NCDLevel + 1) &&
II.Affected.count(SuccTN) == 0) {
DEBUG(dbgs() << "\t\tMarking affected and adding "
<< BlockNamePrinter(Succ) << " to a Bucket\n");
LLVM_DEBUG(dbgs() << "\t\tMarking affected and adding "
<< BlockNamePrinter(Succ) << " to a Bucket\n");
II.Affected.insert(SuccTN);
II.Bucket.push({SuccLevel, SuccTN});
}
@ -831,11 +836,11 @@ struct SemiNCAInfo {
// Updates immediate dominators and levels after insertion.
static void UpdateInsertion(DomTreeT &DT, const BatchUpdatePtr BUI,
const TreeNodePtr NCD, InsertionInfo &II) {
DEBUG(dbgs() << "Updating NCD = " << BlockNamePrinter(NCD) << "\n");
LLVM_DEBUG(dbgs() << "Updating NCD = " << BlockNamePrinter(NCD) << "\n");
for (const TreeNodePtr TN : II.AffectedQueue) {
DEBUG(dbgs() << "\tIDom(" << BlockNamePrinter(TN)
<< ") = " << BlockNamePrinter(NCD) << "\n");
LLVM_DEBUG(dbgs() << "\tIDom(" << BlockNamePrinter(TN)
<< ") = " << BlockNamePrinter(NCD) << "\n");
TN->setIDom(NCD);
}
@ -844,12 +849,13 @@ struct SemiNCAInfo {
}
static void UpdateLevelsAfterInsertion(InsertionInfo &II) {
DEBUG(dbgs() << "Updating levels for visited but not affected nodes\n");
LLVM_DEBUG(
dbgs() << "Updating levels for visited but not affected nodes\n");
for (const TreeNodePtr TN : II.VisitedNotAffectedQueue) {
DEBUG(dbgs() << "\tlevel(" << BlockNamePrinter(TN) << ") = ("
<< BlockNamePrinter(TN->getIDom()) << ") "
<< TN->getIDom()->getLevel() << " + 1\n");
LLVM_DEBUG(dbgs() << "\tlevel(" << BlockNamePrinter(TN) << ") = ("
<< BlockNamePrinter(TN->getIDom()) << ") "
<< TN->getIDom()->getLevel() << " + 1\n");
TN->UpdateLevel();
}
}
@ -857,23 +863,24 @@ struct SemiNCAInfo {
// Handles insertion to previously unreachable nodes.
static void InsertUnreachable(DomTreeT &DT, const BatchUpdatePtr BUI,
const TreeNodePtr From, const NodePtr To) {
DEBUG(dbgs() << "Inserting " << BlockNamePrinter(From)
<< " -> (unreachable) " << BlockNamePrinter(To) << "\n");
LLVM_DEBUG(dbgs() << "Inserting " << BlockNamePrinter(From)
<< " -> (unreachable) " << BlockNamePrinter(To) << "\n");
// Collect discovered edges to already reachable nodes.
SmallVector<std::pair<NodePtr, TreeNodePtr>, 8> DiscoveredEdgesToReachable;
// Discover and connect nodes that became reachable with the insertion.
ComputeUnreachableDominators(DT, BUI, To, From, DiscoveredEdgesToReachable);
DEBUG(dbgs() << "Inserted " << BlockNamePrinter(From)
<< " -> (prev unreachable) " << BlockNamePrinter(To) << "\n");
LLVM_DEBUG(dbgs() << "Inserted " << BlockNamePrinter(From)
<< " -> (prev unreachable) " << BlockNamePrinter(To)
<< "\n");
// Used the discovered edges and inset discovered connecting (incoming)
// edges.
for (const auto &Edge : DiscoveredEdgesToReachable) {
DEBUG(dbgs() << "\tInserting discovered connecting edge "
<< BlockNamePrinter(Edge.first) << " -> "
<< BlockNamePrinter(Edge.second) << "\n");
LLVM_DEBUG(dbgs() << "\tInserting discovered connecting edge "
<< BlockNamePrinter(Edge.first) << " -> "
<< BlockNamePrinter(Edge.second) << "\n");
InsertReachable(DT, BUI, DT.getNode(Edge.first), Edge.second);
}
}
@ -901,14 +908,14 @@ struct SemiNCAInfo {
SNCA.runSemiNCA(DT);
SNCA.attachNewSubtree(DT, Incoming);
DEBUG(dbgs() << "After adding unreachable nodes\n");
LLVM_DEBUG(dbgs() << "After adding unreachable nodes\n");
}
static void DeleteEdge(DomTreeT &DT, const BatchUpdatePtr BUI,
const NodePtr From, const NodePtr To) {
assert(From && To && "Cannot disconnect nullptrs");
DEBUG(dbgs() << "Deleting edge " << BlockNamePrinter(From) << " -> "
<< BlockNamePrinter(To) << "\n");
LLVM_DEBUG(dbgs() << "Deleting edge " << BlockNamePrinter(From) << " -> "
<< BlockNamePrinter(To) << "\n");
#ifndef NDEBUG
// Ensure that the edge was in fact deleted from the CFG before informing
@ -928,8 +935,9 @@ struct SemiNCAInfo {
const TreeNodePtr ToTN = DT.getNode(To);
if (!ToTN) {
DEBUG(dbgs() << "\tTo (" << BlockNamePrinter(To)
<< ") already unreachable -- there is no edge to delete\n");
LLVM_DEBUG(
dbgs() << "\tTo (" << BlockNamePrinter(To)
<< ") already unreachable -- there is no edge to delete\n");
return;
}
@ -941,8 +949,8 @@ struct SemiNCAInfo {
DT.DFSInfoValid = false;
const TreeNodePtr ToIDom = ToTN->getIDom();
DEBUG(dbgs() << "\tNCD " << BlockNamePrinter(NCD) << ", ToIDom "
<< BlockNamePrinter(ToIDom) << "\n");
LLVM_DEBUG(dbgs() << "\tNCD " << BlockNamePrinter(NCD) << ", ToIDom "
<< BlockNamePrinter(ToIDom) << "\n");
// To remains reachable after deletion.
// (Based on the caption under Figure 4. from the second paper.)
@ -959,9 +967,9 @@ struct SemiNCAInfo {
static void DeleteReachable(DomTreeT &DT, const BatchUpdatePtr BUI,
const TreeNodePtr FromTN,
const TreeNodePtr ToTN) {
DEBUG(dbgs() << "Deleting reachable " << BlockNamePrinter(FromTN) << " -> "
<< BlockNamePrinter(ToTN) << "\n");
DEBUG(dbgs() << "\tRebuilding subtree\n");
LLVM_DEBUG(dbgs() << "Deleting reachable " << BlockNamePrinter(FromTN)
<< " -> " << BlockNamePrinter(ToTN) << "\n");
LLVM_DEBUG(dbgs() << "\tRebuilding subtree\n");
// Find the top of the subtree that needs to be rebuilt.
// (Based on the lemma 2.6 from the second paper.)
@ -974,7 +982,7 @@ struct SemiNCAInfo {
// Top of the subtree to rebuild is the root node. Rebuild the tree from
// scratch.
if (!PrevIDomSubTree) {
DEBUG(dbgs() << "The entire tree needs to be rebuilt\n");
LLVM_DEBUG(dbgs() << "The entire tree needs to be rebuilt\n");
CalculateFromScratch(DT, BUI);
return;
}
@ -985,11 +993,12 @@ struct SemiNCAInfo {
return DT.getNode(To)->getLevel() > Level;
};
DEBUG(dbgs() << "\tTop of subtree: " << BlockNamePrinter(ToIDomTN) << "\n");
LLVM_DEBUG(dbgs() << "\tTop of subtree: " << BlockNamePrinter(ToIDomTN)
<< "\n");
SemiNCAInfo SNCA(BUI);
SNCA.runDFS(ToIDom, 0, DescendBelow, 0);
DEBUG(dbgs() << "\tRunning Semi-NCA\n");
LLVM_DEBUG(dbgs() << "\tRunning Semi-NCA\n");
SNCA.runSemiNCA(DT, Level);
SNCA.reattachExistingSubtree(DT, PrevIDomSubTree);
}
@ -998,19 +1007,20 @@ struct SemiNCAInfo {
// explained on the page 7 of the second paper.
static bool HasProperSupport(DomTreeT &DT, const BatchUpdatePtr BUI,
const TreeNodePtr TN) {
DEBUG(dbgs() << "IsReachableFromIDom " << BlockNamePrinter(TN) << "\n");
LLVM_DEBUG(dbgs() << "IsReachableFromIDom " << BlockNamePrinter(TN)
<< "\n");
for (const NodePtr Pred :
ChildrenGetter<!IsPostDom>::Get(TN->getBlock(), BUI)) {
DEBUG(dbgs() << "\tPred " << BlockNamePrinter(Pred) << "\n");
LLVM_DEBUG(dbgs() << "\tPred " << BlockNamePrinter(Pred) << "\n");
if (!DT.getNode(Pred)) continue;
const NodePtr Support =
DT.findNearestCommonDominator(TN->getBlock(), Pred);
DEBUG(dbgs() << "\tSupport " << BlockNamePrinter(Support) << "\n");
LLVM_DEBUG(dbgs() << "\tSupport " << BlockNamePrinter(Support) << "\n");
if (Support != TN->getBlock()) {
DEBUG(dbgs() << "\t" << BlockNamePrinter(TN)
<< " is reachable from support "
<< BlockNamePrinter(Support) << "\n");
LLVM_DEBUG(dbgs() << "\t" << BlockNamePrinter(TN)
<< " is reachable from support "
<< BlockNamePrinter(Support) << "\n");
return true;
}
}
@ -1022,8 +1032,8 @@ struct SemiNCAInfo {
// (Based on the lemma 2.7 from the second paper.)
static void DeleteUnreachable(DomTreeT &DT, const BatchUpdatePtr BUI,
const TreeNodePtr ToTN) {
DEBUG(dbgs() << "Deleting unreachable subtree " << BlockNamePrinter(ToTN)
<< "\n");
LLVM_DEBUG(dbgs() << "Deleting unreachable subtree "
<< BlockNamePrinter(ToTN) << "\n");
assert(ToTN);
assert(ToTN->getBlock());
@ -1031,8 +1041,9 @@ struct SemiNCAInfo {
// Deletion makes a region reverse-unreachable and creates a new root.
// Simulate that by inserting an edge from the virtual root to ToTN and
// adding it as a new root.
DEBUG(dbgs() << "\tDeletion made a region reverse-unreachable\n");
DEBUG(dbgs() << "\tAdding new root " << BlockNamePrinter(ToTN) << "\n");
LLVM_DEBUG(dbgs() << "\tDeletion made a region reverse-unreachable\n");
LLVM_DEBUG(dbgs() << "\tAdding new root " << BlockNamePrinter(ToTN)
<< "\n");
DT.Roots.push_back(ToTN->getBlock());
InsertReachable(DT, BUI, DT.getNode(nullptr), ToTN);
return;
@ -1069,15 +1080,15 @@ struct SemiNCAInfo {
const TreeNodePtr NCD = DT.getNode(NCDBlock);
assert(NCD);
DEBUG(dbgs() << "Processing affected node " << BlockNamePrinter(TN)
<< " with NCD = " << BlockNamePrinter(NCD)
<< ", MinNode =" << BlockNamePrinter(MinNode) << "\n");
LLVM_DEBUG(dbgs() << "Processing affected node " << BlockNamePrinter(TN)
<< " with NCD = " << BlockNamePrinter(NCD)
<< ", MinNode =" << BlockNamePrinter(MinNode) << "\n");
if (NCD != TN && NCD->getLevel() < MinNode->getLevel()) MinNode = NCD;
}
// Root reached, rebuild the whole tree from scratch.
if (!MinNode->getIDom()) {
DEBUG(dbgs() << "The entire tree needs to be rebuilt\n");
LLVM_DEBUG(dbgs() << "The entire tree needs to be rebuilt\n");
CalculateFromScratch(DT, BUI);
return;
}
@ -1087,7 +1098,7 @@ struct SemiNCAInfo {
for (unsigned i = LastDFSNum; i > 0; --i) {
const NodePtr N = SNCA.NumToNode[i];
const TreeNodePtr TN = DT.getNode(N);
DEBUG(dbgs() << "Erasing node " << BlockNamePrinter(TN) << "\n");
LLVM_DEBUG(dbgs() << "Erasing node " << BlockNamePrinter(TN) << "\n");
EraseNode(DT, TN);
}
@ -1095,8 +1106,8 @@ struct SemiNCAInfo {
// The affected subtree start at the To node -- there's no extra work to do.
if (MinNode == ToTN) return;
DEBUG(dbgs() << "DeleteUnreachable: running DFS with MinNode = "
<< BlockNamePrinter(MinNode) << "\n");
LLVM_DEBUG(dbgs() << "DeleteUnreachable: running DFS with MinNode = "
<< BlockNamePrinter(MinNode) << "\n");
const unsigned MinLevel = MinNode->getLevel();
const TreeNodePtr PrevIDom = MinNode->getIDom();
assert(PrevIDom);
@ -1109,8 +1120,8 @@ struct SemiNCAInfo {
};
SNCA.runDFS(MinNode->getBlock(), 0, DescendBelow, 0);
DEBUG(dbgs() << "Previous IDom(MinNode) = " << BlockNamePrinter(PrevIDom)
<< "\nRunning Semi-NCA\n");
LLVM_DEBUG(dbgs() << "Previous IDom(MinNode) = "
<< BlockNamePrinter(PrevIDom) << "\nRunning Semi-NCA\n");
// Rebuild the remaining part of affected subtree.
SNCA.runSemiNCA(DT, MinLevel);
@ -1169,11 +1180,11 @@ struct SemiNCAInfo {
BUI.FuturePredecessors[U.getTo()].insert({U.getFrom(), U.getKind()});
}
DEBUG(dbgs() << "About to apply " << NumLegalized << " updates\n");
DEBUG(if (NumLegalized < 32) for (const auto &U
: reverse(BUI.Updates)) dbgs()
<< '\t' << U << "\n");
DEBUG(dbgs() << "\n");
LLVM_DEBUG(dbgs() << "About to apply " << NumLegalized << " updates\n");
LLVM_DEBUG(if (NumLegalized < 32) for (const auto &U
: reverse(BUI.Updates)) dbgs()
<< '\t' << U << "\n");
LLVM_DEBUG(dbgs() << "\n");
// If the DominatorTree was recalculated at some point, stop the batch
// updates. Full recalculations ignore batch updates and look at the actual
@ -1201,7 +1212,7 @@ struct SemiNCAInfo {
// minimizes the amount of work needed done during incremental updates.
static void LegalizeUpdates(ArrayRef<UpdateT> AllUpdates,
SmallVectorImpl<UpdateT> &Result) {
DEBUG(dbgs() << "Legalizing " << AllUpdates.size() << " updates\n");
LLVM_DEBUG(dbgs() << "Legalizing " << AllUpdates.size() << " updates\n");
// Count the total number of inserions of each edge.
// Each insertion adds 1 and deletion subtracts 1. The end number should be
// one of {-1 (deletion), 0 (NOP), +1 (insertion)}. Otherwise, the sequence
@ -1251,7 +1262,7 @@ struct SemiNCAInfo {
static void ApplyNextUpdate(DomTreeT &DT, BatchUpdateInfo &BUI) {
assert(!BUI.Updates.empty() && "No updates to apply!");
UpdateT CurrentUpdate = BUI.Updates.pop_back_val();
DEBUG(dbgs() << "Applying update: " << CurrentUpdate << "\n");
LLVM_DEBUG(dbgs() << "Applying update: " << CurrentUpdate << "\n");
// Move to the next snapshot of the CFG by removing the reverse-applied
// current update.
@ -1530,8 +1541,8 @@ struct SemiNCAInfo {
const NodePtr BB = TN->getBlock();
if (!BB || TN->getChildren().empty()) continue;
DEBUG(dbgs() << "Verifying parent property of node "
<< BlockNamePrinter(TN) << "\n");
LLVM_DEBUG(dbgs() << "Verifying parent property of node "
<< BlockNamePrinter(TN) << "\n");
clear();
doFullDFSWalk(DT, [BB](NodePtr From, NodePtr To) {
return From != BB && To != BB;

16
llvm/include/llvm/Support/UnicodeCharRanges.h
View File

@ -77,17 +77,17 @@ private:
for (CharRanges::const_iterator I = Ranges.begin(), E = Ranges.end();
I != E; ++I) {
if (I != Ranges.begin() && Prev >= I->Lower) {
DEBUG(dbgs() << "Upper bound 0x");
DEBUG(dbgs().write_hex(Prev));
DEBUG(dbgs() << " should be less than succeeding lower bound 0x");
DEBUG(dbgs().write_hex(I->Lower) << "\n");
LLVM_DEBUG(dbgs() << "Upper bound 0x");
LLVM_DEBUG(dbgs().write_hex(Prev));
LLVM_DEBUG(dbgs() << " should be less than succeeding lower bound 0x");
LLVM_DEBUG(dbgs().write_hex(I->Lower) << "\n");
return false;
}
if (I->Upper < I->Lower) {
DEBUG(dbgs() << "Upper bound 0x");
DEBUG(dbgs().write_hex(I->Lower));
DEBUG(dbgs() << " should not be less than lower bound 0x");
DEBUG(dbgs().write_hex(I->Upper) << "\n");
LLVM_DEBUG(dbgs() << "Upper bound 0x");
LLVM_DEBUG(dbgs().write_hex(I->Lower));
LLVM_DEBUG(dbgs() << " should not be less than lower bound 0x");
LLVM_DEBUG(dbgs().write_hex(I->Upper) << "\n");
return false;
}
Prev = I->Upper;

5
llvm/include/llvm/Transforms/InstCombine/InstCombineWorklist.h
View File

@ -40,7 +40,7 @@ public:
/// in it.
void Add(Instruction *I) {
if (WorklistMap.insert(std::make_pair(I, Worklist.size())).second) {
DEBUG(dbgs() << "IC: ADD: " << *I << '\n');
LLVM_DEBUG(dbgs() << "IC: ADD: " << *I << '\n');
Worklist.push_back(I);
}
}
@ -57,7 +57,8 @@ public:
assert(Worklist.empty() && "Worklist must be empty to add initial group");
Worklist.reserve(List.size()+16);
WorklistMap.reserve(List.size());
DEBUG(dbgs() << "IC: ADDING: " << List.size() << " instrs to worklist\n");
LLVM_DEBUG(dbgs() << "IC: ADDING: " << List.size()
<< " instrs to worklist\n");
unsigned Idx = 0;
for (Instruction *I : reverse(List)) {
WorklistMap.insert(std::make_pair(I, Idx++));

2
llvm/include/llvm/Transforms/Utils/SSAUpdaterImpl.h
View File

@ -379,7 +379,7 @@ public:
Traits::AddPHIOperand(PHI, PredInfo->AvailableVal, Pred);
}
DEBUG(dbgs() << " Inserted PHI: " << *PHI << "\n");
LLVM_DEBUG(dbgs() << " Inserted PHI: " << *PHI << "\n");
// If the client wants to know about all new instructions, tell it.
if (InsertedPHIs) InsertedPHIs->push_back(PHI);

80
llvm/lib/Analysis/BlockFrequencyInfoImpl.cpp
View File

@ -316,13 +316,13 @@ bool BlockFrequencyInfoImplBase::addToDist(Distribution &Dist,
#endif
if (isLoopHeader(Resolved)) {
DEBUG(debugSuccessor("backedge"));
LLVM_DEBUG(debugSuccessor("backedge"));
Dist.addBackedge(Resolved, Weight);
return true;
}
if (Working[Resolved.Index].getContainingLoop() != OuterLoop) {
DEBUG(debugSuccessor(" exit "));
LLVM_DEBUG(debugSuccessor(" exit "));
Dist.addExit(Resolved, Weight);
return true;
}
@ -334,7 +334,7 @@ bool BlockFrequencyInfoImplBase::addToDist(Distribution &Dist,
"unhandled irreducible control flow");
// Irreducible backedge. Abort.
DEBUG(debugSuccessor("abort!!!"));
LLVM_DEBUG(debugSuccessor("abort!!!"));
return false;
}
@ -345,7 +345,7 @@ bool BlockFrequencyInfoImplBase::addToDist(Distribution &Dist,
"unhandled irreducible control flow");
}
DEBUG(debugSuccessor(" local "));
LLVM_DEBUG(debugSuccessor(" local "));
Dist.addLocal(Resolved, Weight);
return true;
}
@ -365,7 +365,7 @@ bool BlockFrequencyInfoImplBase::addLoopSuccessorsToDist(
/// Compute the loop scale for a loop.
void BlockFrequencyInfoImplBase::computeLoopScale(LoopData &Loop) {
// Compute loop scale.
DEBUG(dbgs() << "compute-loop-scale: " << getLoopName(Loop) << "\n");
LLVM_DEBUG(dbgs() << "compute-loop-scale: " << getLoopName(Loop) << "\n");
// Infinite loops need special handling. If we give the back edge an infinite
// mass, they may saturate all the other scales in the function down to 1,
@ -391,20 +391,21 @@ void BlockFrequencyInfoImplBase::computeLoopScale(LoopData &Loop) {
Loop.Scale =
ExitMass.isEmpty() ? InfiniteLoopScale : ExitMass.toScaled().inverse();
DEBUG(dbgs() << " - exit-mass = " << ExitMass << " (" << BlockMass::getFull()
<< " - " << TotalBackedgeMass << ")\n"
<< " - scale = " << Loop.Scale << "\n");
LLVM_DEBUG(dbgs() << " - exit-mass = " << ExitMass << " ("
<< BlockMass::getFull() << " - " << TotalBackedgeMass
<< ")\n"
<< " - scale = " << Loop.Scale << "\n");
}
/// Package up a loop.
void BlockFrequencyInfoImplBase::packageLoop(LoopData &Loop) {
DEBUG(dbgs() << "packaging-loop: " << getLoopName(Loop) << "\n");
LLVM_DEBUG(dbgs() << "packaging-loop: " << getLoopName(Loop) << "\n");
// Clear the subloop exits to prevent quadratic memory usage.
for (const BlockNode &M : Loop.Nodes) {
if (auto *Loop = Working[M.Index].getPackagedLoop())
Loop->Exits.clear();
DEBUG(dbgs() << " - node: " << getBlockName(M.Index) << "\n");
LLVM_DEBUG(dbgs() << " - node: " << getBlockName(M.Index) << "\n");
}
Loop.IsPackaged = true;
}
@ -426,7 +427,7 @@ void BlockFrequencyInfoImplBase::distributeMass(const BlockNode &Source,
LoopData *OuterLoop,
Distribution &Dist) {
BlockMass Mass = Working[Source.Index].getMass();
DEBUG(dbgs() << " => mass: " << Mass << "\n");
LLVM_DEBUG(dbgs() << " => mass: " << Mass << "\n");
// Distribute mass to successors as laid out in Dist.
DitheringDistributer D(Dist, Mass);
@ -436,7 +437,7 @@ void BlockFrequencyInfoImplBase::distributeMass(const BlockNode &Source,
BlockMass Taken = D.takeMass(W.Amount);
if (W.Type == Weight::Local) {
Working[W.TargetNode.Index].getMass() += Taken;
DEBUG(debugAssign(*this, D, W.TargetNode, Taken, nullptr));
LLVM_DEBUG(debugAssign(*this, D, W.TargetNode, Taken, nullptr));
continue;
}
@ -446,14 +447,14 @@ void BlockFrequencyInfoImplBase::distributeMass(const BlockNode &Source,
// Check for a backedge.
if (W.Type == Weight::Backedge) {
OuterLoop->BackedgeMass[OuterLoop->getHeaderIndex(W.TargetNode)] += Taken;
DEBUG(debugAssign(*this, D, W.TargetNode, Taken, "back"));
LLVM_DEBUG(debugAssign(*this, D, W.TargetNode, Taken, "back"));
continue;
}
// This must be an exit.
assert(W.Type == Weight::Exit);
OuterLoop->Exits.push_back(std::make_pair(W.TargetNode, Taken));
DEBUG(debugAssign(*this, D, W.TargetNode, Taken, "exit"));
LLVM_DEBUG(debugAssign(*this, D, W.TargetNode, Taken, "exit"));
}
}
@ -481,14 +482,14 @@ static void convertFloatingToInteger(BlockFrequencyInfoImplBase &BFI,
}
// Translate the floats to integers.
DEBUG(dbgs() << "float-to-int: min = " << Min << ", max = " << Max
<< ", factor = " << ScalingFactor << "\n");
LLVM_DEBUG(dbgs() << "float-to-int: min = " << Min << ", max = " << Max
<< ", factor = " << ScalingFactor << "\n");
for (size_t Index = 0; Index < BFI.Freqs.size(); ++Index) {
Scaled64 Scaled = BFI.Freqs[Index].Scaled * ScalingFactor;
BFI.Freqs[Index].Integer = std::max(UINT64_C(1), Scaled.toInt<uint64_t>());
DEBUG(dbgs() << " - " << BFI.getBlockName(Index) << ": float = "
<< BFI.Freqs[Index].Scaled << ", scaled = " << Scaled
<< ", int = " << BFI.Freqs[Index].Integer << "\n");
LLVM_DEBUG(dbgs() << " - " << BFI.getBlockName(Index) << ": float = "
<< BFI.Freqs[Index].Scaled << ", scaled = " << Scaled
<< ", int = " << BFI.Freqs[Index].Integer << "\n");
}
}
@ -497,12 +498,12 @@ static void convertFloatingToInteger(BlockFrequencyInfoImplBase &BFI,
/// Visits all the members of a loop, adjusting their BlockData according to
/// the loop's pseudo-node.
static void unwrapLoop(BlockFrequencyInfoImplBase &BFI, LoopData &Loop) {
DEBUG(dbgs() << "unwrap-loop-package: " << BFI.getLoopName(Loop)
<< ": mass = " << Loop.Mass << ", scale = " << Loop.Scale
<< "\n");
LLVM_DEBUG(dbgs() << "unwrap-loop-package: " << BFI.getLoopName(Loop)
<< ": mass = " << Loop.Mass << ", scale = " << Loop.Scale
<< "\n");
Loop.Scale *= Loop.Mass.toScaled();
Loop.IsPackaged = false;
DEBUG(dbgs() << " => combined-scale = " << Loop.Scale << "\n");
LLVM_DEBUG(dbgs() << " => combined-scale = " << Loop.Scale << "\n");
// Propagate the head scale through the loop. Since members are visited in
// RPO, the head scale will be updated by the loop scale first, and then the
@ -512,8 +513,8 @@ static void unwrapLoop(BlockFrequencyInfoImplBase &BFI, LoopData &Loop) {
Scaled64 &F = Working.isAPackage() ? Working.getPackagedLoop()->Scale
: BFI.Freqs[N.Index].Scaled;
Scaled64 New = Loop.Scale * F;
DEBUG(dbgs() << " - " << BFI.getBlockName(N) << ": " << F << " => " << New
<< "\n");
LLVM_DEBUG(dbgs() << " - " << BFI.getBlockName(N) << ": " << F << " => "
<< New << "\n");
F = New;
}
}
@ -545,7 +546,7 @@ void BlockFrequencyInfoImplBase::finalizeMetrics() {
cleanup(*this);
// Print out the final stats.
DEBUG(dump());
LLVM_DEBUG(dump());
}
BlockFrequency
@ -695,7 +696,8 @@ static void findIrreducibleHeaders(
// This is an entry block.
I->second = true;
Headers.push_back(Irr.Node);
DEBUG(dbgs() << " => entry = " << BFI.getBlockName(Irr.Node) << "\n");
LLVM_DEBUG(dbgs() << " => entry = " << BFI.getBlockName(Irr.Node)
<< "\n");
break;
}
}
@ -726,7 +728,8 @@ static void findIrreducibleHeaders(
// Store the extra header.
Headers.push_back(Irr.Node);
DEBUG(dbgs() << " => extra = " << BFI.getBlockName(Irr.Node) << "\n");
LLVM_DEBUG(dbgs() << " => extra = " << BFI.getBlockName(Irr.Node)
<< "\n");
break;
}
if (Headers.back() == Irr.Node)
@ -735,7 +738,7 @@ static void findIrreducibleHeaders(
// This is not a header.
Others.push_back(Irr.Node);
DEBUG(dbgs() << " => other = " << BFI.getBlockName(Irr.Node) << "\n");
LLVM_DEBUG(dbgs() << " => other = " << BFI.getBlockName(Irr.Node) << "\n");
}
llvm::sort(Headers.begin(), Headers.end());
llvm::sort(Others.begin(), Others.end());
@ -746,7 +749,7 @@ static void createIrreducibleLoop(
LoopData *OuterLoop, std::list<LoopData>::iterator Insert,
const std::vector<const IrreducibleGraph::IrrNode *> &SCC) {
// Translate the SCC into RPO.
DEBUG(dbgs() << " - found-scc\n");
LLVM_DEBUG(dbgs() << " - found-scc\n");
LoopData::NodeList Headers;
LoopData::NodeList Others;
@ -807,27 +810,28 @@ void BlockFrequencyInfoImplBase::adjustLoopHeaderMass(LoopData &Loop) {
BlockMass LoopMass = BlockMass::getFull();
Distribution Dist;
DEBUG(dbgs() << "adjust-loop-header-mass:\n");
LLVM_DEBUG(dbgs() << "adjust-loop-header-mass:\n");
for (uint32_t H = 0; H < Loop.NumHeaders; ++H) {
auto &HeaderNode = Loop.Nodes[H];
auto &BackedgeMass = Loop.BackedgeMass[Loop.getHeaderIndex(HeaderNode)];
DEBUG(dbgs() << " - Add back edge mass for node "
<< getBlockName(HeaderNode) << ": " << BackedgeMass << "\n");
LLVM_DEBUG(dbgs() << " - Add back edge mass for node "
<< getBlockName(HeaderNode) << ": " << BackedgeMass
<< "\n");
if (BackedgeMass.getMass() > 0)
Dist.addLocal(HeaderNode, BackedgeMass.getMass());
else
DEBUG(dbgs() << " Nothing added. Back edge mass is zero\n");
LLVM_DEBUG(dbgs() << " Nothing added. Back edge mass is zero\n");
}
DitheringDistributer D(Dist, LoopMass);
DEBUG(dbgs() << " Distribute loop mass " << LoopMass
<< " to headers using above weights\n");
LLVM_DEBUG(dbgs() << " Distribute loop mass " << LoopMass
<< " to headers using above weights\n");
for (const Weight &W : Dist.Weights) {
BlockMass Taken = D.takeMass(W.Amount);
assert(W.Type == Weight::Local && "all weights should be local");
Working[W.TargetNode.Index].getMass() = Taken;
DEBUG(debugAssign(*this, D, W.TargetNode, Taken, nullptr));
LLVM_DEBUG(debugAssign(*this, D, W.TargetNode, Taken, nullptr));
}
}
@ -838,6 +842,6 @@ void BlockFrequencyInfoImplBase::distributeIrrLoopHeaderMass(Distribution &Dist)
BlockMass Taken = D.takeMass(W.Amount);
assert(W.Type == Weight::Local && "all weights should be local");
Working[W.TargetNode.Index].getMass() = Taken;
DEBUG(debugAssign(*this, D, W.TargetNode, Taken, nullptr));
LLVM_DEBUG(debugAssign(*this, D, W.TargetNode, Taken, nullptr));
}
}

18
llvm/lib/Analysis/BranchProbabilityInfo.cpp
View File

@ -908,8 +908,9 @@ void BranchProbabilityInfo::setEdgeProbability(const BasicBlock *Src,
BranchProbability Prob) {
Probs[std::make_pair(Src, IndexInSuccessors)] = Prob;
Handles.insert(BasicBlockCallbackVH(Src, this));
DEBUG(dbgs() << "set edge " << Src->getName() << " -> " << IndexInSuccessors
<< " successor probability to " << Prob << "\n");
LLVM_DEBUG(dbgs() << "set edge " << Src->getName() << " -> "
<< IndexInSuccessors << " successor probability to " << Prob
<< "\n");
}
raw_ostream &
@ -934,8 +935,8 @@ void BranchProbabilityInfo::eraseBlock(const BasicBlock *BB) {
void BranchProbabilityInfo::calculate(const Function &F, const LoopInfo &LI,
const TargetLibraryInfo *TLI) {
DEBUG(dbgs() << "---- Branch Probability Info : " << F.getName()
<< " ----\n\n");
LLVM_DEBUG(dbgs() << "---- Branch Probability Info : " << F.getName()
<< " ----\n\n");
LastF = &F; // Store the last function we ran on for printing.
assert(PostDominatedByUnreachable.empty());
assert(PostDominatedByColdCall.empty());
@ -953,18 +954,19 @@ void BranchProbabilityInfo::calculate(const Function &F, const LoopInfo &LI,
if (Scc.size() == 1)
continue;
DEBUG(dbgs() << "BPI: SCC " << SccNum << ":");
LLVM_DEBUG(dbgs() << "BPI: SCC " << SccNum << ":");
for (auto *BB : Scc) {
DEBUG(dbgs() << " " << BB->getName());
LLVM_DEBUG(dbgs() << " " << BB->getName());
SccI.SccNums[BB] = SccNum;
}
DEBUG(dbgs() << "\n");
LLVM_DEBUG(dbgs() << "\n");
}
// Walk the basic blocks in post-order so that we can build up state about
// the successors of a block iteratively.
for (auto BB : post_order(&F.getEntryBlock())) {
DEBUG(dbgs() << "Computing probabilities for " << BB->getName() << "\n");
LLVM_DEBUG(dbgs() << "Computing probabilities for " << BB->getName()
<< "\n");
updatePostDominatedByUnreachable(BB);
updatePostDominatedByColdCall(BB);
// If there is no at least two successors, no sense to set probability.

5
llvm/lib/Analysis/CFLAndersAliasAnalysis.cpp
View File

@ -855,8 +855,9 @@ AliasResult CFLAndersAAResult::query(const MemoryLocation &LocA,
if (!Fn) {
// The only times this is known to happen are when globals + InlineAsm are
// involved
DEBUG(dbgs()
<< "CFLAndersAA: could not extract parent function information.\n");
LLVM_DEBUG(
dbgs()
<< "CFLAndersAA: could not extract parent function information.\n");
return MayAlias;
}
} else {

5
llvm/lib/Analysis/CFLSteensAliasAnalysis.cpp
View File

@ -276,8 +276,9 @@ AliasResult CFLSteensAAResult::query(const MemoryLocation &LocA,
if (!MaybeFnA && !MaybeFnB) {
// The only times this is known to happen are when globals + InlineAsm are
// involved
DEBUG(dbgs()
<< "CFLSteensAA: could not extract parent function information.\n");
LLVM_DEBUG(
dbgs()
<< "CFLSteensAA: could not extract parent function information.\n");
return MayAlias;
}

35
llvm/lib/Analysis/CGSCCPassManager.cpp
View File

@ -75,7 +75,7 @@ PassManager<LazyCallGraph::SCC, CGSCCAnalysisManager, LazyCallGraph &,
// If the CGSCC pass wasn't able to provide a valid updated SCC, the
// current SCC may simply need to be skipped if invalid.
if (UR.InvalidatedSCCs.count(C)) {
DEBUG(dbgs() << "Skipping invalidated root or island SCC!\n");
LLVM_DEBUG(dbgs() << "Skipping invalidated root or island SCC!\n");
break;
}
// Check that we didn't miss any update scenario.
@ -353,7 +353,8 @@ incorporateNewSCCRange(const SCCRangeT &NewSCCRange, LazyCallGraph &G,
// Add the current SCC to the worklist as its shape has changed.
UR.CWorklist.insert(C);
DEBUG(dbgs() << "Enqueuing the existing SCC in the worklist:" << *C << "\n");
LLVM_DEBUG(dbgs() << "Enqueuing the existing SCC in the worklist:" << *C
<< "\n");
SCC *OldC = C;
@ -389,7 +390,7 @@ incorporateNewSCCRange(const SCCRangeT &NewSCCRange, LazyCallGraph &G,
assert(C != &NewC && "No need to re-visit the current SCC!");
assert(OldC != &NewC && "Already handled the original SCC!");
UR.CWorklist.insert(&NewC);
DEBUG(dbgs() << "Enqueuing a newly formed SCC:" << NewC << "\n");
LLVM_DEBUG(dbgs() << "Enqueuing a newly formed SCC:" << NewC << "\n");
// Ensure new SCCs' function analyses are updated.
if (NeedFAMProxy)
@ -514,8 +515,8 @@ LazyCallGraph::SCC &llvm::updateCGAndAnalysisManagerForFunctionPass(
return false;
RC->removeOutgoingEdge(N, *TargetN);
DEBUG(dbgs() << "Deleting outgoing edge from '" << N
<< "' to '" << TargetN << "'\n");
LLVM_DEBUG(dbgs() << "Deleting outgoing edge from '"
<< N << "' to '" << TargetN << "'\n");
return true;
}),
DeadTargets.end());
@ -546,8 +547,8 @@ LazyCallGraph::SCC &llvm::updateCGAndAnalysisManagerForFunctionPass(
assert(NewRC != RC && "Should not encounter the current RefSCC further "
"in the postorder list of new RefSCCs.");
UR.RCWorklist.insert(NewRC);
DEBUG(dbgs() << "Enqueuing a new RefSCC in the update worklist: "
<< *NewRC << "\n");
LLVM_DEBUG(dbgs() << "Enqueuing a new RefSCC in the update worklist: "
<< *NewRC << "\n");
}
}
@ -564,8 +565,8 @@ LazyCallGraph::SCC &llvm::updateCGAndAnalysisManagerForFunctionPass(
assert(RC->isAncestorOf(TargetRC) &&
"Cannot potentially form RefSCC cycles here!");
RC->switchOutgoingEdgeToRef(N, *RefTarget);
DEBUG(dbgs() << "Switch outgoing call edge to a ref edge from '" << N
<< "' to '" << *RefTarget << "'\n");
LLVM_DEBUG(dbgs() << "Switch outgoing call edge to a ref edge from '" << N
<< "' to '" << *RefTarget << "'\n");
continue;
}
@ -593,12 +594,12 @@ LazyCallGraph::SCC &llvm::updateCGAndAnalysisManagerForFunctionPass(
assert(RC->isAncestorOf(TargetRC) &&
"Cannot potentially form RefSCC cycles here!");
RC->switchOutgoingEdgeToCall(N, *CallTarget);
DEBUG(dbgs() << "Switch outgoing ref edge to a call edge from '" << N
<< "' to '" << *CallTarget << "'\n");
LLVM_DEBUG(dbgs() << "Switch outgoing ref edge to a call edge from '" << N
<< "' to '" << *CallTarget << "'\n");
continue;
}
DEBUG(dbgs() << "Switch an internal ref edge to a call edge from '" << N
<< "' to '" << *CallTarget << "'\n");
LLVM_DEBUG(dbgs() << "Switch an internal ref edge to a call edge from '"
<< N << "' to '" << *CallTarget << "'\n");
// Otherwise we are switching an internal ref edge to a call edge. This
// may merge away some SCCs, and we add those to the UpdateResult. We also
@ -661,14 +662,14 @@ LazyCallGraph::SCC &llvm::updateCGAndAnalysisManagerForFunctionPass(
// post-order sequence, and may end up observing more precise context to
// optimize the current SCC.
UR.CWorklist.insert(C);
DEBUG(dbgs() << "Enqueuing the existing SCC in the worklist: " << *C
<< "\n");
LLVM_DEBUG(dbgs() << "Enqueuing the existing SCC in the worklist: " << *C
<< "\n");
// Enqueue in reverse order as we pop off the back of the worklist.
for (SCC &MovedC : llvm::reverse(make_range(RC->begin() + InitialSCCIndex,
RC->begin() + NewSCCIndex))) {
UR.CWorklist.insert(&MovedC);
DEBUG(dbgs() << "Enqueuing a newly earlier in post-order SCC: "
<< MovedC << "\n");
LLVM_DEBUG(dbgs() << "Enqueuing a newly earlier in post-order SCC: "
<< MovedC << "\n");
}
}
}

50
llvm/lib/Analysis/CallGraphSCCPass.cpp
View File

@ -162,8 +162,8 @@ bool CGPassManager::RunPassOnSCC(Pass *P, CallGraphSCC &CurSCC,
// The function pass(es) modified the IR, they may have clobbered the
// callgraph.
if (Changed && CallGraphUpToDate) {
DEBUG(dbgs() << "CGSCCPASSMGR: Pass Dirtied SCC: "
<< P->getPassName() << '\n');
LLVM_DEBUG(dbgs() << "CGSCCPASSMGR: Pass Dirtied SCC: " << P->getPassName()
<< '\n');
CallGraphUpToDate = false;
}
return Changed;
@ -181,12 +181,11 @@ bool CGPassManager::RunPassOnSCC(Pass *P, CallGraphSCC &CurSCC,
bool CGPassManager::RefreshCallGraph(const CallGraphSCC &CurSCC, CallGraph &CG,
bool CheckingMode) {
DenseMap<Value*, CallGraphNode*> CallSites;
DEBUG(dbgs() << "CGSCCPASSMGR: Refreshing SCC with " << CurSCC.size()
<< " nodes:\n";
for (CallGraphNode *CGN : CurSCC)
CGN->dump();
);
LLVM_DEBUG(dbgs() << "CGSCCPASSMGR: Refreshing SCC with " << CurSCC.size()
<< " nodes:\n";
for (CallGraphNode *CGN
: CurSCC) CGN->dump(););
bool MadeChange = false;
bool DevirtualizedCall = false;
@ -307,8 +306,8 @@ bool CGPassManager::RefreshCallGraph(const CallGraphSCC &CurSCC, CallGraph &CG,
// one.
if (!ExistingNode->getFunction()) {
DevirtualizedCall = true;
DEBUG(dbgs() << " CGSCCPASSMGR: Devirtualized call to '"
<< Callee->getName() << "'\n");
LLVM_DEBUG(dbgs() << " CGSCCPASSMGR: Devirtualized call to '"
<< Callee->getName() << "'\n");
}
} else {
CalleeNode = CG.getCallsExternalNode();
@ -363,17 +362,15 @@ bool CGPassManager::RefreshCallGraph(const CallGraphSCC &CurSCC, CallGraph &CG,
CallSites.clear();
}
DEBUG(if (MadeChange) {
dbgs() << "CGSCCPASSMGR: Refreshed SCC is now:\n";
for (CallGraphNode *CGN : CurSCC)
CGN->dump();
if (DevirtualizedCall)
dbgs() << "CGSCCPASSMGR: Refresh devirtualized a call!\n";
} else {
dbgs() << "CGSCCPASSMGR: SCC Refresh didn't change call graph.\n";
}
);
LLVM_DEBUG(if (MadeChange) {
dbgs() << "CGSCCPASSMGR: Refreshed SCC is now:\n";
for (CallGraphNode *CGN : CurSCC)
CGN->dump();
if (DevirtualizedCall)
dbgs() << "CGSCCPASSMGR: Refresh devirtualized a call!\n";
} else {
dbgs() << "CGSCCPASSMGR: SCC Refresh didn't change call graph.\n";
});
(void)MadeChange;
return DevirtualizedCall;
@ -472,16 +469,17 @@ bool CGPassManager::runOnModule(Module &M) {
unsigned Iteration = 0;
bool DevirtualizedCall = false;
do {
DEBUG(if (Iteration)
dbgs() << " SCCPASSMGR: Re-visiting SCC, iteration #"
<< Iteration << '\n');
LLVM_DEBUG(if (Iteration) dbgs()
<< " SCCPASSMGR: Re-visiting SCC, iteration #" << Iteration
<< '\n');
DevirtualizedCall = false;
Changed |= RunAllPassesOnSCC(CurSCC, CG, DevirtualizedCall);
} while (Iteration++ < MaxIterations && DevirtualizedCall);
if (DevirtualizedCall)
DEBUG(dbgs() << " CGSCCPASSMGR: Stopped iteration after " << Iteration
<< " times, due to -max-cg-scc-iterations\n");
LLVM_DEBUG(dbgs() << " CGSCCPASSMGR: Stopped iteration after "
<< Iteration
<< " times, due to -max-cg-scc-iterations\n");
MaxSCCIterations.updateMax(Iteration);
}

2
llvm/lib/Analysis/CodeMetrics.cpp
View File

@ -61,7 +61,7 @@ static void completeEphemeralValues(SmallPtrSetImpl<const Value *> &Visited,
continue;
EphValues.insert(V);
DEBUG(dbgs() << "Ephemeral Value: " << *V << "\n");
LLVM_DEBUG(dbgs() << "Ephemeral Value: " << *V << "\n");
// Append any more operands to consider.
appendSpeculatableOperands(V, Visited, Worklist);

8
llvm/lib/Analysis/DemandedBits.cpp
View File

@ -283,7 +283,7 @@ void DemandedBits::performAnalysis() {
if (!isAlwaysLive(&I))
continue;
DEBUG(dbgs() << "DemandedBits: Root: " << I << "\n");
LLVM_DEBUG(dbgs() << "DemandedBits: Root: " << I << "\n");
// For integer-valued instructions, set up an initial empty set of alive
// bits and add the instruction to the work list. For other instructions
// add their operands to the work list (for integer values operands, mark
@ -313,13 +313,13 @@ void DemandedBits::performAnalysis() {
while (!Worklist.empty()) {
Instruction *UserI = Worklist.pop_back_val();
DEBUG(dbgs() << "DemandedBits: Visiting: " << *UserI);
LLVM_DEBUG(dbgs() << "DemandedBits: Visiting: " << *UserI);
APInt AOut;
if (UserI->getType()->isIntegerTy()) {
AOut = AliveBits[UserI];
DEBUG(dbgs() << " Alive Out: " << AOut);
LLVM_DEBUG(dbgs() << " Alive Out: " << AOut);
}
DEBUG(dbgs() << "\n");
LLVM_DEBUG(dbgs() << "\n");
if (!UserI->getType()->isIntegerTy())
Visited.insert(UserI);

479
llvm/lib/Analysis/DependenceAnalysis.cpp
View File

File diff suppressed because it is too large Load Diff

17
llvm/lib/Analysis/IVUsers.cpp
View File

@ -235,13 +235,13 @@ bool IVUsers::AddUsersImpl(Instruction *I,
if (LI->getLoopFor(User->getParent()) != L) {
if (isa<PHINode>(User) || Processed.count(User) ||
!AddUsersImpl(User, SimpleLoopNests)) {
DEBUG(dbgs() << "FOUND USER in other loop: " << *User << '\n'
<< " OF SCEV: " << *ISE << '\n');
LLVM_DEBUG(dbgs() << "FOUND USER in other loop: " << *User << '\n'
<< " OF SCEV: " << *ISE << '\n');
AddUserToIVUsers = true;
}
} else if (Processed.count(User) || !AddUsersImpl(User, SimpleLoopNests)) {
DEBUG(dbgs() << "FOUND USER: " << *User << '\n'
<< " OF SCEV: " << *ISE << '\n');
LLVM_DEBUG(dbgs() << "FOUND USER: " << *User << '\n'
<< " OF SCEV: " << *ISE << '\n');
AddUserToIVUsers = true;
}
@ -274,14 +274,15 @@ bool IVUsers::AddUsersImpl(Instruction *I,
// If we normalized the expression, but denormalization doesn't give the
// original one, discard this user.
if (OriginalISE != DenormalizedISE) {
DEBUG(dbgs() << " DISCARDING (NORMALIZATION ISN'T INVERTIBLE): "
<< *ISE << '\n');
LLVM_DEBUG(dbgs()
<< " DISCARDING (NORMALIZATION ISN'T INVERTIBLE): "
<< *ISE << '\n');
IVUses.pop_back();
return false;
}
}
DEBUG(if (SE->getSCEV(I) != ISE)
dbgs() << " NORMALIZED TO: " << *ISE << '\n');
LLVM_DEBUG(if (SE->getSCEV(I) != ISE) dbgs()
<< " NORMALIZED TO: " << *ISE << '\n');
}
}
return true;

10
llvm/lib/Analysis/IndirectCallPromotionAnalysis.cpp
View File

@ -71,19 +71,19 @@ uint32_t ICallPromotionAnalysis::getProfitablePromotionCandidates(
const Instruction *Inst, uint32_t NumVals, uint64_t TotalCount) {
ArrayRef<InstrProfValueData> ValueDataRef(ValueDataArray.get(), NumVals);
DEBUG(dbgs() << " \nWork on callsite " << *Inst << " Num_targets: " << NumVals
<< "\n");
LLVM_DEBUG(dbgs() << " \nWork on callsite " << *Inst
<< " Num_targets: " << NumVals << "\n");
uint32_t I = 0;
uint64_t RemainingCount = TotalCount;
for (; I < MaxNumPromotions && I < NumVals; I++) {
uint64_t Count = ValueDataRef[I].Count;
assert(Count <= RemainingCount);
DEBUG(dbgs() << " Candidate " << I << " Count=" << Count
<< " Target_func: " << ValueDataRef[I].Value << "\n");
LLVM_DEBUG(dbgs() << " Candidate " << I << " Count=" << Count
<< " Target_func: " << ValueDataRef[I].Value << "\n");
if (!isPromotionProfitable(Count, TotalCount, RemainingCount)) {
DEBUG(dbgs() << " Not promote: Cold target.\n");
LLVM_DEBUG(dbgs() << " Not promote: Cold target.\n");
return I;
}
RemainingCount -= Count;

14
llvm/lib/Analysis/InlineCost.cpp
View File

@ -921,14 +921,14 @@ void CallAnalyzer::updateThreshold(CallSite CS, Function &Callee) {
BlockFrequencyInfo *CallerBFI = GetBFI ? &((*GetBFI)(*Caller)) : nullptr;
auto HotCallSiteThreshold = getHotCallSiteThreshold(CS, CallerBFI);
if (!Caller->optForSize() && HotCallSiteThreshold) {
DEBUG(dbgs() << "Hot callsite.\n");
LLVM_DEBUG(dbgs() << "Hot callsite.\n");
// FIXME: This should update the threshold only if it exceeds the
// current threshold, but AutoFDO + ThinLTO currently relies on this
// behavior to prevent inlining of hot callsites during ThinLTO
// compile phase.
Threshold = HotCallSiteThreshold.getValue();
} else if (isColdCallSite(CS, CallerBFI)) {
DEBUG(dbgs() << "Cold callsite.\n");
LLVM_DEBUG(dbgs() << "Cold callsite.\n");
// Do not apply bonuses for a cold callsite including the
// LastCallToStatic bonus. While this bonus might result in code size
// reduction, it can cause the size of a non-cold caller to increase
@ -939,13 +939,13 @@ void CallAnalyzer::updateThreshold(CallSite CS, Function &Callee) {
// Use callee's global profile information only if we have no way of
// determining this via callsite information.
if (PSI->isFunctionEntryHot(&Callee)) {
DEBUG(dbgs() << "Hot callee.\n");
LLVM_DEBUG(dbgs() << "Hot callee.\n");
// If callsite hotness can not be determined, we may still know
// that the callee is hot and treat it as a weaker hint for threshold
// increase.
Threshold = MaxIfValid(Threshold, Params.HintThreshold);
} else if (PSI->isFunctionEntryCold(&Callee)) {
DEBUG(dbgs() << "Cold callee.\n");
LLVM_DEBUG(dbgs() << "Cold callee.\n");
// Do not apply bonuses for a cold callee including the
// LastCallToStatic bonus. While this bonus might result in code size
// reduction, it can cause the size of a non-cold caller to increase
@ -2002,14 +2002,14 @@ InlineCost llvm::getInlineCost(
CS.isNoInline())
return llvm::InlineCost::getNever();
DEBUG(llvm::dbgs() << " Analyzing call of " << Callee->getName()
<< "... (caller:" << Caller->getName() << ")\n");
LLVM_DEBUG(llvm::dbgs() << " Analyzing call of " << Callee->getName()
<< "... (caller:" << Caller->getName() << ")\n");
CallAnalyzer CA(CalleeTTI, GetAssumptionCache, GetBFI, PSI, ORE, *Callee, CS,
Params);
bool ShouldInline = CA.analyzeCall(CS);
DEBUG(CA.dump());
LLVM_DEBUG(CA.dump());
// Check if there was a reason to force inlining or no inlining.
if (!ShouldInline && CA.getCost() < CA.getThreshold())

19
llvm/lib/Analysis/LazyCallGraph.cpp
View File

@ -66,15 +66,15 @@ static void addEdge(SmallVectorImpl<LazyCallGraph::Edge> &Edges,
if (!EdgeIndexMap.insert({&N, Edges.size()}).second)
return;
DEBUG(dbgs() << " Added callable function: " << N.getName() << "\n");
LLVM_DEBUG(dbgs() << " Added callable function: " << N.getName() << "\n");
Edges.emplace_back(LazyCallGraph::Edge(N, EK));
}
LazyCallGraph::EdgeSequence &LazyCallGraph::Node::populateSlow() {
assert(!Edges && "Must not have already populated the edges for this node!");
DEBUG(dbgs() << " Adding functions called by '" << getName()
<< "' to the graph.\n");
LLVM_DEBUG(dbgs() << " Adding functions called by '" << getName()
<< "' to the graph.\n");
Edges = EdgeSequence();
@ -152,8 +152,8 @@ static bool isKnownLibFunction(Function &F, TargetLibraryInfo &TLI) {
}
LazyCallGraph::LazyCallGraph(Module &M, TargetLibraryInfo &TLI) {
DEBUG(dbgs() << "Building CG for module: " << M.getModuleIdentifier()
<< "\n");
LLVM_DEBUG(dbgs() << "Building CG for module: " << M.getModuleIdentifier()
<< "\n");
for (Function &F : M) {
if (F.isDeclaration())
continue;
@ -168,8 +168,8 @@ LazyCallGraph::LazyCallGraph(Module &M, TargetLibraryInfo &TLI) {
// External linkage defined functions have edges to them from other
// modules.
DEBUG(dbgs() << " Adding '" << F.getName()
<< "' to entry set of the graph.\n");
LLVM_DEBUG(dbgs() << " Adding '" << F.getName()
<< "' to entry set of the graph.\n");
addEdge(EntryEdges.Edges, EntryEdges.EdgeIndexMap, get(F), Edge::Ref);
}
@ -181,8 +181,9 @@ LazyCallGraph::LazyCallGraph(Module &M, TargetLibraryInfo &TLI) {
if (Visited.insert(GV.getInitializer()).second)
Worklist.push_back(GV.getInitializer());
DEBUG(dbgs() << " Adding functions referenced by global initializers to the "
"entry set.\n");
LLVM_DEBUG(
dbgs() << " Adding functions referenced by global initializers to the "
"entry set.\n");
visitReferences(Worklist, Visited, [&](Function &F) {
addEdge(EntryEdges.Edges, EntryEdges.EdgeIndexMap, get(F),
LazyCallGraph::Edge::Ref);

55
llvm/lib/Analysis/LazyValueInfo.cpp
View File

@ -392,8 +392,8 @@ namespace {
if (!BlockValueSet.insert(BV).second)
return false; // It's already in the stack.
DEBUG(dbgs() << "PUSH: " << *BV.second << " in " << BV.first->getName()
<< "\n");
LLVM_DEBUG(dbgs() << "PUSH: " << *BV.second << " in "
<< BV.first->getName() << "\n");
BlockValueStack.push_back(BV);
return true;
}
@ -508,7 +508,8 @@ void LazyValueInfoImpl::solve() {
// PredicateInfo is used in LVI or CVP, we should be able to make the
// overdefined cache global, and remove this throttle.
if (processedCount > MaxProcessedPerValue) {
DEBUG(dbgs() << "Giving up on stack because we are getting too deep\n");
LLVM_DEBUG(
dbgs() << "Giving up on stack because we are getting too deep\n");
// Fill in the original values
while (!StartingStack.empty()) {
std::pair<BasicBlock *, Value *> &e = StartingStack.back();
@ -529,8 +530,9 @@ void LazyValueInfoImpl::solve() {
assert(TheCache.hasCachedValueInfo(e.second, e.first) &&
"Result should be in cache!");
DEBUG(dbgs() << "POP " << *e.second << " in " << e.first->getName()
<< " = " << TheCache.getCachedValueInfo(e.second, e.first) << "\n");
LLVM_DEBUG(
dbgs() << "POP " << *e.second << " in " << e.first->getName() << " = "
<< TheCache.getCachedValueInfo(e.second, e.first) << "\n");
BlockValueStack.pop_back();
BlockValueSet.erase(e);
@ -581,8 +583,8 @@ bool LazyValueInfoImpl::solveBlockValue(Value *Val, BasicBlock *BB) {
if (TheCache.hasCachedValueInfo(Val, BB)) {
// If we have a cached value, use that.
DEBUG(dbgs() << " reuse BB '" << BB->getName()
<< "' val=" << TheCache.getCachedValueInfo(Val, BB) << '\n');
LLVM_DEBUG(dbgs() << " reuse BB '" << BB->getName() << "' val="
<< TheCache.getCachedValueInfo(Val, BB) << '\n');
// Since we're reusing a cached value, we don't need to update the
// OverDefinedCache. The cache will have been properly updated whenever the
@ -637,8 +639,8 @@ bool LazyValueInfoImpl::solveBlockValueImpl(ValueLatticeElement &Res,
return solveBlockValueBinaryOp(Res, BO, BB);
}
DEBUG(dbgs() << " compute BB '" << BB->getName()
<< "' - unknown inst def found.\n");
LLVM_DEBUG(dbgs() << " compute BB '" << BB->getName()
<< "' - unknown inst def found.\n");
Res = getFromRangeMetadata(BBI);
return true;
}
@ -733,8 +735,8 @@ bool LazyValueInfoImpl::solveBlockValueNonLocal(ValueLatticeElement &BBLV,
// If we hit overdefined, exit early. The BlockVals entry is already set
// to overdefined.
if (Result.isOverdefined()) {
DEBUG(dbgs() << " compute BB '" << BB->getName()
<< "' - overdefined because of pred (non local).\n");
LLVM_DEBUG(dbgs() << " compute BB '" << BB->getName()
<< "' - overdefined because of pred (non local).\n");
// Before giving up, see if we can prove the pointer non-null local to
// this particular block.
if (Val->getType()->isPointerTy() &&
@ -777,8 +779,8 @@ bool LazyValueInfoImpl::solveBlockValuePHINode(ValueLatticeElement &BBLV,
// If we hit overdefined, exit early. The BlockVals entry is already set
// to overdefined.
if (Result.isOverdefined()) {
DEBUG(dbgs() << " compute BB '" << BB->getName()
<< "' - overdefined because of pred (local).\n");
LLVM_DEBUG(dbgs() << " compute BB '" << BB->getName()
<< "' - overdefined because of pred (local).\n");
BBLV = Result;
return true;
@ -968,8 +970,8 @@ bool LazyValueInfoImpl::solveBlockValueCast(ValueLatticeElement &BBLV,
break;
default:
// Unhandled instructions are overdefined.
DEBUG(dbgs() << " compute BB '" << BB->getName()
<< "' - overdefined (unknown cast).\n");
LLVM_DEBUG(dbgs() << " compute BB '" << BB->getName()
<< "' - overdefined (unknown cast).\n");
BBLV = ValueLatticeElement::getOverdefined();
return true;
}
@ -1027,8 +1029,8 @@ bool LazyValueInfoImpl::solveBlockValueBinaryOp(ValueLatticeElement &BBLV,
break;
default:
// Unhandled instructions are overdefined.
DEBUG(dbgs() << " compute BB '" << BB->getName()
<< "' - overdefined (unknown binary operator).\n");
LLVM_DEBUG(dbgs() << " compute BB '" << BB->getName()
<< "' - overdefined (unknown binary operator).\n");
BBLV = ValueLatticeElement::getOverdefined();
return true;
};
@ -1399,8 +1401,8 @@ bool LazyValueInfoImpl::getEdgeValue(Value *Val, BasicBlock *BBFrom,
ValueLatticeElement LazyValueInfoImpl::getValueInBlock(Value *V, BasicBlock *BB,
Instruction *CxtI) {
DEBUG(dbgs() << "LVI Getting block end value " << *V << " at '"
<< BB->getName() << "'\n");
LLVM_DEBUG(dbgs() << "LVI Getting block end value " << *V << " at '"
<< BB->getName() << "'\n");
assert(BlockValueStack.empty() && BlockValueSet.empty());
if (!hasBlockValue(V, BB)) {
@ -1410,13 +1412,13 @@ ValueLatticeElement LazyValueInfoImpl::getValueInBlock(Value *V, BasicBlock *BB,
ValueLatticeElement Result = getBlockValue(V, BB);
intersectAssumeOrGuardBlockValueConstantRange(V, Result, CxtI);
DEBUG(dbgs() << " Result = " << Result << "\n");
LLVM_DEBUG(dbgs() << " Result = " << Result << "\n");
return Result;
}
ValueLatticeElement LazyValueInfoImpl::getValueAt(Value *V, Instruction *CxtI) {
DEBUG(dbgs() << "LVI Getting value " << *V << " at '"
<< CxtI->getName() << "'\n");
LLVM_DEBUG(dbgs() << "LVI Getting value " << *V << " at '" << CxtI->getName()
<< "'\n");
if (auto *C = dyn_cast<Constant>(V))
return ValueLatticeElement::get(C);
@ -1426,15 +1428,16 @@ ValueLatticeElement LazyValueInfoImpl::getValueAt(Value *V, Instruction *CxtI) {
Result = getFromRangeMetadata(I);
intersectAssumeOrGuardBlockValueConstantRange(V, Result, CxtI);
DEBUG(dbgs() << " Result = " << Result << "\n");
LLVM_DEBUG(dbgs() << " Result = " << Result << "\n");
return Result;
}
ValueLatticeElement LazyValueInfoImpl::
getValueOnEdge(Value *V, BasicBlock *FromBB, BasicBlock *ToBB,
Instruction *CxtI) {
DEBUG(dbgs() << "LVI Getting edge value " << *V << " from '"
<< FromBB->getName() << "' to '" << ToBB->getName() << "'\n");
LLVM_DEBUG(dbgs() << "LVI Getting edge value " << *V << " from '"
<< FromBB->getName() << "' to '" << ToBB->getName()
<< "'\n");
ValueLatticeElement Result;
if (!getEdgeValue(V, FromBB, ToBB, Result, CxtI)) {
@ -1444,7 +1447,7 @@ getValueOnEdge(Value *V, BasicBlock *FromBB, BasicBlock *ToBB,
assert(WasFastQuery && "More work to do after problem solved?");
}
DEBUG(dbgs() << " Result = " << Result << "\n");
LLVM_DEBUG(dbgs() << " Result = " << Result << "\n");
return Result;
}

198
llvm/lib/Analysis/LoopAccessAnalysis.cpp
View File

@ -165,8 +165,8 @@ const SCEV *llvm::replaceSymbolicStrideSCEV(PredicatedScalarEvolution &PSE,
PSE.addPredicate(*SE->getEqualPredicate(U, CT));
auto *Expr = PSE.getSCEV(Ptr);
DEBUG(dbgs() << "LAA: Replacing SCEV: " << *OrigSCEV << " by: " << *Expr
<< "\n");
LLVM_DEBUG(dbgs() << "LAA: Replacing SCEV: " << *OrigSCEV
<< " by: " << *Expr << "\n");
return Expr;
}
@ -684,7 +684,7 @@ bool AccessAnalysis::createCheckForAccess(RuntimePointerChecking &RtCheck,
bool IsWrite = Access.getInt();
RtCheck.insert(TheLoop, Ptr, IsWrite, DepId, ASId, StridesMap, PSE);
DEBUG(dbgs() << "LAA: Found a runtime check ptr:" << *Ptr << '\n');
LLVM_DEBUG(dbgs() << "LAA: Found a runtime check ptr:" << *Ptr << '\n');
return true;
}
@ -729,7 +729,7 @@ bool AccessAnalysis::canCheckPtrAtRT(RuntimePointerChecking &RtCheck,
if (!createCheckForAccess(RtCheck, Access, StridesMap, DepSetId, TheLoop,
RunningDepId, ASId, ShouldCheckWrap, false)) {
DEBUG(dbgs() << "LAA: Can't find bounds for ptr:" << *Ptr << '\n');
LLVM_DEBUG(dbgs() << "LAA: Can't find bounds for ptr:" << *Ptr << '\n');
Retries.push_back(Access);
CanDoAliasSetRT = false;
}
@ -791,8 +791,9 @@ bool AccessAnalysis::canCheckPtrAtRT(RuntimePointerChecking &RtCheck,
unsigned ASi = PtrI->getType()->getPointerAddressSpace();
unsigned ASj = PtrJ->getType()->getPointerAddressSpace();
if (ASi != ASj) {
DEBUG(dbgs() << "LAA: Runtime check would require comparison between"
" different address spaces\n");
LLVM_DEBUG(
dbgs() << "LAA: Runtime check would require comparison between"
" different address spaces\n");
return false;
}
}
@ -801,8 +802,8 @@ bool AccessAnalysis::canCheckPtrAtRT(RuntimePointerChecking &RtCheck,
if (NeedRTCheck && CanDoRT)
RtCheck.generateChecks(DepCands, IsDepCheckNeeded);
DEBUG(dbgs() << "LAA: We need to do " << RtCheck.getNumberOfChecks()
<< " pointer comparisons.\n");
LLVM_DEBUG(dbgs() << "LAA: We need to do " << RtCheck.getNumberOfChecks()
<< " pointer comparisons.\n");
RtCheck.Need = NeedRTCheck;
@ -817,10 +818,10 @@ void AccessAnalysis::processMemAccesses() {
// process read-only pointers. This allows us to skip dependence tests for
// read-only pointers.
DEBUG(dbgs() << "LAA: Processing memory accesses...\n");
DEBUG(dbgs() << " AST: "; AST.dump());
DEBUG(dbgs() << "LAA: Accesses(" << Accesses.size() << "):\n");
DEBUG({
LLVM_DEBUG(dbgs() << "LAA: Processing memory accesses...\n");
LLVM_DEBUG(dbgs() << " AST: "; AST.dump());
LLVM_DEBUG(dbgs() << "LAA: Accesses(" << Accesses.size() << "):\n");
LLVM_DEBUG({
for (auto A : Accesses)
dbgs() << "\t" << *A.getPointer() << " (" <<
(A.getInt() ? "write" : (ReadOnlyPtr.count(A.getPointer()) ?
@ -904,7 +905,8 @@ void AccessAnalysis::processMemAccesses() {
ValueVector TempObjects;
GetUnderlyingObjects(Ptr, TempObjects, DL, LI);
DEBUG(dbgs() << "Underlying objects for pointer " << *Ptr << "\n");
LLVM_DEBUG(dbgs()
<< "Underlying objects for pointer " << *Ptr << "\n");
for (Value *UnderlyingObj : TempObjects) {
// nullptr never alias, don't join sets for pointer that have "null"
// in their UnderlyingObjects list.
@ -917,7 +919,7 @@ void AccessAnalysis::processMemAccesses() {
DepCands.unionSets(Access, Prev->second);
ObjToLastAccess[UnderlyingObj] = Access;
DEBUG(dbgs() << " " << *UnderlyingObj << "\n");
LLVM_DEBUG(dbgs() << " " << *UnderlyingObj << "\n");
}
}
}
@ -989,8 +991,8 @@ int64_t llvm::getPtrStride(PredicatedScalarEvolution &PSE, Value *Ptr,
// Make sure that the pointer does not point to aggregate types.
auto *PtrTy = cast<PointerType>(Ty);
if (PtrTy->getElementType()->isAggregateType()) {
DEBUG(dbgs() << "LAA: Bad stride - Not a pointer to a scalar type" << *Ptr
<< "\n");
LLVM_DEBUG(dbgs() << "LAA: Bad stride - Not a pointer to a scalar type"
<< *Ptr << "\n");
return 0;
}
@ -1001,15 +1003,15 @@ int64_t llvm::getPtrStride(PredicatedScalarEvolution &PSE, Value *Ptr,
AR = PSE.getAsAddRec(Ptr);
if (!AR) {
DEBUG(dbgs() << "LAA: Bad stride - Not an AddRecExpr pointer " << *Ptr
<< " SCEV: " << *PtrScev << "\n");
LLVM_DEBUG(dbgs() << "LAA: Bad stride - Not an AddRecExpr pointer " << *Ptr
<< " SCEV: " << *PtrScev << "\n");
return 0;
}
// The accesss function must stride over the innermost loop.
if (Lp != AR->getLoop()) {
DEBUG(dbgs() << "LAA: Bad stride - Not striding over innermost loop " <<
*Ptr << " SCEV: " << *AR << "\n");
LLVM_DEBUG(dbgs() << "LAA: Bad stride - Not striding over innermost loop "
<< *Ptr << " SCEV: " << *AR << "\n");
return 0;
}
@ -1029,13 +1031,14 @@ int64_t llvm::getPtrStride(PredicatedScalarEvolution &PSE, Value *Ptr,
if (Assume) {
PSE.setNoOverflow(Ptr, SCEVWrapPredicate::IncrementNUSW);
IsNoWrapAddRec = true;
DEBUG(dbgs() << "LAA: Pointer may wrap in the address space:\n"
<< "LAA: Pointer: " << *Ptr << "\n"
<< "LAA: SCEV: " << *AR << "\n"
<< "LAA: Added an overflow assumption\n");
LLVM_DEBUG(dbgs() << "LAA: Pointer may wrap in the address space:\n"
<< "LAA: Pointer: " << *Ptr << "\n"
<< "LAA: SCEV: " << *AR << "\n"
<< "LAA: Added an overflow assumption\n");
} else {
DEBUG(dbgs() << "LAA: Bad stride - Pointer may wrap in the address space "
<< *Ptr << " SCEV: " << *AR << "\n");
LLVM_DEBUG(
dbgs() << "LAA: Bad stride - Pointer may wrap in the address space "
<< *Ptr << " SCEV: " << *AR << "\n");
return 0;
}
}
@ -1046,8 +1049,8 @@ int64_t llvm::getPtrStride(PredicatedScalarEvolution &PSE, Value *Ptr,
// Calculate the pointer stride and check if it is constant.
const SCEVConstant *C = dyn_cast<SCEVConstant>(Step);
if (!C) {
DEBUG(dbgs() << "LAA: Bad stride - Not a constant strided " << *Ptr <<
" SCEV: " << *AR << "\n");
LLVM_DEBUG(dbgs() << "LAA: Bad stride - Not a constant strided " << *Ptr
<< " SCEV: " << *AR << "\n");
return 0;
}
@ -1074,11 +1077,11 @@ int64_t llvm::getPtrStride(PredicatedScalarEvolution &PSE, Value *Ptr,
Stride != 1 && Stride != -1) {
if (Assume) {
// We can avoid this case by adding a run-time check.
DEBUG(dbgs() << "LAA: Non unit strided pointer which is not either "
<< "inbouds or in address space 0 may wrap:\n"
<< "LAA: Pointer: " << *Ptr << "\n"
<< "LAA: SCEV: " << *AR << "\n"
<< "LAA: Added an overflow assumption\n");
LLVM_DEBUG(dbgs() << "LAA: Non unit strided pointer which is not either "
<< "inbouds or in address space 0 may wrap:\n"
<< "LAA: Pointer: " << *Ptr << "\n"
<< "LAA: SCEV: " << *AR << "\n"
<< "LAA: Added an overflow assumption\n");
PSE.setNoOverflow(Ptr, SCEVWrapPredicate::IncrementNUSW);
} else
return 0;
@ -1293,8 +1296,9 @@ bool MemoryDepChecker::couldPreventStoreLoadForward(uint64_t Distance,
}
if (MaxVFWithoutSLForwardIssues < 2 * TypeByteSize) {
DEBUG(dbgs() << "LAA: Distance " << Distance
<< " that could cause a store-load forwarding conflict\n");
LLVM_DEBUG(
dbgs() << "LAA: Distance " << Distance
<< " that could cause a store-load forwarding conflict\n");
return true;
}
@ -1446,16 +1450,16 @@ MemoryDepChecker::isDependent(const MemAccessInfo &A, unsigned AIdx,
const SCEV *Dist = PSE.getSE()->getMinusSCEV(Sink, Src);
DEBUG(dbgs() << "LAA: Src Scev: " << *Src << "Sink Scev: " << *Sink
<< "(Induction step: " << StrideAPtr << ")\n");
DEBUG(dbgs() << "LAA: Distance for " << *InstMap[AIdx] << " to "
<< *InstMap[BIdx] << ": " << *Dist << "\n");
LLVM_DEBUG(dbgs() << "LAA: Src Scev: " << *Src << "Sink Scev: " << *Sink
<< "(Induction step: " << StrideAPtr << ")\n");
LLVM_DEBUG(dbgs() << "LAA: Distance for " << *InstMap[AIdx] << " to "
<< *InstMap[BIdx] << ": " << *Dist << "\n");
// Need accesses with constant stride. We don't want to vectorize
// "A[B[i]] += ..." and similar code or pointer arithmetic that could wrap in
// the address space.
if (!StrideAPtr || !StrideBPtr || StrideAPtr != StrideBPtr){
DEBUG(dbgs() << "Pointer access with non-constant stride\n");
LLVM_DEBUG(dbgs() << "Pointer access with non-constant stride\n");
return Dependence::Unknown;
}
@ -1472,7 +1476,7 @@ MemoryDepChecker::isDependent(const MemAccessInfo &A, unsigned AIdx,
TypeByteSize))
return Dependence::NoDep;
DEBUG(dbgs() << "LAA: Dependence because of non-constant distance\n");
LLVM_DEBUG(dbgs() << "LAA: Dependence because of non-constant distance\n");
ShouldRetryWithRuntimeCheck = true;
return Dependence::Unknown;
}
@ -1483,7 +1487,7 @@ MemoryDepChecker::isDependent(const MemAccessInfo &A, unsigned AIdx,
// Attempt to prove strided accesses independent.
if (std::abs(Distance) > 0 && Stride > 1 && ATy == BTy &&
areStridedAccessesIndependent(std::abs(Distance), Stride, TypeByteSize)) {
DEBUG(dbgs() << "LAA: Strided accesses are independent\n");
LLVM_DEBUG(dbgs() << "LAA: Strided accesses are independent\n");
return Dependence::NoDep;
}
@ -1493,11 +1497,11 @@ MemoryDepChecker::isDependent(const MemAccessInfo &A, unsigned AIdx,
if (IsTrueDataDependence && EnableForwardingConflictDetection &&
(couldPreventStoreLoadForward(Val.abs().getZExtValue(), TypeByteSize) ||
ATy != BTy)) {
DEBUG(dbgs() << "LAA: Forward but may prevent st->ld forwarding\n");
LLVM_DEBUG(dbgs() << "LAA: Forward but may prevent st->ld forwarding\n");
return Dependence::ForwardButPreventsForwarding;
}
DEBUG(dbgs() << "LAA: Dependence is negative\n");
LLVM_DEBUG(dbgs() << "LAA: Dependence is negative\n");
return Dependence::Forward;
}
@ -1506,15 +1510,17 @@ MemoryDepChecker::isDependent(const MemAccessInfo &A, unsigned AIdx,
if (Val == 0) {
if (ATy == BTy)
return Dependence::Forward;
DEBUG(dbgs() << "LAA: Zero dependence difference but different types\n");
LLVM_DEBUG(
dbgs() << "LAA: Zero dependence difference but different types\n");
return Dependence::Unknown;
}
assert(Val.isStrictlyPositive() && "Expect a positive value");
if (ATy != BTy) {
DEBUG(dbgs() <<
"LAA: ReadWrite-Write positive dependency with different types\n");
LLVM_DEBUG(
dbgs()
<< "LAA: ReadWrite-Write positive dependency with different types\n");
return Dependence::Unknown;
}
@ -1555,15 +1561,15 @@ MemoryDepChecker::isDependent(const MemAccessInfo &A, unsigned AIdx,
uint64_t MinDistanceNeeded =
TypeByteSize * Stride * (MinNumIter - 1) + TypeByteSize;
if (MinDistanceNeeded > static_cast<uint64_t>(Distance)) {
DEBUG(dbgs() << "LAA: Failure because of positive distance " << Distance
<< '\n');
LLVM_DEBUG(dbgs() << "LAA: Failure because of positive distance "
<< Distance << '\n');
return Dependence::Backward;
}
// Unsafe if the minimum distance needed is greater than max safe distance.
if (MinDistanceNeeded > MaxSafeDepDistBytes) {
DEBUG(dbgs() << "LAA: Failure because it needs at least "
<< MinDistanceNeeded << " size in bytes");
LLVM_DEBUG(dbgs() << "LAA: Failure because it needs at least "
<< MinDistanceNeeded << " size in bytes");
return Dependence::Backward;
}
@ -1592,8 +1598,8 @@ MemoryDepChecker::isDependent(const MemAccessInfo &A, unsigned AIdx,
return Dependence::BackwardVectorizableButPreventsForwarding;
uint64_t MaxVF = MaxSafeDepDistBytes / (TypeByteSize * Stride);
DEBUG(dbgs() << "LAA: Positive distance " << Val.getSExtValue()
<< " with max VF = " << MaxVF << '\n');
LLVM_DEBUG(dbgs() << "LAA: Positive distance " << Val.getSExtValue()
<< " with max VF = " << MaxVF << '\n');
uint64_t MaxVFInBits = MaxVF * TypeByteSize * 8;
MaxSafeRegisterWidth = std::min(MaxSafeRegisterWidth, MaxVFInBits);
return Dependence::BackwardVectorizable;
@ -1651,7 +1657,8 @@ bool MemoryDepChecker::areDepsSafe(DepCandidates &AccessSets,
if (Dependences.size() >= MaxDependences) {
RecordDependences = false;
Dependences.clear();
DEBUG(dbgs() << "Too many dependences, stopped recording\n");
LLVM_DEBUG(dbgs()
<< "Too many dependences, stopped recording\n");
}
}
if (!RecordDependences && !SafeForVectorization)
@ -1663,7 +1670,7 @@ bool MemoryDepChecker::areDepsSafe(DepCandidates &AccessSets,
}
}
DEBUG(dbgs() << "Total Dependences: " << Dependences.size() << "\n");
LLVM_DEBUG(dbgs() << "Total Dependences: " << Dependences.size() << "\n");
return SafeForVectorization;
}
@ -1693,20 +1700,21 @@ void MemoryDepChecker::Dependence::print(
bool LoopAccessInfo::canAnalyzeLoop() {
// We need to have a loop header.
DEBUG(dbgs() << "LAA: Found a loop in "
<< TheLoop->getHeader()->getParent()->getName() << ": "
<< TheLoop->getHeader()->getName() << '\n');
LLVM_DEBUG(dbgs() << "LAA: Found a loop in "
<< TheLoop->getHeader()->getParent()->getName() << ": "
<< TheLoop->getHeader()->getName() << '\n');
// We can only analyze innermost loops.
if (!TheLoop->empty()) {
DEBUG(dbgs() << "LAA: loop is not the innermost loop\n");
LLVM_DEBUG(dbgs() << "LAA: loop is not the innermost loop\n");
recordAnalysis("NotInnerMostLoop") << "loop is not the innermost loop";
return false;
}
// We must have a single backedge.
if (TheLoop->getNumBackEdges() != 1) {
DEBUG(dbgs() << "LAA: loop control flow is not understood by analyzer\n");
LLVM_DEBUG(
dbgs() << "LAA: loop control flow is not understood by analyzer\n");
recordAnalysis("CFGNotUnderstood")
<< "loop control flow is not understood by analyzer";
return false;
@ -1714,7 +1722,8 @@ bool LoopAccessInfo::canAnalyzeLoop() {
// We must have a single exiting block.
if (!TheLoop->getExitingBlock()) {
DEBUG(dbgs() << "LAA: loop control flow is not understood by analyzer\n");
LLVM_DEBUG(
dbgs() << "LAA: loop control flow is not understood by analyzer\n");
recordAnalysis("CFGNotUnderstood")
<< "loop control flow is not understood by analyzer";
return false;
@ -1724,7 +1733,8 @@ bool LoopAccessInfo::canAnalyzeLoop() {
// checked at the end of each iteration. With that we can assume that all
// instructions in the loop are executed the same number of times.
if (TheLoop->getExitingBlock() != TheLoop->getLoopLatch()) {
DEBUG(dbgs() << "LAA: loop control flow is not understood by analyzer\n");
LLVM_DEBUG(
dbgs() << "LAA: loop control flow is not understood by analyzer\n");
recordAnalysis("CFGNotUnderstood")
<< "loop control flow is not understood by analyzer";
return false;
@ -1735,7 +1745,7 @@ bool LoopAccessInfo::canAnalyzeLoop() {
if (ExitCount == PSE->getSE()->getCouldNotCompute()) {
recordAnalysis("CantComputeNumberOfIterations")
<< "could not determine number of loop iterations";
DEBUG(dbgs() << "LAA: SCEV could not compute the loop exit count.\n");
LLVM_DEBUG(dbgs() << "LAA: SCEV could not compute the loop exit count.\n");
return false;
}
@ -1785,7 +1795,7 @@ void LoopAccessInfo::analyzeLoop(AliasAnalysis *AA, LoopInfo *LI,
if (!Ld || (!Ld->isSimple() && !IsAnnotatedParallel)) {
recordAnalysis("NonSimpleLoad", Ld)
<< "read with atomic ordering or volatile read";
DEBUG(dbgs() << "LAA: Found a non-simple load.\n");
LLVM_DEBUG(dbgs() << "LAA: Found a non-simple load.\n");
CanVecMem = false;
return;
}
@ -1809,7 +1819,7 @@ void LoopAccessInfo::analyzeLoop(AliasAnalysis *AA, LoopInfo *LI,
if (!St->isSimple() && !IsAnnotatedParallel) {
recordAnalysis("NonSimpleStore", St)
<< "write with atomic ordering or volatile write";
DEBUG(dbgs() << "LAA: Found a non-simple store.\n");
LLVM_DEBUG(dbgs() << "LAA: Found a non-simple store.\n");
CanVecMem = false;
return;
}
@ -1828,7 +1838,7 @@ void LoopAccessInfo::analyzeLoop(AliasAnalysis *AA, LoopInfo *LI,
// Check if we see any stores. If there are no stores, then we don't
// care if the pointers are *restrict*.
if (!Stores.size()) {
DEBUG(dbgs() << "LAA: Found a read-only loop!\n");
LLVM_DEBUG(dbgs() << "LAA: Found a read-only loop!\n");
CanVecMem = true;
return;
}
@ -1865,9 +1875,9 @@ void LoopAccessInfo::analyzeLoop(AliasAnalysis *AA, LoopInfo *LI,
}
if (IsAnnotatedParallel) {
DEBUG(dbgs()
<< "LAA: A loop annotated parallel, ignore memory dependency "
<< "checks.\n");
LLVM_DEBUG(
dbgs() << "LAA: A loop annotated parallel, ignore memory dependency "
<< "checks.\n");
CanVecMem = true;
return;
}
@ -1902,7 +1912,7 @@ void LoopAccessInfo::analyzeLoop(AliasAnalysis *AA, LoopInfo *LI,
// If we write (or read-write) to a single destination and there are no
// other reads in this loop then is it safe to vectorize.
if (NumReadWrites == 1 && NumReads == 0) {
DEBUG(dbgs() << "LAA: Found a write-only loop!\n");
LLVM_DEBUG(dbgs() << "LAA: Found a write-only loop!\n");
CanVecMem = true;
return;
}
@ -1917,23 +1927,24 @@ void LoopAccessInfo::analyzeLoop(AliasAnalysis *AA, LoopInfo *LI,
TheLoop, SymbolicStrides);
if (!CanDoRTIfNeeded) {
recordAnalysis("CantIdentifyArrayBounds") << "cannot identify array bounds";
DEBUG(dbgs() << "LAA: We can't vectorize because we can't find "
<< "the array bounds.\n");
LLVM_DEBUG(dbgs() << "LAA: We can't vectorize because we can't find "
<< "the array bounds.\n");
CanVecMem = false;
return;
}
DEBUG(dbgs() << "LAA: We can perform a memory runtime check if needed.\n");
LLVM_DEBUG(
dbgs() << "LAA: We can perform a memory runtime check if needed.\n");
CanVecMem = true;
if (Accesses.isDependencyCheckNeeded()) {
DEBUG(dbgs() << "LAA: Checking memory dependencies\n");
LLVM_DEBUG(dbgs() << "LAA: Checking memory dependencies\n");
CanVecMem = DepChecker->areDepsSafe(
DependentAccesses, Accesses.getDependenciesToCheck(), SymbolicStrides);
MaxSafeDepDistBytes = DepChecker->getMaxSafeDepDistBytes();
if (!CanVecMem && DepChecker->shouldRetryWithRuntimeCheck()) {
DEBUG(dbgs() << "LAA: Retrying with memory checks\n");
LLVM_DEBUG(dbgs() << "LAA: Retrying with memory checks\n");
// Clear the dependency checks. We assume they are not needed.
Accesses.resetDepChecks(*DepChecker);
@ -1949,7 +1960,7 @@ void LoopAccessInfo::analyzeLoop(AliasAnalysis *AA, LoopInfo *LI,
if (!CanDoRTIfNeeded) {
recordAnalysis("CantCheckMemDepsAtRunTime")
<< "cannot check memory dependencies at runtime";
DEBUG(dbgs() << "LAA: Can't vectorize with memory checks\n");
LLVM_DEBUG(dbgs() << "LAA: Can't vectorize with memory checks\n");
CanVecMem = false;
return;
}
@ -1959,16 +1970,17 @@ void LoopAccessInfo::analyzeLoop(AliasAnalysis *AA, LoopInfo *LI,
}
if (CanVecMem)
DEBUG(dbgs() << "LAA: No unsafe dependent memory operations in loop. We"
<< (PtrRtChecking->Need ? "" : " don't")
<< " need runtime memory checks.\n");
LLVM_DEBUG(
dbgs() << "LAA: No unsafe dependent memory operations in loop. We"
<< (PtrRtChecking->Need ? "" : " don't")
<< " need runtime memory checks.\n");
else {
recordAnalysis("UnsafeMemDep")
<< "unsafe dependent memory operations in loop. Use "
"#pragma loop distribute(enable) to allow loop distribution "
"to attempt to isolate the offending operations into a separate "
"loop";
DEBUG(dbgs() << "LAA: unsafe dependent memory operations in loop\n");
LLVM_DEBUG(dbgs() << "LAA: unsafe dependent memory operations in loop\n");
}
}
@ -2052,8 +2064,8 @@ expandBounds(const RuntimePointerChecking::CheckingPtrGroup *CG, Loop *TheLoop,
Type *PtrArithTy = Type::getInt8PtrTy(Ctx, AS);
if (SE->isLoopInvariant(Sc, TheLoop)) {
DEBUG(dbgs() << "LAA: Adding RT check for a loop invariant ptr:" << *Ptr
<< "\n");
LLVM_DEBUG(dbgs() << "LAA: Adding RT check for a loop invariant ptr:"
<< *Ptr << "\n");
// Ptr could be in the loop body. If so, expand a new one at the correct
// location.
Instruction *Inst = dyn_cast<Instruction>(Ptr);
@ -2066,10 +2078,11 @@ expandBounds(const RuntimePointerChecking::CheckingPtrGroup *CG, Loop *TheLoop,
return {NewPtr, NewPtrPlusOne};
} else {
Value *Start = nullptr, *End = nullptr;
DEBUG(dbgs() << "LAA: Adding RT check for range:\n");
LLVM_DEBUG(dbgs() << "LAA: Adding RT check for range:\n");
Start = Exp.expandCodeFor(CG->Low, PtrArithTy, Loc);
End = Exp.expandCodeFor(CG->High, PtrArithTy, Loc);
DEBUG(dbgs() << "Start: " << *CG->Low << " End: " << *CG->High << "\n");
LLVM_DEBUG(dbgs() << "Start: " << *CG->Low << " End: " << *CG->High
<< "\n");
return {Start, End};
}
}
@ -2187,9 +2200,9 @@ void LoopAccessInfo::collectStridedAccess(Value *MemAccess) {
if (!Stride)
return;
DEBUG(dbgs() << "LAA: Found a strided access that is a candidate for "
"versioning:");
DEBUG(dbgs() << " Ptr: " << *Ptr << " Stride: " << *Stride << "\n");
LLVM_DEBUG(dbgs() << "LAA: Found a strided access that is a candidate for "
"versioning:");
LLVM_DEBUG(dbgs() << " Ptr: " << *Ptr << " Stride: " << *Stride << "\n");
// Avoid adding the "Stride == 1" predicate when we know that
// Stride >= Trip-Count. Such a predicate will effectively optimize a single
@ -2225,12 +2238,13 @@ void LoopAccessInfo::collectStridedAccess(Value *MemAccess) {
// "Stride >= TripCount" is equivalent to checking:
// Stride - BETakenCount > 0
if (SE->isKnownPositive(StrideMinusBETaken)) {
DEBUG(dbgs() << "LAA: Stride>=TripCount; No point in versioning as the "
"Stride==1 predicate will imply that the loop executes "
"at most once.\n");
LLVM_DEBUG(
dbgs() << "LAA: Stride>=TripCount; No point in versioning as the "
"Stride==1 predicate will imply that the loop executes "
"at most once.\n");
return;
}
DEBUG(dbgs() << "LAA: Found a strided access that we can version.");
}
LLVM_DEBUG(dbgs() << "LAA: Found a strided access that we can version.");
SymbolicStrides[Ptr] = Stride;
StrideSet.insert(Stride);

4
llvm/lib/Analysis/LoopPass.cpp
View File

@ -362,8 +362,8 @@ bool LoopPass::skipLoop(const Loop *L) const {
// Check for the OptimizeNone attribute.
if (F->hasFnAttribute(Attribute::OptimizeNone)) {
// FIXME: Report this to dbgs() only once per function.
DEBUG(dbgs() << "Skipping pass '" << getPassName()
<< "' in function " << F->getName() << "\n");
LLVM_DEBUG(dbgs() << "Skipping pass '" << getPassName() << "' in function "
<< F->getName() << "\n");
// FIXME: Delete loop from pass manager's queue?
return true;
}

15
llvm/lib/Analysis/MemoryBuiltins.cpp
View File

@ -528,8 +528,8 @@ SizeOffsetType ObjectSizeOffsetVisitor::compute(Value *V) {
return visitGEPOperator(cast<GEPOperator>(*CE));
}
DEBUG(dbgs() << "ObjectSizeOffsetVisitor::compute() unhandled value: " << *V
<< '\n');
LLVM_DEBUG(dbgs() << "ObjectSizeOffsetVisitor::compute() unhandled value: "
<< *V << '\n');
return unknown();
}
@ -729,7 +729,8 @@ SizeOffsetType ObjectSizeOffsetVisitor::visitUndefValue(UndefValue&) {
}
SizeOffsetType ObjectSizeOffsetVisitor::visitInstruction(Instruction &I) {
DEBUG(dbgs() << "ObjectSizeOffsetVisitor unknown instruction:" << I << '\n');
LLVM_DEBUG(dbgs() << "ObjectSizeOffsetVisitor unknown instruction:" << I
<< '\n');
return unknown();
}
@ -808,8 +809,9 @@ SizeOffsetEvalType ObjectSizeOffsetEvaluator::compute_(Value *V) {
// Ignore values where we cannot do more than ObjectSizeVisitor.
Result = unknown();
} else {
DEBUG(dbgs() << "ObjectSizeOffsetEvaluator::compute() unhandled value: "
<< *V << '\n');
LLVM_DEBUG(
dbgs() << "ObjectSizeOffsetEvaluator::compute() unhandled value: " << *V
<< '\n');
Result = unknown();
}
@ -946,6 +948,7 @@ SizeOffsetEvalType ObjectSizeOffsetEvaluator::visitSelectInst(SelectInst &I) {
}
SizeOffsetEvalType ObjectSizeOffsetEvaluator::visitInstruction(Instruction &I) {
DEBUG(dbgs() << "ObjectSizeOffsetEvaluator unknown instruction:" << I <<'\n');
LLVM_DEBUG(dbgs() << "ObjectSizeOffsetEvaluator unknown instruction:" << I
<< '\n');
return unknown();
}

12
llvm/lib/Analysis/MemoryDependenceAnalysis.cpp
View File

@ -824,7 +824,7 @@ MemoryDependenceResults::getNonLocalCallDependency(CallSite QueryCS) {
SmallPtrSet<BasicBlock *, 32> Visited;
unsigned NumSortedEntries = Cache.size();
DEBUG(AssertSorted(Cache));
LLVM_DEBUG(AssertSorted(Cache));
// Iterate while we still have blocks to update.
while (!DirtyBlocks.empty()) {
@ -837,7 +837,7 @@ MemoryDependenceResults::getNonLocalCallDependency(CallSite QueryCS) {
// Do a binary search to see if we already have an entry for this block in
// the cache set. If so, find it.
DEBUG(AssertSorted(Cache, NumSortedEntries));
LLVM_DEBUG(AssertSorted(Cache, NumSortedEntries));
NonLocalDepInfo::iterator Entry =
std::upper_bound(Cache.begin(), Cache.begin() + NumSortedEntries,
NonLocalDepEntry(DirtyBB));
@ -1210,7 +1210,7 @@ bool MemoryDependenceResults::getNonLocalPointerDepFromBB(
unsigned NumSortedEntries = Cache->size();
unsigned WorklistEntries = BlockNumberLimit;
bool GotWorklistLimit = false;
DEBUG(AssertSorted(*Cache));
LLVM_DEBUG(AssertSorted(*Cache));
while (!Worklist.empty()) {
BasicBlock *BB = Worklist.pop_back_val();
@ -1241,7 +1241,7 @@ bool MemoryDependenceResults::getNonLocalPointerDepFromBB(
// Get the dependency info for Pointer in BB. If we have cached
// information, we will use it, otherwise we compute it.
DEBUG(AssertSorted(*Cache, NumSortedEntries));
LLVM_DEBUG(AssertSorted(*Cache, NumSortedEntries));
MemDepResult Dep = GetNonLocalInfoForBlock(QueryInst, Loc, isLoad, BB,
Cache, NumSortedEntries);
@ -1455,7 +1455,7 @@ bool MemoryDependenceResults::getNonLocalPointerDepFromBB(
// Okay, we're done now. If we added new values to the cache, re-sort it.
SortNonLocalDepInfoCache(*Cache, NumSortedEntries);
DEBUG(AssertSorted(*Cache));
LLVM_DEBUG(AssertSorted(*Cache));
return true;
}
@ -1651,7 +1651,7 @@ void MemoryDependenceResults::removeInstruction(Instruction *RemInst) {
}
assert(!NonLocalDeps.count(RemInst) && "RemInst got reinserted?");
DEBUG(verifyRemoved(RemInst));
LLVM_DEBUG(verifyRemoved(RemInst));
}
/// Verify that the specified instruction does not occur in our internal data

25
llvm/lib/Analysis/MemorySSA.cpp
View File

@ -1240,10 +1240,11 @@ void MemorySSA::OptimizeUses::optimizeUsesInBlock(
unsigned long UpperBound = VersionStack.size() - 1;
if (UpperBound - LocInfo.LowerBound > MaxCheckLimit) {
DEBUG(dbgs() << "MemorySSA skipping optimization of " << *MU << " ("
<< *(MU->getMemoryInst()) << ")"
<< " because there are " << UpperBound - LocInfo.LowerBound
<< " stores to disambiguate\n");
LLVM_DEBUG(dbgs() << "MemorySSA skipping optimization of " << *MU << " ("
<< *(MU->getMemoryInst()) << ")"
<< " because there are "
<< UpperBound - LocInfo.LowerBound
<< " stores to disambiguate\n");
// Because we did not walk, LastKill is no longer valid, as this may
// have been a kill.
LocInfo.LastKillValid = false;
@ -2036,10 +2037,10 @@ MemoryAccess *MemorySSA::CachingWalker::getClobberingMemoryAccess(
: StartingUseOrDef;
MemoryAccess *Clobber = getClobberingMemoryAccess(DefiningAccess, Q);
DEBUG(dbgs() << "Starting Memory SSA clobber for " << *I << " is ");
DEBUG(dbgs() << *StartingUseOrDef << "\n");
DEBUG(dbgs() << "Final Memory SSA clobber for " << *I << " is ");
DEBUG(dbgs() << *Clobber << "\n");
LLVM_DEBUG(dbgs() << "Starting Memory SSA clobber for " << *I << " is ");
LLVM_DEBUG(dbgs() << *StartingUseOrDef << "\n");
LLVM_DEBUG(dbgs() << "Final Memory SSA clobber for " << *I << " is ");
LLVM_DEBUG(dbgs() << *Clobber << "\n");
return Clobber;
}
@ -2083,10 +2084,10 @@ MemorySSA::CachingWalker::getClobberingMemoryAccess(MemoryAccess *MA) {
}
MemoryAccess *Result = getClobberingMemoryAccess(DefiningAccess, Q);
DEBUG(dbgs() << "Starting Memory SSA clobber for " << *I << " is ");
DEBUG(dbgs() << *DefiningAccess << "\n");
DEBUG(dbgs() << "Final Memory SSA clobber for " << *I << " is ");
DEBUG(dbgs() << *Result << "\n");
LLVM_DEBUG(dbgs() << "Starting Memory SSA clobber for " << *I << " is ");
LLVM_DEBUG(dbgs() << *DefiningAccess << "\n");
LLVM_DEBUG(dbgs() << "Final Memory SSA clobber for " << *I << " is ");
LLVM_DEBUG(dbgs() << *Result << "\n");
StartingAccess->setOptimized(Result);
if (MSSA->isLiveOnEntryDef(Result))

13
llvm/lib/Analysis/RegionPass.cpp
View File

@ -158,12 +158,9 @@ bool RGPassManager::runOnFunction(Function &F) {
}
// Print the region tree after all pass.
DEBUG(
dbgs() << "\nRegion tree of function " << F.getName()
<< " after all region Pass:\n";
RI->dump();
dbgs() << "\n";
);
LLVM_DEBUG(dbgs() << "\nRegion tree of function " << F.getName()
<< " after all region Pass:\n";
RI->dump(); dbgs() << "\n";);
return Changed;
}
@ -289,8 +286,8 @@ bool RegionPass::skipRegion(Region &R) const {
if (F.hasFnAttribute(Attribute::OptimizeNone)) {
// Report this only once per function.
if (R.getEntry() == &F.getEntryBlock())
DEBUG(dbgs() << "Skipping pass '" << getPassName()
<< "' on function " << F.getName() << "\n");
LLVM_DEBUG(dbgs() << "Skipping pass '" << getPassName()
<< "' on function " << F.getName() << "\n");
return true;
}
return false;

100
llvm/lib/Analysis/ScalarEvolution.cpp
View File

@ -4723,7 +4723,7 @@ ScalarEvolution::createAddRecFromPHIWithCastsImpl(const SCEVUnknown *SymbolicPHI
const SCEV *StartExtended = getExtendedExpr(StartVal, Signed);
if (PredIsKnownFalse(StartVal, StartExtended)) {
DEBUG(dbgs() << "P2 is compile-time false\n";);
LLVM_DEBUG(dbgs() << "P2 is compile-time false\n";);
return None;
}
@ -4731,7 +4731,7 @@ ScalarEvolution::createAddRecFromPHIWithCastsImpl(const SCEVUnknown *SymbolicPHI
// NSSW or NUSW)
const SCEV *AccumExtended = getExtendedExpr(Accum, /*CreateSignExtend=*/true);
if (PredIsKnownFalse(Accum, AccumExtended)) {
DEBUG(dbgs() << "P3 is compile-time false\n";);
LLVM_DEBUG(dbgs() << "P3 is compile-time false\n";);
return None;
}
@ -4740,7 +4740,7 @@ ScalarEvolution::createAddRecFromPHIWithCastsImpl(const SCEVUnknown *SymbolicPHI
if (Expr != ExtendedExpr &&
!isKnownPredicate(ICmpInst::ICMP_EQ, Expr, ExtendedExpr)) {
const SCEVPredicate *Pred = getEqualPredicate(Expr, ExtendedExpr);
DEBUG (dbgs() << "Added Predicate: " << *Pred);
LLVM_DEBUG(dbgs() << "Added Predicate: " << *Pred);
Predicates.push_back(Pred);
}
};
@ -10633,22 +10633,22 @@ void ScalarEvolution::collectParametricTerms(const SCEV *Expr,
SCEVCollectStrides StrideCollector(*this, Strides);
visitAll(Expr, StrideCollector);
DEBUG({
dbgs() << "Strides:\n";
for (const SCEV *S : Strides)
dbgs() << *S << "\n";
});
LLVM_DEBUG({
dbgs() << "Strides:\n";
for (const SCEV *S : Strides)
dbgs() << *S << "\n";
});
for (const SCEV *S : Strides) {
SCEVCollectTerms TermCollector(Terms);
visitAll(S, TermCollector);
}
DEBUG({
dbgs() << "Terms:\n";
for (const SCEV *T : Terms)
dbgs() << *T << "\n";
});
LLVM_DEBUG({
dbgs() << "Terms:\n";
for (const SCEV *T : Terms)
dbgs() << *T << "\n";
});
SCEVCollectAddRecMultiplies MulCollector(Terms, *this);
visitAll(Expr, MulCollector);
@ -10759,11 +10759,11 @@ void ScalarEvolution::findArrayDimensions(SmallVectorImpl<const SCEV *> &Terms,
if (!containsParameters(Terms))
return;
DEBUG({
dbgs() << "Terms:\n";
for (const SCEV *T : Terms)
dbgs() << *T << "\n";
});
LLVM_DEBUG({
dbgs() << "Terms:\n";
for (const SCEV *T : Terms)
dbgs() << *T << "\n";
});
// Remove duplicates.
array_pod_sort(Terms.begin(), Terms.end());
@ -10790,11 +10790,11 @@ void ScalarEvolution::findArrayDimensions(SmallVectorImpl<const SCEV *> &Terms,
if (const SCEV *NewT = removeConstantFactors(*this, T))
NewTerms.push_back(NewT);
DEBUG({
dbgs() << "Terms after sorting:\n";
for (const SCEV *T : NewTerms)
dbgs() << *T << "\n";
});
LLVM_DEBUG({
dbgs() << "Terms after sorting:\n";
for (const SCEV *T : NewTerms)
dbgs() << *T << "\n";
});
if (NewTerms.empty() || !findArrayDimensionsRec(*this, NewTerms, Sizes)) {
Sizes.clear();
@ -10804,11 +10804,11 @@ void ScalarEvolution::findArrayDimensions(SmallVectorImpl<const SCEV *> &Terms,
// The last element to be pushed into Sizes is the size of an element.
Sizes.push_back(ElementSize);
DEBUG({
dbgs() << "Sizes:\n";
for (const SCEV *S : Sizes)
dbgs() << *S << "\n";
});
LLVM_DEBUG({
dbgs() << "Sizes:\n";
for (const SCEV *S : Sizes)
dbgs() << *S << "\n";
});
}
void ScalarEvolution::computeAccessFunctions(
@ -10828,13 +10828,13 @@ void ScalarEvolution::computeAccessFunctions(
const SCEV *Q, *R;
SCEVDivision::divide(*this, Res, Sizes[i], &Q, &R);
DEBUG({
dbgs() << "Res: " << *Res << "\n";
dbgs() << "Sizes[i]: " << *Sizes[i] << "\n";
dbgs() << "Res divided by Sizes[i]:\n";
dbgs() << "Quotient: " << *Q << "\n";
dbgs() << "Remainder: " << *R << "\n";
});
LLVM_DEBUG({
dbgs() << "Res: " << *Res << "\n";
dbgs() << "Sizes[i]: " << *Sizes[i] << "\n";
dbgs() << "Res divided by Sizes[i]:\n";
dbgs() << "Quotient: " << *Q << "\n";
dbgs() << "Remainder: " << *R << "\n";
});
Res = Q;
@ -10862,11 +10862,11 @@ void ScalarEvolution::computeAccessFunctions(
std::reverse(Subscripts.begin(), Subscripts.end());
DEBUG({
dbgs() << "Subscripts:\n";
for (const SCEV *S : Subscripts)
dbgs() << *S << "\n";
});
LLVM_DEBUG({
dbgs() << "Subscripts:\n";
for (const SCEV *S : Subscripts)
dbgs() << *S << "\n";
});
}
/// Splits the SCEV into two vectors of SCEVs representing the subscripts and
@ -10940,17 +10940,17 @@ void ScalarEvolution::delinearize(const SCEV *Expr,
if (Subscripts.empty())
return;
DEBUG({
dbgs() << "succeeded to delinearize " << *Expr << "\n";
dbgs() << "ArrayDecl[UnknownSize]";
for (const SCEV *S : Sizes)
dbgs() << "[" << *S << "]";
LLVM_DEBUG({
dbgs() << "succeeded to delinearize " << *Expr << "\n";
dbgs() << "ArrayDecl[UnknownSize]";
for (const SCEV *S : Sizes)
dbgs() << "[" << *S << "]";
dbgs() << "\nArrayRef";
for (const SCEV *S : Subscripts)
dbgs() << "[" << *S << "]";
dbgs() << "\n";
});
dbgs() << "\nArrayRef";
for (const SCEV *S : Subscripts)
dbgs() << "[" << *S << "]";
dbgs() << "\n";
});
}
//===----------------------------------------------------------------------===//

152
llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp
View File

@ -139,10 +139,11 @@ AggressiveAntiDepBreaker::AggressiveAntiDepBreaker(
CriticalPathSet |= CPSet;
}
DEBUG(dbgs() << "AntiDep Critical-Path Registers:");
DEBUG(for (unsigned r : CriticalPathSet.set_bits())
dbgs() << " " << printReg(r, TRI));
DEBUG(dbgs() << '\n');
LLVM_DEBUG(dbgs() << "AntiDep Critical-Path Registers:");
LLVM_DEBUG(for (unsigned r
: CriticalPathSet.set_bits()) dbgs()
<< " " << printReg(r, TRI));
LLVM_DEBUG(dbgs() << '\n');
}
AggressiveAntiDepBreaker::~AggressiveAntiDepBreaker() {
@ -202,9 +203,9 @@ void AggressiveAntiDepBreaker::Observe(MachineInstr &MI, unsigned Count,
PrescanInstruction(MI, Count, PassthruRegs);
ScanInstruction(MI, Count);
DEBUG(dbgs() << "Observe: ");
DEBUG(MI.dump());
DEBUG(dbgs() << "\tRegs:");
LLVM_DEBUG(dbgs() << "Observe: ");
LLVM_DEBUG(MI.dump());
LLVM_DEBUG(dbgs() << "\tRegs:");
std::vector<unsigned> &DefIndices = State->GetDefIndices();
for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) {
@ -215,16 +216,16 @@ void AggressiveAntiDepBreaker::Observe(MachineInstr &MI, unsigned Count,
// conservative location (i.e. the beginning of the previous
// schedule region).
if (State->IsLive(Reg)) {
DEBUG(if (State->GetGroup(Reg) != 0)
dbgs() << " " << printReg(Reg, TRI) << "=g" <<
State->GetGroup(Reg) << "->g0(region live-out)");
LLVM_DEBUG(if (State->GetGroup(Reg) != 0) dbgs()
<< " " << printReg(Reg, TRI) << "=g" << State->GetGroup(Reg)
<< "->g0(region live-out)");
State->UnionGroups(Reg, 0);
} else if ((DefIndices[Reg] < InsertPosIndex)
&& (DefIndices[Reg] >= Count)) {
DefIndices[Reg] = Count;
}
}
DEBUG(dbgs() << '\n');
LLVM_DEBUG(dbgs() << '\n');
}
bool AggressiveAntiDepBreaker::IsImplicitDefUse(MachineInstr &MI,
@ -313,7 +314,7 @@ void AggressiveAntiDepBreaker::HandleLastUse(unsigned Reg, unsigned KillIdx,
// subregister definitions).
for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
if (TRI->isSuperRegister(Reg, *AI) && State->IsLive(*AI)) {
DEBUG(if (!header && footer) dbgs() << footer);
LLVM_DEBUG(if (!header && footer) dbgs() << footer);
return;
}
@ -322,9 +323,11 @@ void AggressiveAntiDepBreaker::HandleLastUse(unsigned Reg, unsigned KillIdx,
DefIndices[Reg] = ~0u;
RegRefs.erase(Reg);
State->LeaveGroup(Reg);
DEBUG(if (header) {
dbgs() << header << printReg(Reg, TRI); header = nullptr; });
DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << tag);
LLVM_DEBUG(if (header) {
dbgs() << header << printReg(Reg, TRI);
header = nullptr;
});
LLVM_DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << tag);
// Repeat for subregisters. Note that we only do this if the superregister
// was not live because otherwise, regardless whether we have an explicit
// use of the subregister, the subregister's contents are needed for the
@ -336,15 +339,17 @@ void AggressiveAntiDepBreaker::HandleLastUse(unsigned Reg, unsigned KillIdx,
DefIndices[SubregReg] = ~0u;
RegRefs.erase(SubregReg);
State->LeaveGroup(SubregReg);
DEBUG(if (header) {
dbgs() << header << printReg(Reg, TRI); header = nullptr; });
DEBUG(dbgs() << " " << printReg(SubregReg, TRI) << "->g" <<
State->GetGroup(SubregReg) << tag);
LLVM_DEBUG(if (header) {
dbgs() << header << printReg(Reg, TRI);
header = nullptr;
});
LLVM_DEBUG(dbgs() << " " << printReg(SubregReg, TRI) << "->g"
<< State->GetGroup(SubregReg) << tag);
}
}
}
DEBUG(if (!header && footer) dbgs() << footer);
LLVM_DEBUG(if (!header && footer) dbgs() << footer);
}
void AggressiveAntiDepBreaker::PrescanInstruction(
@ -367,14 +372,15 @@ void AggressiveAntiDepBreaker::PrescanInstruction(
HandleLastUse(Reg, Count + 1, "", "\tDead Def: ", "\n");
}
DEBUG(dbgs() << "\tDef Groups:");
LLVM_DEBUG(dbgs() << "\tDef Groups:");
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI.getOperand(i);
if (!MO.isReg() || !MO.isDef()) continue;
unsigned Reg = MO.getReg();
if (Reg == 0) continue;
DEBUG(dbgs() << " " << printReg(Reg, TRI) << "=g" << State->GetGroup(Reg));
LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI) << "=g"
<< State->GetGroup(Reg));
// If MI's defs have a special allocation requirement, don't allow
// any def registers to be changed. Also assume all registers
@ -383,7 +389,7 @@ void AggressiveAntiDepBreaker::PrescanInstruction(
// can tell user specified registers from compiler-specified.
if (MI.isCall() || MI.hasExtraDefRegAllocReq() || TII->isPredicated(MI) ||
MI.isInlineAsm()) {
DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)");
LLVM_DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)");
State->UnionGroups(Reg, 0);
}
@ -393,8 +399,8 @@ void AggressiveAntiDepBreaker::PrescanInstruction(
unsigned AliasReg = *AI;
if (State->IsLive(AliasReg)) {
State->UnionGroups(Reg, AliasReg);
DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << "(via "
<< printReg(AliasReg, TRI) << ")");
LLVM_DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << "(via "
<< printReg(AliasReg, TRI) << ")");
}
}
@ -406,7 +412,7 @@ void AggressiveAntiDepBreaker::PrescanInstruction(
RegRefs.insert(std::make_pair(Reg, RR));
}
DEBUG(dbgs() << '\n');
LLVM_DEBUG(dbgs() << '\n');
// Scan the register defs for this instruction and update
// live-ranges.
@ -437,7 +443,7 @@ void AggressiveAntiDepBreaker::PrescanInstruction(
void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr &MI,
unsigned Count) {
DEBUG(dbgs() << "\tUse Groups:");
LLVM_DEBUG(dbgs() << "\tUse Groups:");
std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
RegRefs = State->GetRegRefs();
@ -469,7 +475,8 @@ void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr &MI,
unsigned Reg = MO.getReg();
if (Reg == 0) continue;
DEBUG(dbgs() << " " << printReg(Reg, TRI) << "=g" << State->GetGroup(Reg));
LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI) << "=g"
<< State->GetGroup(Reg));
// It wasn't previously live but now it is, this is a kill. Forget
// the previous live-range information and start a new live-range
@ -477,7 +484,7 @@ void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr &MI,
HandleLastUse(Reg, Count, "(last-use)");
if (Special) {
DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)");
LLVM_DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)");
State->UnionGroups(Reg, 0);
}
@ -489,12 +496,12 @@ void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr &MI,
RegRefs.insert(std::make_pair(Reg, RR));
}
DEBUG(dbgs() << '\n');
LLVM_DEBUG(dbgs() << '\n');
// Form a group of all defs and uses of a KILL instruction to ensure
// that all registers are renamed as a group.
if (MI.isKill()) {
DEBUG(dbgs() << "\tKill Group:");
LLVM_DEBUG(dbgs() << "\tKill Group:");
unsigned FirstReg = 0;
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
@ -504,15 +511,15 @@ void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr &MI,
if (Reg == 0) continue;
if (FirstReg != 0) {
DEBUG(dbgs() << "=" << printReg(Reg, TRI));
LLVM_DEBUG(dbgs() << "=" << printReg(Reg, TRI));
State->UnionGroups(FirstReg, Reg);
} else {
DEBUG(dbgs() << " " << printReg(Reg, TRI));
LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI));
FirstReg = Reg;
}
}
DEBUG(dbgs() << "->g" << State->GetGroup(FirstReg) << '\n');
LLVM_DEBUG(dbgs() << "->g" << State->GetGroup(FirstReg) << '\n');
}
}
@ -535,7 +542,7 @@ BitVector AggressiveAntiDepBreaker::GetRenameRegisters(unsigned Reg) {
BV &= RCBV;
}
DEBUG(dbgs() << " " << TRI->getRegClassName(RC));
LLVM_DEBUG(dbgs() << " " << TRI->getRegClassName(RC));
}
return BV;
@ -562,8 +569,8 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
// Find the "superest" register in the group. At the same time,
// collect the BitVector of registers that can be used to rename
// each register.
DEBUG(dbgs() << "\tRename Candidates for Group g" << AntiDepGroupIndex
<< ":\n");
LLVM_DEBUG(dbgs() << "\tRename Candidates for Group g" << AntiDepGroupIndex
<< ":\n");
std::map<unsigned, BitVector> RenameRegisterMap;
unsigned SuperReg = 0;
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
@ -573,13 +580,13 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
// If Reg has any references, then collect possible rename regs
if (RegRefs.count(Reg) > 0) {
DEBUG(dbgs() << "\t\t" << printReg(Reg, TRI) << ":");
LLVM_DEBUG(dbgs() << "\t\t" << printReg(Reg, TRI) << ":");
BitVector &BV = RenameRegisterMap[Reg];
assert(BV.empty());
BV = GetRenameRegisters(Reg);
DEBUG({
LLVM_DEBUG({
dbgs() << " ::";
for (unsigned r : BV.set_bits())
dbgs() << " " << printReg(r, TRI);
@ -625,11 +632,11 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC);
if (Order.empty()) {
DEBUG(dbgs() << "\tEmpty Super Regclass!!\n");
LLVM_DEBUG(dbgs() << "\tEmpty Super Regclass!!\n");
return false;
}
DEBUG(dbgs() << "\tFind Registers:");
LLVM_DEBUG(dbgs() << "\tFind Registers:");
RenameOrder.insert(RenameOrderType::value_type(SuperRC, Order.size()));
@ -645,7 +652,7 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
// Don't replace a register with itself.
if (NewSuperReg == SuperReg) continue;
DEBUG(dbgs() << " [" << printReg(NewSuperReg, TRI) << ':');
LLVM_DEBUG(dbgs() << " [" << printReg(NewSuperReg, TRI) << ':');
RenameMap.clear();
// For each referenced group register (which must be a SuperReg or
@ -662,11 +669,11 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
NewReg = TRI->getSubReg(NewSuperReg, NewSubRegIdx);
}
DEBUG(dbgs() << " " << printReg(NewReg, TRI));
LLVM_DEBUG(dbgs() << " " << printReg(NewReg, TRI));
// Check if Reg can be renamed to NewReg.
if (!RenameRegisterMap[Reg].test(NewReg)) {
DEBUG(dbgs() << "(no rename)");
LLVM_DEBUG(dbgs() << "(no rename)");
goto next_super_reg;
}
@ -675,7 +682,7 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
// must also check all aliases of NewReg, because we can't define a
// register when any sub or super is already live.
if (State->IsLive(NewReg) || (KillIndices[Reg] > DefIndices[NewReg])) {
DEBUG(dbgs() << "(live)");
LLVM_DEBUG(dbgs() << "(live)");
goto next_super_reg;
} else {
bool found = false;
@ -683,7 +690,8 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
unsigned AliasReg = *AI;
if (State->IsLive(AliasReg) ||
(KillIndices[Reg] > DefIndices[AliasReg])) {
DEBUG(dbgs() << "(alias " << printReg(AliasReg, TRI) << " live)");
LLVM_DEBUG(dbgs()
<< "(alias " << printReg(AliasReg, TRI) << " live)");
found = true;
break;
}
@ -701,7 +709,7 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
continue;
if (UseMI->getOperand(Idx).isEarlyClobber()) {
DEBUG(dbgs() << "(ec)");
LLVM_DEBUG(dbgs() << "(ec)");
goto next_super_reg;
}
}
@ -715,7 +723,7 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
MachineInstr *DefMI = Q.second.Operand->getParent();
if (DefMI->readsRegister(NewReg, TRI)) {
DEBUG(dbgs() << "(ec)");
LLVM_DEBUG(dbgs() << "(ec)");
goto next_super_reg;
}
}
@ -728,14 +736,14 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
// renamed, as recorded in RenameMap.
RenameOrder.erase(SuperRC);
RenameOrder.insert(RenameOrderType::value_type(SuperRC, R));
DEBUG(dbgs() << "]\n");
LLVM_DEBUG(dbgs() << "]\n");
return true;
next_super_reg:
DEBUG(dbgs() << ']');
LLVM_DEBUG(dbgs() << ']');
} while (R != EndR);
DEBUG(dbgs() << '\n');
LLVM_DEBUG(dbgs() << '\n');
// No registers are free and available!
return false;
@ -788,13 +796,13 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
}
#ifndef NDEBUG
DEBUG(dbgs() << "\n===== Aggressive anti-dependency breaking\n");
DEBUG(dbgs() << "Available regs:");
LLVM_DEBUG(dbgs() << "\n===== Aggressive anti-dependency breaking\n");
LLVM_DEBUG(dbgs() << "Available regs:");
for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) {
if (!State->IsLive(Reg))
DEBUG(dbgs() << " " << printReg(Reg, TRI));
LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI));
}
DEBUG(dbgs() << '\n');
LLVM_DEBUG(dbgs() << '\n');
#endif
BitVector RegAliases(TRI->getNumRegs());
@ -811,8 +819,8 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
if (MI.isDebugInstr())
continue;
DEBUG(dbgs() << "Anti: ");
DEBUG(MI.dump());
LLVM_DEBUG(dbgs() << "Anti: ");
LLVM_DEBUG(MI.dump());
std::set<unsigned> PassthruRegs;
GetPassthruRegs(MI, PassthruRegs);
@ -848,30 +856,30 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
(Edge->getKind() != SDep::Output)) continue;
unsigned AntiDepReg = Edge->getReg();
DEBUG(dbgs() << "\tAntidep reg: " << printReg(AntiDepReg, TRI));
LLVM_DEBUG(dbgs() << "\tAntidep reg: " << printReg(AntiDepReg, TRI));
assert(AntiDepReg != 0 && "Anti-dependence on reg0?");
if (!MRI.isAllocatable(AntiDepReg)) {
// Don't break anti-dependencies on non-allocatable registers.
DEBUG(dbgs() << " (non-allocatable)\n");
LLVM_DEBUG(dbgs() << " (non-allocatable)\n");
continue;
} else if (ExcludeRegs && ExcludeRegs->test(AntiDepReg)) {
// Don't break anti-dependencies for critical path registers
// if not on the critical path
DEBUG(dbgs() << " (not critical-path)\n");
LLVM_DEBUG(dbgs() << " (not critical-path)\n");
continue;
} else if (PassthruRegs.count(AntiDepReg) != 0) {
// If the anti-dep register liveness "passes-thru", then
// don't try to change it. It will be changed along with
// the use if required to break an earlier antidep.
DEBUG(dbgs() << " (passthru)\n");
LLVM_DEBUG(dbgs() << " (passthru)\n");
continue;
} else {
// No anti-dep breaking for implicit deps
MachineOperand *AntiDepOp = MI.findRegisterDefOperand(AntiDepReg);
assert(AntiDepOp && "Can't find index for defined register operand");
if (!AntiDepOp || AntiDepOp->isImplicit()) {
DEBUG(dbgs() << " (implicit)\n");
LLVM_DEBUG(dbgs() << " (implicit)\n");
continue;
}
@ -897,13 +905,13 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
PE = PathSU->Preds.end(); P != PE; ++P) {
if ((P->getSUnit() == NextSU) && (P->getKind() != SDep::Anti) &&
(P->getKind() != SDep::Output)) {
DEBUG(dbgs() << " (real dependency)\n");
LLVM_DEBUG(dbgs() << " (real dependency)\n");
AntiDepReg = 0;
break;
} else if ((P->getSUnit() != NextSU) &&
(P->getKind() == SDep::Data) &&
(P->getReg() == AntiDepReg)) {
DEBUG(dbgs() << " (other dependency)\n");
LLVM_DEBUG(dbgs() << " (other dependency)\n");
AntiDepReg = 0;
break;
}
@ -941,17 +949,17 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
// Determine AntiDepReg's register group.
const unsigned GroupIndex = State->GetGroup(AntiDepReg);
if (GroupIndex == 0) {
DEBUG(dbgs() << " (zero group)\n");
LLVM_DEBUG(dbgs() << " (zero group)\n");
continue;
}
DEBUG(dbgs() << '\n');
LLVM_DEBUG(dbgs() << '\n');
// Look for a suitable register to use to break the anti-dependence.
std::map<unsigned, unsigned> RenameMap;
if (FindSuitableFreeRegisters(GroupIndex, RenameOrder, RenameMap)) {
DEBUG(dbgs() << "\tBreaking anti-dependence edge on "
<< printReg(AntiDepReg, TRI) << ":");
LLVM_DEBUG(dbgs() << "\tBreaking anti-dependence edge on "
<< printReg(AntiDepReg, TRI) << ":");
// Handle each group register...
for (std::map<unsigned, unsigned>::iterator
@ -959,9 +967,9 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
unsigned CurrReg = S->first;
unsigned NewReg = S->second;
DEBUG(dbgs() << " " << printReg(CurrReg, TRI) << "->"
<< printReg(NewReg, TRI) << "("
<< RegRefs.count(CurrReg) << " refs)");
LLVM_DEBUG(dbgs() << " " << printReg(CurrReg, TRI) << "->"
<< printReg(NewReg, TRI) << "("
<< RegRefs.count(CurrReg) << " refs)");
// Update the references to the old register CurrReg to
// refer to the new register NewReg.
@ -994,7 +1002,7 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
}
++Broken;
DEBUG(dbgs() << '\n');
LLVM_DEBUG(dbgs() << '\n');
}
}
}

2
llvm/lib/CodeGen/AllocationOrder.cpp
View File

@ -39,7 +39,7 @@ AllocationOrder::AllocationOrder(unsigned VirtReg,
HardHints = true;
rewind();
DEBUG({
LLVM_DEBUG({
if (!Hints.empty()) {
dbgs() << "hints:";
for (unsigned I = 0, E = Hints.size(); I != E; ++I)

5
llvm/lib/CodeGen/AsmPrinter/DIE.cpp
View File

@ -87,8 +87,9 @@ void DIEAbbrev::Emit(const AsmPrinter *AP) const {
// easily, which helps track down where it came from.
if (!dwarf::isValidFormForVersion(AttrData.getForm(),
AP->getDwarfVersion())) {
DEBUG(dbgs() << "Invalid form " << format("0x%x", AttrData.getForm())
<< " for DWARF version " << AP->getDwarfVersion() << "\n");
LLVM_DEBUG(dbgs() << "Invalid form " << format("0x%x", AttrData.getForm())
<< " for DWARF version " << AP->getDwarfVersion()
<< "\n");
llvm_unreachable("Invalid form for specified DWARF version");
}
#endif

16
llvm/lib/CodeGen/AsmPrinter/DIEHash.cpp
View File

@ -43,7 +43,7 @@ static StringRef getDIEStringAttr(const DIE &Die, uint16_t Attr) {
/// Adds the string in \p Str to the hash. This also hashes
/// a trailing NULL with the string.
void DIEHash::addString(StringRef Str) {
DEBUG(dbgs() << "Adding string " << Str << " to hash.\n");
LLVM_DEBUG(dbgs() << "Adding string " << Str << " to hash.\n");
Hash.update(Str);
Hash.update(makeArrayRef((uint8_t)'\0'));
}
@ -53,7 +53,7 @@ void DIEHash::addString(StringRef Str) {
/// Adds the unsigned in \p Value to the hash encoded as a ULEB128.
void DIEHash::addULEB128(uint64_t Value) {
DEBUG(dbgs() << "Adding ULEB128 " << Value << " to hash.\n");
LLVM_DEBUG(dbgs() << "Adding ULEB128 " << Value << " to hash.\n");
do {
uint8_t Byte = Value & 0x7f;
Value >>= 7;
@ -64,7 +64,7 @@ void DIEHash::addULEB128(uint64_t Value) {
}
void DIEHash::addSLEB128(int64_t Value) {
DEBUG(dbgs() << "Adding ULEB128 " << Value << " to hash.\n");
LLVM_DEBUG(dbgs() << "Adding ULEB128 " << Value << " to hash.\n");
bool More;
do {
uint8_t Byte = Value & 0x7f;
@ -80,7 +80,7 @@ void DIEHash::addSLEB128(int64_t Value) {
/// Including \p Parent adds the context of Parent to the hash..
void DIEHash::addParentContext(const DIE &Parent) {
DEBUG(dbgs() << "Adding parent context to hash...\n");
LLVM_DEBUG(dbgs() << "Adding parent context to hash...\n");
// [7.27.2] For each surrounding type or namespace beginning with the
// outermost such construct...
@ -108,7 +108,7 @@ void DIEHash::addParentContext(const DIE &Parent) {
// ... Then the name, taken from the DW_AT_name attribute.
StringRef Name = getDIEStringAttr(Die, dwarf::DW_AT_name);
DEBUG(dbgs() << "... adding context: " << Name << "\n");
LLVM_DEBUG(dbgs() << "... adding context: " << Name << "\n");
if (!Name.empty())
addString(Name);
}
@ -118,9 +118,9 @@ void DIEHash::addParentContext(const DIE &Parent) {
void DIEHash::collectAttributes(const DIE &Die, DIEAttrs &Attrs) {
for (const auto &V : Die.values()) {
DEBUG(dbgs() << "Attribute: "
<< dwarf::AttributeString(V.getAttribute())
<< " added.\n");
LLVM_DEBUG(dbgs() << "Attribute: "
<< dwarf::AttributeString(V.getAttribute())
<< " added.\n");
switch (V.getAttribute()) {
#define HANDLE_DIE_HASH_ATTR(NAME) \
case dwarf::NAME: \

4
llvm/lib/CodeGen/AsmPrinter/DbgValueHistoryCalculator.cpp
View File

@ -50,8 +50,8 @@ void DbgValueHistoryMap::startInstrRange(InlinedVariable Var,
auto &Ranges = VarInstrRanges[Var];
if (!Ranges.empty() && Ranges.back().second == nullptr &&
Ranges.back().first->isIdenticalTo(MI)) {
DEBUG(dbgs() << "Coalescing identical DBG_VALUE entries:\n"
<< "\t" << Ranges.back().first << "\t" << MI << "\n");
LLVM_DEBUG(dbgs() << "Coalescing identical DBG_VALUE entries:\n"
<< "\t" << Ranges.back().first << "\t" << MI << "\n");
return;
}
Ranges.push_back(std::make_pair(&MI, nullptr));

4
llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
View File

@ -1034,7 +1034,7 @@ DwarfDebug::buildLocationList(SmallVectorImpl<DebugLocEntry> &DebugLoc,
EndLabel = getLabelBeforeInsn(std::next(I)->first);
assert(EndLabel && "Forgot label after instruction ending a range!");
DEBUG(dbgs() << "DotDebugLoc: " << *Begin << "\n");
LLVM_DEBUG(dbgs() << "DotDebugLoc: " << *Begin << "\n");
auto Value = getDebugLocValue(Begin);
DebugLocEntry Loc(StartLabel, EndLabel, Value);
@ -1063,7 +1063,7 @@ DwarfDebug::buildLocationList(SmallVectorImpl<DebugLocEntry> &DebugLoc,
// Attempt to coalesce the ranges of two otherwise identical
// DebugLocEntries.
auto CurEntry = DebugLoc.rbegin();
DEBUG({
LLVM_DEBUG({
dbgs() << CurEntry->getValues().size() << " Values:\n";
for (auto &Value : CurEntry->getValues())
Value.dump();

8
llvm/lib/CodeGen/AtomicExpandPass.cpp
View File

@ -379,8 +379,8 @@ LoadInst *AtomicExpand::convertAtomicLoadToIntegerType(LoadInst *LI) {
NewLI->setAlignment(LI->getAlignment());
NewLI->setVolatile(LI->isVolatile());
NewLI->setAtomic(LI->getOrdering(), LI->getSyncScopeID());
DEBUG(dbgs() << "Replaced " << *LI << " with " << *NewLI << "\n");
LLVM_DEBUG(dbgs() << "Replaced " << *LI << " with " << *NewLI << "\n");
Value *NewVal = Builder.CreateBitCast(NewLI, LI->getType());
LI->replaceAllUsesWith(NewVal);
LI->eraseFromParent();
@ -462,7 +462,7 @@ StoreInst *AtomicExpand::convertAtomicStoreToIntegerType(StoreInst *SI) {
NewSI->setAlignment(SI->getAlignment());
NewSI->setVolatile(SI->isVolatile());
NewSI->setAtomic(SI->getOrdering(), SI->getSyncScopeID());
DEBUG(dbgs() << "Replaced " << *SI << " with " << *NewSI << "\n");
LLVM_DEBUG(dbgs() << "Replaced " << *SI << " with " << *NewSI << "\n");
SI->eraseFromParent();
return NewSI;
}
@ -943,7 +943,7 @@ AtomicCmpXchgInst *AtomicExpand::convertCmpXchgToIntegerType(AtomicCmpXchgInst *
CI->getSyncScopeID());
NewCI->setVolatile(CI->isVolatile());
NewCI->setWeak(CI->isWeak());
DEBUG(dbgs() << "Replaced " << *CI << " with " << *NewCI << "\n");
LLVM_DEBUG(dbgs() << "Replaced " << *CI << " with " << *NewCI << "\n");
Value *OldVal = Builder.CreateExtractValue(NewCI, 0);
Value *Succ = Builder.CreateExtractValue(NewCI, 1);

63
llvm/lib/CodeGen/BranchFolding.cpp
View File

@ -152,7 +152,7 @@ BranchFolder::BranchFolder(bool defaultEnableTailMerge, bool CommonHoist,
void BranchFolder::RemoveDeadBlock(MachineBasicBlock *MBB) {
assert(MBB->pred_empty() && "MBB must be dead!");
DEBUG(dbgs() << "\nRemoving MBB: " << *MBB);
LLVM_DEBUG(dbgs() << "\nRemoving MBB: " << *MBB);
MachineFunction *MF = MBB->getParent();
// drop all successors.
@ -650,9 +650,9 @@ ProfitableToMerge(MachineBasicBlock *MBB1, MachineBasicBlock *MBB2,
CommonTailLen = ComputeCommonTailLength(MBB1, MBB2, I1, I2);
if (CommonTailLen == 0)
return false;
DEBUG(dbgs() << "Common tail length of " << printMBBReference(*MBB1)
<< " and " << printMBBReference(*MBB2) << " is " << CommonTailLen
<< '\n');
LLVM_DEBUG(dbgs() << "Common tail length of " << printMBBReference(*MBB1)
<< " and " << printMBBReference(*MBB2) << " is "
<< CommonTailLen << '\n');
// It's almost always profitable to merge any number of non-terminator
// instructions with the block that falls through into the common successor.
@ -807,8 +807,8 @@ bool BranchFolder::CreateCommonTailOnlyBlock(MachineBasicBlock *&PredBB,
SameTails[commonTailIndex].getTailStartPos();
MachineBasicBlock *MBB = SameTails[commonTailIndex].getBlock();
DEBUG(dbgs() << "\nSplitting " << printMBBReference(*MBB) << ", size "
<< maxCommonTailLength);
LLVM_DEBUG(dbgs() << "\nSplitting " << printMBBReference(*MBB) << ", size "
<< maxCommonTailLength);
// If the split block unconditionally falls-thru to SuccBB, it will be
// merged. In control flow terms it should then take SuccBB's name. e.g. If
@ -817,7 +817,7 @@ bool BranchFolder::CreateCommonTailOnlyBlock(MachineBasicBlock *&PredBB,
SuccBB->getBasicBlock() : MBB->getBasicBlock();
MachineBasicBlock *newMBB = SplitMBBAt(*MBB, BBI, BB);
if (!newMBB) {
DEBUG(dbgs() << "... failed!");
LLVM_DEBUG(dbgs() << "... failed!");
return false;
}
@ -956,18 +956,19 @@ bool BranchFolder::TryTailMergeBlocks(MachineBasicBlock *SuccBB,
unsigned MinCommonTailLength) {
bool MadeChange = false;
DEBUG(dbgs() << "\nTryTailMergeBlocks: ";
for (unsigned i = 0, e = MergePotentials.size(); i != e; ++i) dbgs()
<< printMBBReference(*MergePotentials[i].getBlock())
<< (i == e - 1 ? "" : ", ");
dbgs() << "\n"; if (SuccBB) {
dbgs() << " with successor " << printMBBReference(*SuccBB) << '\n';
if (PredBB)
dbgs() << " which has fall-through from "
<< printMBBReference(*PredBB) << "\n";
} dbgs() << "Looking for common tails of at least "
<< MinCommonTailLength << " instruction"
<< (MinCommonTailLength == 1 ? "" : "s") << '\n';);
LLVM_DEBUG(
dbgs() << "\nTryTailMergeBlocks: ";
for (unsigned i = 0, e = MergePotentials.size(); i != e; ++i) dbgs()
<< printMBBReference(*MergePotentials[i].getBlock())
<< (i == e - 1 ? "" : ", ");
dbgs() << "\n"; if (SuccBB) {
dbgs() << " with successor " << printMBBReference(*SuccBB) << '\n';
if (PredBB)
dbgs() << " which has fall-through from "
<< printMBBReference(*PredBB) << "\n";
} dbgs() << "Looking for common tails of at least "
<< MinCommonTailLength << " instruction"
<< (MinCommonTailLength == 1 ? "" : "s") << '\n';);
// Sort by hash value so that blocks with identical end sequences sort
// together.
@ -1047,19 +1048,19 @@ bool BranchFolder::TryTailMergeBlocks(MachineBasicBlock *SuccBB,
// MBB is common tail. Adjust all other BB's to jump to this one.
// Traversal must be forwards so erases work.
DEBUG(dbgs() << "\nUsing common tail in " << printMBBReference(*MBB)
<< " for ");
LLVM_DEBUG(dbgs() << "\nUsing common tail in " << printMBBReference(*MBB)
<< " for ");
for (unsigned int i=0, e = SameTails.size(); i != e; ++i) {
if (commonTailIndex == i)
continue;
DEBUG(dbgs() << printMBBReference(*SameTails[i].getBlock())
<< (i == e - 1 ? "" : ", "));
LLVM_DEBUG(dbgs() << printMBBReference(*SameTails[i].getBlock())
<< (i == e - 1 ? "" : ", "));
// Hack the end off BB i, making it jump to BB commonTailIndex instead.
replaceTailWithBranchTo(SameTails[i].getTailStartPos(), *MBB);
// BB i is no longer a predecessor of SuccBB; remove it from the worklist.
MergePotentials.erase(SameTails[i].getMPIter());
}
DEBUG(dbgs() << "\n");
LLVM_DEBUG(dbgs() << "\n");
// We leave commonTailIndex in the worklist in case there are other blocks
// that match it with a smaller number of instructions.
MadeChange = true;
@ -1363,7 +1364,8 @@ static void copyDebugInfoToPredecessor(const TargetInstrInfo *TII,
for (MachineInstr &MI : MBB.instrs())
if (MI.isDebugValue()) {
TII->duplicate(PredMBB, InsertBefore, MI);
DEBUG(dbgs() << "Copied debug value from empty block to pred: " << MI);
LLVM_DEBUG(dbgs() << "Copied debug value from empty block to pred: "
<< MI);
}
}
@ -1374,7 +1376,8 @@ static void copyDebugInfoToSuccessor(const TargetInstrInfo *TII,
for (MachineInstr &MI : MBB.instrs())
if (MI.isDebugValue()) {
TII->duplicate(SuccMBB, InsertBefore, MI);
DEBUG(dbgs() << "Copied debug value from empty block to succ: " << MI);
LLVM_DEBUG(dbgs() << "Copied debug value from empty block to succ: "
<< MI);
}
}
@ -1489,8 +1492,8 @@ ReoptimizeBlock:
if (PriorCond.empty() && !PriorTBB && MBB->pred_size() == 1 &&
PrevBB.succ_size() == 1 &&
!MBB->hasAddressTaken() && !MBB->isEHPad()) {
DEBUG(dbgs() << "\nMerging into block: " << PrevBB
<< "From MBB: " << *MBB);
LLVM_DEBUG(dbgs() << "\nMerging into block: " << PrevBB
<< "From MBB: " << *MBB);
// Remove redundant DBG_VALUEs first.
if (PrevBB.begin() != PrevBB.end()) {
MachineBasicBlock::iterator PrevBBIter = PrevBB.end();
@ -1576,8 +1579,8 @@ ReoptimizeBlock:
// Reverse the branch so we will fall through on the previous true cond.
SmallVector<MachineOperand, 4> NewPriorCond(PriorCond);
if (!TII->reverseBranchCondition(NewPriorCond)) {
DEBUG(dbgs() << "\nMoving MBB: " << *MBB
<< "To make fallthrough to: " << *PriorTBB << "\n");
LLVM_DEBUG(dbgs() << "\nMoving MBB: " << *MBB
<< "To make fallthrough to: " << *PriorTBB << "\n");
DebugLoc dl = getBranchDebugLoc(PrevBB);
TII->removeBranch(PrevBB);

41
llvm/lib/CodeGen/BranchRelaxation.cpp
View File

@ -288,10 +288,11 @@ bool BranchRelaxation::isBlockInRange(
if (TII->isBranchOffsetInRange(MI.getOpcode(), DestOffset - BrOffset))
return true;
DEBUG(dbgs() << "Out of range branch to destination "
<< printMBBReference(DestBB) << " from "
<< printMBBReference(*MI.getParent()) << " to " << DestOffset
<< " offset " << DestOffset - BrOffset << '\t' << MI);
LLVM_DEBUG(dbgs() << "Out of range branch to destination "
<< printMBBReference(DestBB) << " from "
<< printMBBReference(*MI.getParent()) << " to "
<< DestOffset << " offset " << DestOffset - BrOffset << '\t'
<< MI);
return false;
}
@ -360,8 +361,9 @@ bool BranchRelaxation::fixupConditionalBranch(MachineInstr &MI) {
// =>
// bne L2
// b L1
DEBUG(dbgs() << " Invert condition and swap "
"its destination with " << MBB->back());
LLVM_DEBUG(dbgs() << " Invert condition and swap "
"its destination with "
<< MBB->back());
removeBranch(MBB);
insertBranch(MBB, FBB, TBB, Cond);
@ -384,9 +386,9 @@ bool BranchRelaxation::fixupConditionalBranch(MachineInstr &MI) {
// just created), so we can use the inverted the condition.
MachineBasicBlock &NextBB = *std::next(MachineFunction::iterator(MBB));
DEBUG(dbgs() << " Insert B to " << printMBBReference(*TBB)
<< ", invert condition and change dest. to "
<< printMBBReference(NextBB) << '\n');
LLVM_DEBUG(dbgs() << " Insert B to " << printMBBReference(*TBB)
<< ", invert condition and change dest. to "
<< printMBBReference(NextBB) << '\n');
removeBranch(MBB);
// Insert a new conditional branch and a new unconditional branch.
@ -397,8 +399,8 @@ bool BranchRelaxation::fixupConditionalBranch(MachineInstr &MI) {
}
// Branch cond can't be inverted.
// In this case we always add a block after the MBB.
DEBUG(dbgs() << " The branch condition can't be inverted. "
<< " Insert a new BB after " << MBB->back());
LLVM_DEBUG(dbgs() << " The branch condition can't be inverted. "
<< " Insert a new BB after " << MBB->back());
if (!FBB)
FBB = &(*std::next(MachineFunction::iterator(MBB)));
@ -417,11 +419,12 @@ bool BranchRelaxation::fixupConditionalBranch(MachineInstr &MI) {
NewBB = createNewBlockAfter(*MBB);
insertUncondBranch(NewBB, TBB);
DEBUG(dbgs() << " Insert cond B to the new BB " << printMBBReference(*NewBB)
<< " Keep the exiting condition.\n"
<< " Insert B to " << printMBBReference(*FBB) << ".\n"
<< " In the new BB: Insert B to "
<< printMBBReference(*TBB) << ".\n");
LLVM_DEBUG(dbgs() << " Insert cond B to the new BB "
<< printMBBReference(*NewBB)
<< " Keep the exiting condition.\n"
<< " Insert B to " << printMBBReference(*FBB) << ".\n"
<< " In the new BB: Insert B to "
<< printMBBReference(*TBB) << ".\n");
// Update the successor lists according to the transformation to follow.
MBB->replaceSuccessor(TBB, NewBB);
@ -541,7 +544,7 @@ bool BranchRelaxation::relaxBranchInstructions() {
bool BranchRelaxation::runOnMachineFunction(MachineFunction &mf) {
MF = &mf;
DEBUG(dbgs() << "***** BranchRelaxation *****\n");
LLVM_DEBUG(dbgs() << "***** BranchRelaxation *****\n");
const TargetSubtargetInfo &ST = MF->getSubtarget();
TII = ST.getInstrInfo();
@ -558,7 +561,7 @@ bool BranchRelaxation::runOnMachineFunction(MachineFunction &mf) {
// sizes of each block.
scanFunction();
DEBUG(dbgs() << " Basic blocks before relaxation\n"; dumpBBs(););
LLVM_DEBUG(dbgs() << " Basic blocks before relaxation\n"; dumpBBs(););
bool MadeChange = false;
while (relaxBranchInstructions())
@ -567,7 +570,7 @@ bool BranchRelaxation::runOnMachineFunction(MachineFunction &mf) {
// After a while, this might be made debug-only, but it is not expensive.
verify();
DEBUG(dbgs() << " Basic blocks after relaxation\n\n"; dumpBBs());
LLVM_DEBUG(dbgs() << " Basic blocks after relaxation\n\n"; dumpBBs());
BlockInfo.clear();

8
llvm/lib/CodeGen/BreakFalseDeps.cpp
View File

@ -165,13 +165,13 @@ bool BreakFalseDeps::shouldBreakDependence(MachineInstr *MI, unsigned OpIdx,
unsigned Pref) {
unsigned reg = MI->getOperand(OpIdx).getReg();
unsigned Clearance = RDA->getClearance(MI, reg);
DEBUG(dbgs() << "Clearance: " << Clearance << ", want " << Pref);
LLVM_DEBUG(dbgs() << "Clearance: " << Clearance << ", want " << Pref);
if (Pref > Clearance) {
DEBUG(dbgs() << ": Break dependency.\n");
LLVM_DEBUG(dbgs() << ": Break dependency.\n");
return true;
}
DEBUG(dbgs() << ": OK .\n");
LLVM_DEBUG(dbgs() << ": OK .\n");
return false;
}
@ -260,7 +260,7 @@ bool BreakFalseDeps::runOnMachineFunction(MachineFunction &mf) {
RegClassInfo.runOnMachineFunction(mf);
DEBUG(dbgs() << "********** BREAK FALSE DEPENDENCIES **********\n");
LLVM_DEBUG(dbgs() << "********** BREAK FALSE DEPENDENCIES **********\n");
// Traverse the basic blocks.
for (MachineBasicBlock &MBB : mf) {

4
llvm/lib/CodeGen/CalcSpillWeights.cpp
View File

@ -35,8 +35,8 @@ void llvm::calculateSpillWeightsAndHints(LiveIntervals &LIS,
const MachineLoopInfo &MLI,
const MachineBlockFrequencyInfo &MBFI,
VirtRegAuxInfo::NormalizingFn norm) {
DEBUG(dbgs() << "********** Compute Spill Weights **********\n"
<< "********** Function: " << MF.getName() << '\n');
LLVM_DEBUG(dbgs() << "********** Compute Spill Weights **********\n"
<< "********** Function: " << MF.getName() << '\n');
MachineRegisterInfo &MRI = MF.getRegInfo();
VirtRegAuxInfo VRAI(MF, LIS, VRM, MLI, MBFI, norm);

135
llvm/lib/CodeGen/CodeGenPrepare.cpp
View File

@ -528,7 +528,7 @@ bool CodeGenPrepare::eliminateFallThrough(Function &F) {
BranchInst *Term = dyn_cast<BranchInst>(SinglePred->getTerminator());
if (Term && !Term->isConditional()) {
Changed = true;
DEBUG(dbgs() << "To merge:\n"<< *SinglePred << "\n\n\n");
LLVM_DEBUG(dbgs() << "To merge:\n" << *SinglePred << "\n\n\n");
// Remember if SinglePred was the entry block of the function.
// If so, we will need to move BB back to the entry position.
bool isEntry = SinglePred == &SinglePred->getParent()->getEntryBlock();
@ -755,7 +755,8 @@ void CodeGenPrepare::eliminateMostlyEmptyBlock(BasicBlock *BB) {
BranchInst *BI = cast<BranchInst>(BB->getTerminator());
BasicBlock *DestBB = BI->getSuccessor(0);
DEBUG(dbgs() << "MERGING MOSTLY EMPTY BLOCKS - BEFORE:\n" << *BB << *DestBB);
LLVM_DEBUG(dbgs() << "MERGING MOSTLY EMPTY BLOCKS - BEFORE:\n"
<< *BB << *DestBB);
// If the destination block has a single pred, then this is a trivial edge,
// just collapse it.
@ -769,7 +770,7 @@ void CodeGenPrepare::eliminateMostlyEmptyBlock(BasicBlock *BB) {
if (isEntry && BB != &BB->getParent()->getEntryBlock())
BB->moveBefore(&BB->getParent()->getEntryBlock());
DEBUG(dbgs() << "AFTER:\n" << *DestBB << "\n\n\n");
LLVM_DEBUG(dbgs() << "AFTER:\n" << *DestBB << "\n\n\n");
return;
}
}
@ -807,7 +808,7 @@ void CodeGenPrepare::eliminateMostlyEmptyBlock(BasicBlock *BB) {
BB->eraseFromParent();
++NumBlocksElim;
DEBUG(dbgs() << "AFTER:\n" << *DestBB << "\n\n\n");
LLVM_DEBUG(dbgs() << "AFTER:\n" << *DestBB << "\n\n\n");
}
// Computes a map of base pointer relocation instructions to corresponding
@ -1272,8 +1273,8 @@ static bool sinkAndCmp0Expression(Instruction *AndI,
if (!TLI.isMaskAndCmp0FoldingBeneficial(*AndI))
return false;
DEBUG(dbgs() << "found 'and' feeding only icmp 0;\n");
DEBUG(AndI->getParent()->dump());
LLVM_DEBUG(dbgs() << "found 'and' feeding only icmp 0;\n");
LLVM_DEBUG(AndI->getParent()->dump());
// Push the 'and' into the same block as the icmp 0. There should only be
// one (icmp (and, 0)) in each block, since CSE/GVN should have removed any
@ -1286,7 +1287,7 @@ static bool sinkAndCmp0Expression(Instruction *AndI,
// Preincrement use iterator so we don't invalidate it.
++UI;
DEBUG(dbgs() << "sinking 'and' use: " << *User << "\n");
LLVM_DEBUG(dbgs() << "sinking 'and' use: " << *User << "\n");
// Keep the 'and' in the same place if the use is already in the same block.
Instruction *InsertPt =
@ -1300,7 +1301,7 @@ static bool sinkAndCmp0Expression(Instruction *AndI,
// Replace a use of the 'and' with a use of the new 'and'.
TheUse = InsertedAnd;
++NumAndUses;
DEBUG(User->getParent()->dump());
LLVM_DEBUG(User->getParent()->dump());
}
// We removed all uses, nuke the and.
@ -2130,13 +2131,14 @@ class TypePromotionTransaction {
/// Move \p Inst before \p Before.
InstructionMoveBefore(Instruction *Inst, Instruction *Before)
: TypePromotionAction(Inst), Position(Inst) {
DEBUG(dbgs() << "Do: move: " << *Inst << "\nbefore: " << *Before << "\n");
LLVM_DEBUG(dbgs() << "Do: move: " << *Inst << "\nbefore: " << *Before
<< "\n");
Inst->moveBefore(Before);
}
/// Move the instruction back to its original position.
void undo() override {
DEBUG(dbgs() << "Undo: moveBefore: " << *Inst << "\n");
LLVM_DEBUG(dbgs() << "Undo: moveBefore: " << *Inst << "\n");
Position.insert(Inst);
}
};
@ -2153,18 +2155,18 @@ class TypePromotionTransaction {
/// Set \p Idx operand of \p Inst with \p NewVal.
OperandSetter(Instruction *Inst, unsigned Idx, Value *NewVal)
: TypePromotionAction(Inst), Idx(Idx) {
DEBUG(dbgs() << "Do: setOperand: " << Idx << "\n"
<< "for:" << *Inst << "\n"
<< "with:" << *NewVal << "\n");
LLVM_DEBUG(dbgs() << "Do: setOperand: " << Idx << "\n"
<< "for:" << *Inst << "\n"
<< "with:" << *NewVal << "\n");
Origin = Inst->getOperand(Idx);
Inst->setOperand(Idx, NewVal);
}
/// Restore the original value of the instruction.
void undo() override {
DEBUG(dbgs() << "Undo: setOperand:" << Idx << "\n"
<< "for: " << *Inst << "\n"
<< "with: " << *Origin << "\n");
LLVM_DEBUG(dbgs() << "Undo: setOperand:" << Idx << "\n"
<< "for: " << *Inst << "\n"
<< "with: " << *Origin << "\n");
Inst->setOperand(Idx, Origin);
}
};
@ -2178,7 +2180,7 @@ class TypePromotionTransaction {
public:
/// Remove \p Inst from the uses of the operands of \p Inst.
OperandsHider(Instruction *Inst) : TypePromotionAction(Inst) {
DEBUG(dbgs() << "Do: OperandsHider: " << *Inst << "\n");
LLVM_DEBUG(dbgs() << "Do: OperandsHider: " << *Inst << "\n");
unsigned NumOpnds = Inst->getNumOperands();
OriginalValues.reserve(NumOpnds);
for (unsigned It = 0; It < NumOpnds; ++It) {
@ -2194,7 +2196,7 @@ class TypePromotionTransaction {
/// Restore the original list of uses.
void undo() override {
DEBUG(dbgs() << "Undo: OperandsHider: " << *Inst << "\n");
LLVM_DEBUG(dbgs() << "Undo: OperandsHider: " << *Inst << "\n");
for (unsigned It = 0, EndIt = OriginalValues.size(); It != EndIt; ++It)
Inst->setOperand(It, OriginalValues[It]);
}
@ -2211,7 +2213,7 @@ class TypePromotionTransaction {
TruncBuilder(Instruction *Opnd, Type *Ty) : TypePromotionAction(Opnd) {
IRBuilder<> Builder(Opnd);
Val = Builder.CreateTrunc(Opnd, Ty, "promoted");
DEBUG(dbgs() << "Do: TruncBuilder: " << *Val << "\n");
LLVM_DEBUG(dbgs() << "Do: TruncBuilder: " << *Val << "\n");
}
/// Get the built value.
@ -2219,7 +2221,7 @@ class TypePromotionTransaction {
/// Remove the built instruction.
void undo() override {
DEBUG(dbgs() << "Undo: TruncBuilder: " << *Val << "\n");
LLVM_DEBUG(dbgs() << "Undo: TruncBuilder: " << *Val << "\n");
if (Instruction *IVal = dyn_cast<Instruction>(Val))
IVal->eraseFromParent();
}
@ -2237,7 +2239,7 @@ class TypePromotionTransaction {
: TypePromotionAction(InsertPt) {
IRBuilder<> Builder(InsertPt);
Val = Builder.CreateSExt(Opnd, Ty, "promoted");
DEBUG(dbgs() << "Do: SExtBuilder: " << *Val << "\n");
LLVM_DEBUG(dbgs() << "Do: SExtBuilder: " << *Val << "\n");
}
/// Get the built value.
@ -2245,7 +2247,7 @@ class TypePromotionTransaction {
/// Remove the built instruction.
void undo() override {
DEBUG(dbgs() << "Undo: SExtBuilder: " << *Val << "\n");
LLVM_DEBUG(dbgs() << "Undo: SExtBuilder: " << *Val << "\n");
if (Instruction *IVal = dyn_cast<Instruction>(Val))
IVal->eraseFromParent();
}
@ -2263,7 +2265,7 @@ class TypePromotionTransaction {
: TypePromotionAction(InsertPt) {
IRBuilder<> Builder(InsertPt);
Val = Builder.CreateZExt(Opnd, Ty, "promoted");
DEBUG(dbgs() << "Do: ZExtBuilder: " << *Val << "\n");
LLVM_DEBUG(dbgs() << "Do: ZExtBuilder: " << *Val << "\n");
}
/// Get the built value.
@ -2271,7 +2273,7 @@ class TypePromotionTransaction {
/// Remove the built instruction.
void undo() override {
DEBUG(dbgs() << "Undo: ZExtBuilder: " << *Val << "\n");
LLVM_DEBUG(dbgs() << "Undo: ZExtBuilder: " << *Val << "\n");
if (Instruction *IVal = dyn_cast<Instruction>(Val))
IVal->eraseFromParent();
}
@ -2286,15 +2288,15 @@ class TypePromotionTransaction {
/// Mutate the type of \p Inst into \p NewTy.
TypeMutator(Instruction *Inst, Type *NewTy)
: TypePromotionAction(Inst), OrigTy(Inst->getType()) {
DEBUG(dbgs() << "Do: MutateType: " << *Inst << " with " << *NewTy
<< "\n");
LLVM_DEBUG(dbgs() << "Do: MutateType: " << *Inst << " with " << *NewTy
<< "\n");
Inst->mutateType(NewTy);
}
/// Mutate the instruction back to its original type.
void undo() override {
DEBUG(dbgs() << "Undo: MutateType: " << *Inst << " with " << *OrigTy
<< "\n");
LLVM_DEBUG(dbgs() << "Undo: MutateType: " << *Inst << " with " << *OrigTy
<< "\n");
Inst->mutateType(OrigTy);
}
};
@ -2321,8 +2323,8 @@ class TypePromotionTransaction {
public:
/// Replace all the use of \p Inst by \p New.
UsesReplacer(Instruction *Inst, Value *New) : TypePromotionAction(Inst) {
DEBUG(dbgs() << "Do: UsersReplacer: " << *Inst << " with " << *New
<< "\n");
LLVM_DEBUG(dbgs() << "Do: UsersReplacer: " << *Inst << " with " << *New
<< "\n");
// Record the original uses.
for (Use &U : Inst->uses()) {
Instruction *UserI = cast<Instruction>(U.getUser());
@ -2334,7 +2336,7 @@ class TypePromotionTransaction {
/// Reassign the original uses of Inst to Inst.
void undo() override {
DEBUG(dbgs() << "Undo: UsersReplacer: " << *Inst << "\n");
LLVM_DEBUG(dbgs() << "Undo: UsersReplacer: " << *Inst << "\n");
for (use_iterator UseIt = OriginalUses.begin(),
EndIt = OriginalUses.end();
UseIt != EndIt; ++UseIt) {
@ -2369,7 +2371,7 @@ class TypePromotionTransaction {
RemovedInsts(RemovedInsts) {
if (New)
Replacer = new UsesReplacer(Inst, New);
DEBUG(dbgs() << "Do: InstructionRemover: " << *Inst << "\n");
LLVM_DEBUG(dbgs() << "Do: InstructionRemover: " << *Inst << "\n");
RemovedInsts.insert(Inst);
/// The instructions removed here will be freed after completing
/// optimizeBlock() for all blocks as we need to keep track of the
@ -2382,7 +2384,7 @@ class TypePromotionTransaction {
/// Resurrect the instruction and reassign it to the proper uses if
/// new value was provided when build this action.
void undo() override {
DEBUG(dbgs() << "Undo: InstructionRemover: " << *Inst << "\n");
LLVM_DEBUG(dbgs() << "Undo: InstructionRemover: " << *Inst << "\n");
Inserter.insert(Inst);
if (Replacer)
Replacer->undo();
@ -3592,19 +3594,19 @@ Value *TypePromotionHelper::promoteOperandForOther(
// Step #3.
Instruction *ExtForOpnd = Ext;
DEBUG(dbgs() << "Propagate Ext to operands\n");
LLVM_DEBUG(dbgs() << "Propagate Ext to operands\n");
for (int OpIdx = 0, EndOpIdx = ExtOpnd->getNumOperands(); OpIdx != EndOpIdx;
++OpIdx) {
DEBUG(dbgs() << "Operand:\n" << *(ExtOpnd->getOperand(OpIdx)) << '\n');
LLVM_DEBUG(dbgs() << "Operand:\n" << *(ExtOpnd->getOperand(OpIdx)) << '\n');
if (ExtOpnd->getOperand(OpIdx)->getType() == Ext->getType() ||
!shouldExtOperand(ExtOpnd, OpIdx)) {
DEBUG(dbgs() << "No need to propagate\n");
LLVM_DEBUG(dbgs() << "No need to propagate\n");
continue;
}
// Check if we can statically extend the operand.
Value *Opnd = ExtOpnd->getOperand(OpIdx);
if (const ConstantInt *Cst = dyn_cast<ConstantInt>(Opnd)) {
DEBUG(dbgs() << "Statically extend\n");
LLVM_DEBUG(dbgs() << "Statically extend\n");
unsigned BitWidth = Ext->getType()->getIntegerBitWidth();
APInt CstVal = IsSExt ? Cst->getValue().sext(BitWidth)
: Cst->getValue().zext(BitWidth);
@ -3613,7 +3615,7 @@ Value *TypePromotionHelper::promoteOperandForOther(
}
// UndefValue are typed, so we have to statically sign extend them.
if (isa<UndefValue>(Opnd)) {
DEBUG(dbgs() << "Statically extend\n");
LLVM_DEBUG(dbgs() << "Statically extend\n");
TPT.setOperand(ExtOpnd, OpIdx, UndefValue::get(Ext->getType()));
continue;
}
@ -3622,7 +3624,7 @@ Value *TypePromotionHelper::promoteOperandForOther(
// Check if Ext was reused to extend an operand.
if (!ExtForOpnd) {
// If yes, create a new one.
DEBUG(dbgs() << "More operands to ext\n");
LLVM_DEBUG(dbgs() << "More operands to ext\n");
Value *ValForExtOpnd = IsSExt ? TPT.createSExt(Ext, Opnd, Ext->getType())
: TPT.createZExt(Ext, Opnd, Ext->getType());
if (!isa<Instruction>(ValForExtOpnd)) {
@ -3643,7 +3645,7 @@ Value *TypePromotionHelper::promoteOperandForOther(
ExtForOpnd = nullptr;
}
if (ExtForOpnd == Ext) {
DEBUG(dbgs() << "Extension is useless now\n");
LLVM_DEBUG(dbgs() << "Extension is useless now\n");
TPT.eraseInstruction(Ext);
}
return ExtOpnd;
@ -3659,7 +3661,8 @@ Value *TypePromotionHelper::promoteOperandForOther(
/// \return True if the promotion is profitable, false otherwise.
bool AddressingModeMatcher::isPromotionProfitable(
unsigned NewCost, unsigned OldCost, Value *PromotedOperand) const {
DEBUG(dbgs() << "OldCost: " << OldCost << "\tNewCost: " << NewCost << '\n');
LLVM_DEBUG(dbgs() << "OldCost: " << OldCost << "\tNewCost: " << NewCost
<< '\n');
// The cost of the new extensions is greater than the cost of the
// old extension plus what we folded.
// This is not profitable.
@ -3930,7 +3933,7 @@ bool AddressingModeMatcher::matchOperationAddr(User *AddrInst, unsigned Opcode,
PromotedOperand)) {
AddrMode = BackupAddrMode;
AddrModeInsts.resize(OldSize);
DEBUG(dbgs() << "Sign extension does not pay off: rollback\n");
LLVM_DEBUG(dbgs() << "Sign extension does not pay off: rollback\n");
TPT.rollback(LastKnownGood);
return false;
}
@ -4393,7 +4396,8 @@ bool CodeGenPrepare::optimizeMemoryInst(Instruction *MemoryInst, Value *Addr,
if (!PhiOrSelectSeen && none_of(AddrModeInsts, [&](Value *V) {
return IsNonLocalValue(V, MemoryInst->getParent());
})) {
DEBUG(dbgs() << "CGP: Found local addrmode: " << AddrMode << "\n");
LLVM_DEBUG(dbgs() << "CGP: Found local addrmode: " << AddrMode
<< "\n");
return false;
}
@ -4412,16 +4416,16 @@ bool CodeGenPrepare::optimizeMemoryInst(Instruction *MemoryInst, Value *Addr,
Value * SunkAddr = SunkAddrVH.pointsToAliveValue() ? SunkAddrVH : nullptr;
if (SunkAddr) {
DEBUG(dbgs() << "CGP: Reusing nonlocal addrmode: " << AddrMode << " for "
<< *MemoryInst << "\n");
LLVM_DEBUG(dbgs() << "CGP: Reusing nonlocal addrmode: " << AddrMode
<< " for " << *MemoryInst << "\n");
if (SunkAddr->getType() != Addr->getType())
SunkAddr = Builder.CreatePointerCast(SunkAddr, Addr->getType());
} else if (AddrSinkUsingGEPs ||
(!AddrSinkUsingGEPs.getNumOccurrences() && TM && TTI->useAA())) {
// By default, we use the GEP-based method when AA is used later. This
// prevents new inttoptr/ptrtoint pairs from degrading AA capabilities.
DEBUG(dbgs() << "CGP: SINKING nonlocal addrmode: " << AddrMode << " for "
<< *MemoryInst << "\n");
LLVM_DEBUG(dbgs() << "CGP: SINKING nonlocal addrmode: " << AddrMode
<< " for " << *MemoryInst << "\n");
Type *IntPtrTy = DL->getIntPtrType(Addr->getType());
Value *ResultPtr = nullptr, *ResultIndex = nullptr;
@ -4560,8 +4564,8 @@ bool CodeGenPrepare::optimizeMemoryInst(Instruction *MemoryInst, Value *Addr,
DL->isNonIntegralPointerType(AddrMode.BaseGV->getType())))
return false;
DEBUG(dbgs() << "CGP: SINKING nonlocal addrmode: " << AddrMode << " for "
<< *MemoryInst << "\n");
LLVM_DEBUG(dbgs() << "CGP: SINKING nonlocal addrmode: " << AddrMode
<< " for " << *MemoryInst << "\n");
Type *IntPtrTy = DL->getIntPtrType(Addr->getType());
Value *Result = nullptr;
@ -5927,8 +5931,9 @@ class VectorPromoteHelper {
VectorCost += TTI.getArithmeticInstrCost(Inst->getOpcode(), PromotedType,
Arg0OVK, Arg1OVK);
}
DEBUG(dbgs() << "Estimated cost of computation to be promoted:\nScalar: "
<< ScalarCost << "\nVector: " << VectorCost << '\n');
LLVM_DEBUG(
dbgs() << "Estimated cost of computation to be promoted:\nScalar: "
<< ScalarCost << "\nVector: " << VectorCost << '\n');
return ScalarCost > VectorCost;
}
@ -6133,35 +6138,36 @@ bool CodeGenPrepare::optimizeExtractElementInst(Instruction *Inst) {
// => we would need to check that we are moving it at a cheaper place and
// we do not do that for now.
BasicBlock *Parent = Inst->getParent();
DEBUG(dbgs() << "Found an interesting transition: " << *Inst << '\n');
LLVM_DEBUG(dbgs() << "Found an interesting transition: " << *Inst << '\n');
VectorPromoteHelper VPH(*DL, *TLI, *TTI, Inst, CombineCost);
// If the transition has more than one use, assume this is not going to be
// beneficial.
while (Inst->hasOneUse()) {
Instruction *ToBePromoted = cast<Instruction>(*Inst->user_begin());
DEBUG(dbgs() << "Use: " << *ToBePromoted << '\n');
LLVM_DEBUG(dbgs() << "Use: " << *ToBePromoted << '\n');
if (ToBePromoted->getParent() != Parent) {
DEBUG(dbgs() << "Instruction to promote is in a different block ("
<< ToBePromoted->getParent()->getName()
<< ") than the transition (" << Parent->getName() << ").\n");
LLVM_DEBUG(dbgs() << "Instruction to promote is in a different block ("
<< ToBePromoted->getParent()->getName()
<< ") than the transition (" << Parent->getName()
<< ").\n");
return false;
}
if (VPH.canCombine(ToBePromoted)) {
DEBUG(dbgs() << "Assume " << *Inst << '\n'
<< "will be combined with: " << *ToBePromoted << '\n');
LLVM_DEBUG(dbgs() << "Assume " << *Inst << '\n'
<< "will be combined with: " << *ToBePromoted << '\n');
VPH.recordCombineInstruction(ToBePromoted);
bool Changed = VPH.promote();
NumStoreExtractExposed += Changed;
return Changed;
}
DEBUG(dbgs() << "Try promoting.\n");
LLVM_DEBUG(dbgs() << "Try promoting.\n");
if (!VPH.canPromote(ToBePromoted) || !VPH.shouldPromote(ToBePromoted))
return false;
DEBUG(dbgs() << "Promoting is possible... Enqueue for promotion!\n");
LLVM_DEBUG(dbgs() << "Promoting is possible... Enqueue for promotion!\n");
VPH.enqueueForPromotion(ToBePromoted);
Inst = ToBePromoted;
@ -6656,7 +6662,8 @@ bool CodeGenPrepare::placeDbgValues(Function &F) {
// after it.
if (isa<PHINode>(VI) && VI->getParent()->getTerminator()->isEHPad())
continue;
DEBUG(dbgs() << "Moving Debug Value before :\n" << *DVI << ' ' << *VI);
LLVM_DEBUG(dbgs() << "Moving Debug Value before :\n"
<< *DVI << ' ' << *VI);
DVI->removeFromParent();
if (isa<PHINode>(VI))
DVI->insertBefore(&*VI->getParent()->getFirstInsertionPt());
@ -6735,7 +6742,7 @@ bool CodeGenPrepare::splitBranchCondition(Function &F) {
!match(Cond2, m_CombineOr(m_Cmp(), m_BinOp())) )
continue;
DEBUG(dbgs() << "Before branch condition splitting\n"; BB.dump());
LLVM_DEBUG(dbgs() << "Before branch condition splitting\n"; BB.dump());
// Create a new BB.
auto TmpBB =
@ -6863,8 +6870,8 @@ bool CodeGenPrepare::splitBranchCondition(Function &F) {
MadeChange = true;
DEBUG(dbgs() << "After branch condition splitting\n"; BB.dump();
TmpBB->dump());
LLVM_DEBUG(dbgs() << "After branch condition splitting\n"; BB.dump();
TmpBB->dump());
}
return MadeChange;
}

18
llvm/lib/CodeGen/CriticalAntiDepBreaker.cpp
View File

@ -461,14 +461,14 @@ BreakAntiDependencies(const std::vector<SUnit> &SUnits,
#ifndef NDEBUG
{
DEBUG(dbgs() << "Critical path has total latency "
<< (Max->getDepth() + Max->Latency) << "\n");
DEBUG(dbgs() << "Available regs:");
LLVM_DEBUG(dbgs() << "Critical path has total latency "
<< (Max->getDepth() + Max->Latency) << "\n");
LLVM_DEBUG(dbgs() << "Available regs:");
for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) {
if (KillIndices[Reg] == ~0u)
DEBUG(dbgs() << " " << printReg(Reg, TRI));
LLVM_DEBUG(dbgs() << " " << printReg(Reg, TRI));
}
DEBUG(dbgs() << '\n');
LLVM_DEBUG(dbgs() << '\n');
}
#endif
@ -645,10 +645,10 @@ BreakAntiDependencies(const std::vector<SUnit> &SUnits,
AntiDepReg,
LastNewReg[AntiDepReg],
RC, ForbidRegs)) {
DEBUG(dbgs() << "Breaking anti-dependence edge on "
<< printReg(AntiDepReg, TRI) << " with "
<< RegRefs.count(AntiDepReg) << " references"
<< " using " << printReg(NewReg, TRI) << "!\n");
LLVM_DEBUG(dbgs() << "Breaking anti-dependence edge on "
<< printReg(AntiDepReg, TRI) << " with "
<< RegRefs.count(AntiDepReg) << " references"
<< " using " << printReg(NewReg, TRI) << "!\n");
// Update the references to the old register to refer to the new
// register.

28
llvm/lib/CodeGen/DFAPacketizer.cpp
View File

@ -222,7 +222,7 @@ VLIWPacketizerList::~VLIWPacketizerList() {
// End the current packet, bundle packet instructions and reset DFA state.
void VLIWPacketizerList::endPacket(MachineBasicBlock *MBB,
MachineBasicBlock::iterator MI) {
DEBUG({
LLVM_DEBUG({
if (!CurrentPacketMIs.empty()) {
dbgs() << "Finalizing packet:\n";
for (MachineInstr *MI : CurrentPacketMIs)
@ -235,7 +235,7 @@ void VLIWPacketizerList::endPacket(MachineBasicBlock *MBB,
}
CurrentPacketMIs.clear();
ResourceTracker->clearResources();
DEBUG(dbgs() << "End packet\n");
LLVM_DEBUG(dbgs() << "End packet\n");
}
// Bundle machine instructions into packets.
@ -248,7 +248,7 @@ void VLIWPacketizerList::PacketizeMIs(MachineBasicBlock *MBB,
std::distance(BeginItr, EndItr));
VLIWScheduler->schedule();
DEBUG({
LLVM_DEBUG({
dbgs() << "Scheduling DAG of the packetize region\n";
for (SUnit &SU : VLIWScheduler->SUnits)
SU.dumpAll(VLIWScheduler);
@ -287,10 +287,10 @@ void VLIWPacketizerList::PacketizeMIs(MachineBasicBlock *MBB,
assert(SUI && "Missing SUnit Info!");
// Ask DFA if machine resource is available for MI.
DEBUG(dbgs() << "Checking resources for adding MI to packet " << MI);
LLVM_DEBUG(dbgs() << "Checking resources for adding MI to packet " << MI);
bool ResourceAvail = ResourceTracker->canReserveResources(MI);
DEBUG({
LLVM_DEBUG({
if (ResourceAvail)
dbgs() << " Resources are available for adding MI to packet\n";
else
@ -302,31 +302,33 @@ void VLIWPacketizerList::PacketizeMIs(MachineBasicBlock *MBB,
SUnit *SUJ = MIToSUnit[MJ];
assert(SUJ && "Missing SUnit Info!");
DEBUG(dbgs() << " Checking against MJ " << *MJ);
LLVM_DEBUG(dbgs() << " Checking against MJ " << *MJ);
// Is it legal to packetize SUI and SUJ together.
if (!isLegalToPacketizeTogether(SUI, SUJ)) {
DEBUG(dbgs() << " Not legal to add MI, try to prune\n");
LLVM_DEBUG(dbgs() << " Not legal to add MI, try to prune\n");
// Allow packetization if dependency can be pruned.
if (!isLegalToPruneDependencies(SUI, SUJ)) {
// End the packet if dependency cannot be pruned.
DEBUG(dbgs() << " Could not prune dependencies for adding MI\n");
LLVM_DEBUG(dbgs()
<< " Could not prune dependencies for adding MI\n");
endPacket(MBB, MI);
break;
}
DEBUG(dbgs() << " Pruned dependence for adding MI\n");
LLVM_DEBUG(dbgs() << " Pruned dependence for adding MI\n");
}
}
} else {
DEBUG(if (ResourceAvail)
dbgs() << "Resources are available, but instruction should not be "
"added to packet\n " << MI);
LLVM_DEBUG(if (ResourceAvail) dbgs()
<< "Resources are available, but instruction should not be "
"added to packet\n "
<< MI);
// End the packet if resource is not available, or if the instruction
// shoud not be added to the current packet.
endPacket(MBB, MI);
}
// Add MI to the current packet.
DEBUG(dbgs() << "* Adding MI to packet " << MI << '\n');
LLVM_DEBUG(dbgs() << "* Adding MI to packet " << MI << '\n');
BeginItr = addToPacket(MI);
} // For all instructions in the packetization range.

2
llvm/lib/CodeGen/DeadMachineInstructionElim.cpp
View File

@ -125,7 +125,7 @@ bool DeadMachineInstructionElim::runOnMachineFunction(MachineFunction &MF) {
// If the instruction is dead, delete it!
if (isDead(MI)) {
DEBUG(dbgs() << "DeadMachineInstructionElim: DELETING: " << *MI);
LLVM_DEBUG(dbgs() << "DeadMachineInstructionElim: DELETING: " << *MI);
// It is possible that some DBG_VALUE instructions refer to this
// instruction. They get marked as undef and will be deleted
// in the live debug variable analysis.

35
llvm/lib/CodeGen/DetectDeadLanes.cpp
View File

@ -439,7 +439,7 @@ LaneBitmask DetectDeadLanes::determineInitialUsedLanes(unsigned Reg) {
const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg);
CrossCopy = isCrossCopy(*MRI, UseMI, DstRC, MO);
if (CrossCopy)
DEBUG(dbgs() << "Copy across incompatible classes: " << UseMI);
LLVM_DEBUG(dbgs() << "Copy across incompatible classes: " << UseMI);
}
if (!CrossCopy)
@ -520,17 +520,15 @@ bool DetectDeadLanes::runOnce(MachineFunction &MF) {
transferDefinedLanesStep(MO, Info.DefinedLanes);
}
DEBUG(
dbgs() << "Defined/Used lanes:\n";
for (unsigned RegIdx = 0; RegIdx < NumVirtRegs; ++RegIdx) {
unsigned Reg = TargetRegisterInfo::index2VirtReg(RegIdx);
const VRegInfo &Info = VRegInfos[RegIdx];
dbgs() << printReg(Reg, nullptr)
<< " Used: " << PrintLaneMask(Info.UsedLanes)
<< " Def: " << PrintLaneMask(Info.DefinedLanes) << '\n';
}
dbgs() << "\n";
);
LLVM_DEBUG(dbgs() << "Defined/Used lanes:\n"; for (unsigned RegIdx = 0;
RegIdx < NumVirtRegs;
++RegIdx) {
unsigned Reg = TargetRegisterInfo::index2VirtReg(RegIdx);
const VRegInfo &Info = VRegInfos[RegIdx];
dbgs() << printReg(Reg, nullptr)
<< " Used: " << PrintLaneMask(Info.UsedLanes)
<< " Def: " << PrintLaneMask(Info.DefinedLanes) << '\n';
} dbgs() << "\n";);
bool Again = false;
// Mark operands as dead/unused.
@ -545,18 +543,19 @@ bool DetectDeadLanes::runOnce(MachineFunction &MF) {
unsigned RegIdx = TargetRegisterInfo::virtReg2Index(Reg);
const VRegInfo &RegInfo = VRegInfos[RegIdx];
if (MO.isDef() && !MO.isDead() && RegInfo.UsedLanes.none()) {
DEBUG(dbgs() << "Marking operand '" << MO << "' as dead in " << MI);
LLVM_DEBUG(dbgs()
<< "Marking operand '" << MO << "' as dead in " << MI);
MO.setIsDead();
}
if (MO.readsReg()) {
bool CrossCopy = false;
if (isUndefRegAtInput(MO, RegInfo)) {
DEBUG(dbgs() << "Marking operand '" << MO << "' as undef in "
<< MI);
LLVM_DEBUG(dbgs()
<< "Marking operand '" << MO << "' as undef in " << MI);
MO.setIsUndef();
} else if (isUndefInput(MO, &CrossCopy)) {
DEBUG(dbgs() << "Marking operand '" << MO << "' as undef in "
<< MI);
LLVM_DEBUG(dbgs()
<< "Marking operand '" << MO << "' as undef in " << MI);
MO.setIsUndef();
if (CrossCopy)
Again = true;
@ -577,7 +576,7 @@ bool DetectDeadLanes::runOnMachineFunction(MachineFunction &MF) {
// so we safe the compile time.
MRI = &MF.getRegInfo();
if (!MRI->subRegLivenessEnabled()) {
DEBUG(dbgs() << "Skipping Detect dead lanes pass\n");
LLVM_DEBUG(dbgs() << "Skipping Detect dead lanes pass\n");
return false;
}

97
llvm/lib/CodeGen/EarlyIfConversion.cpp
View File

@ -185,7 +185,7 @@ bool SSAIfConv::canSpeculateInstrs(MachineBasicBlock *MBB) {
// Reject any live-in physregs. It's probably CPSR/EFLAGS, and very hard to
// get right.
if (!MBB->livein_empty()) {
DEBUG(dbgs() << printMBBReference(*MBB) << " has live-ins.\n");
LLVM_DEBUG(dbgs() << printMBBReference(*MBB) << " has live-ins.\n");
return false;
}
@ -199,14 +199,14 @@ bool SSAIfConv::canSpeculateInstrs(MachineBasicBlock *MBB) {
continue;
if (++InstrCount > BlockInstrLimit && !Stress) {
DEBUG(dbgs() << printMBBReference(*MBB) << " has more than "
<< BlockInstrLimit << " instructions.\n");
LLVM_DEBUG(dbgs() << printMBBReference(*MBB) << " has more than "
<< BlockInstrLimit << " instructions.\n");
return false;
}
// There shouldn't normally be any phis in a single-predecessor block.
if (I->isPHI()) {
DEBUG(dbgs() << "Can't hoist: " << *I);
LLVM_DEBUG(dbgs() << "Can't hoist: " << *I);
return false;
}
@ -214,21 +214,21 @@ bool SSAIfConv::canSpeculateInstrs(MachineBasicBlock *MBB) {
// speculate GOT or constant pool loads that are guaranteed not to trap,
// but we don't support that for now.
if (I->mayLoad()) {
DEBUG(dbgs() << "Won't speculate load: " << *I);
LLVM_DEBUG(dbgs() << "Won't speculate load: " << *I);
return false;
}
// We never speculate stores, so an AA pointer isn't necessary.
bool DontMoveAcrossStore = true;
if (!I->isSafeToMove(nullptr, DontMoveAcrossStore)) {
DEBUG(dbgs() << "Can't speculate: " << *I);
LLVM_DEBUG(dbgs() << "Can't speculate: " << *I);
return false;
}
// Check for any dependencies on Head instructions.
for (const MachineOperand &MO : I->operands()) {
if (MO.isRegMask()) {
DEBUG(dbgs() << "Won't speculate regmask: " << *I);
LLVM_DEBUG(dbgs() << "Won't speculate regmask: " << *I);
return false;
}
if (!MO.isReg())
@ -246,9 +246,10 @@ bool SSAIfConv::canSpeculateInstrs(MachineBasicBlock *MBB) {
if (!DefMI || DefMI->getParent() != Head)
continue;
if (InsertAfter.insert(DefMI).second)
DEBUG(dbgs() << printMBBReference(*MBB) << " depends on " << *DefMI);
LLVM_DEBUG(dbgs() << printMBBReference(*MBB) << " depends on "
<< *DefMI);
if (DefMI->isTerminator()) {
DEBUG(dbgs() << "Can't insert instructions below terminator.\n");
LLVM_DEBUG(dbgs() << "Can't insert instructions below terminator.\n");
return false;
}
}
@ -279,7 +280,7 @@ bool SSAIfConv::findInsertionPoint() {
--I;
// Some of the conditional code depends in I.
if (InsertAfter.count(&*I)) {
DEBUG(dbgs() << "Can't insert code after " << *I);
LLVM_DEBUG(dbgs() << "Can't insert code after " << *I);
return false;
}
@ -313,7 +314,7 @@ bool SSAIfConv::findInsertionPoint() {
// Some of the clobbered registers are live before I, not a valid insertion
// point.
if (!LiveRegUnits.empty()) {
DEBUG({
LLVM_DEBUG({
dbgs() << "Would clobber";
for (SparseSet<unsigned>::const_iterator
i = LiveRegUnits.begin(), e = LiveRegUnits.end(); i != e; ++i)
@ -325,10 +326,10 @@ bool SSAIfConv::findInsertionPoint() {
// This is a valid insertion point.
InsertionPoint = I;
DEBUG(dbgs() << "Can insert before " << *I);
LLVM_DEBUG(dbgs() << "Can insert before " << *I);
return true;
}
DEBUG(dbgs() << "No legal insertion point found.\n");
LLVM_DEBUG(dbgs() << "No legal insertion point found.\n");
return false;
}
@ -361,39 +362,39 @@ bool SSAIfConv::canConvertIf(MachineBasicBlock *MBB) {
if (Succ1->pred_size() != 1 || Succ1->succ_size() != 1 ||
Succ1->succ_begin()[0] != Tail)
return false;
DEBUG(dbgs() << "\nDiamond: " << printMBBReference(*Head) << " -> "
<< printMBBReference(*Succ0) << "/"
<< printMBBReference(*Succ1) << " -> "
<< printMBBReference(*Tail) << '\n');
LLVM_DEBUG(dbgs() << "\nDiamond: " << printMBBReference(*Head) << " -> "
<< printMBBReference(*Succ0) << "/"
<< printMBBReference(*Succ1) << " -> "
<< printMBBReference(*Tail) << '\n');
// Live-in physregs are tricky to get right when speculating code.
if (!Tail->livein_empty()) {
DEBUG(dbgs() << "Tail has live-ins.\n");
LLVM_DEBUG(dbgs() << "Tail has live-ins.\n");
return false;
}
} else {
DEBUG(dbgs() << "\nTriangle: " << printMBBReference(*Head) << " -> "
<< printMBBReference(*Succ0) << " -> "
<< printMBBReference(*Tail) << '\n');
LLVM_DEBUG(dbgs() << "\nTriangle: " << printMBBReference(*Head) << " -> "
<< printMBBReference(*Succ0) << " -> "
<< printMBBReference(*Tail) << '\n');
}
// This is a triangle or a diamond.
// If Tail doesn't have any phis, there must be side effects.
if (Tail->empty() || !Tail->front().isPHI()) {
DEBUG(dbgs() << "No phis in tail.\n");
LLVM_DEBUG(dbgs() << "No phis in tail.\n");
return false;
}
// The branch we're looking to eliminate must be analyzable.
Cond.clear();
if (TII->analyzeBranch(*Head, TBB, FBB, Cond)) {
DEBUG(dbgs() << "Branch not analyzable.\n");
LLVM_DEBUG(dbgs() << "Branch not analyzable.\n");
return false;
}
// This is weird, probably some sort of degenerate CFG.
if (!TBB) {
DEBUG(dbgs() << "AnalyzeBranch didn't find conditional branch.\n");
LLVM_DEBUG(dbgs() << "AnalyzeBranch didn't find conditional branch.\n");
return false;
}
@ -422,7 +423,7 @@ bool SSAIfConv::canConvertIf(MachineBasicBlock *MBB) {
// Get target information.
if (!TII->canInsertSelect(*Head, Cond, PI.TReg, PI.FReg,
PI.CondCycles, PI.TCycles, PI.FCycles)) {
DEBUG(dbgs() << "Can't convert: " << *PI.PHI);
LLVM_DEBUG(dbgs() << "Can't convert: " << *PI.PHI);
return false;
}
}
@ -459,10 +460,10 @@ void SSAIfConv::replacePHIInstrs() {
// Convert all PHIs to select instructions inserted before FirstTerm.
for (unsigned i = 0, e = PHIs.size(); i != e; ++i) {
PHIInfo &PI = PHIs[i];
DEBUG(dbgs() << "If-converting " << *PI.PHI);
LLVM_DEBUG(dbgs() << "If-converting " << *PI.PHI);
unsigned DstReg = PI.PHI->getOperand(0).getReg();
TII->insertSelect(*Head, FirstTerm, HeadDL, DstReg, Cond, PI.TReg, PI.FReg);
DEBUG(dbgs() << " --> " << *std::prev(FirstTerm));
LLVM_DEBUG(dbgs() << " --> " << *std::prev(FirstTerm));
PI.PHI->eraseFromParent();
PI.PHI = nullptr;
}
@ -481,7 +482,7 @@ void SSAIfConv::rewritePHIOperands() {
PHIInfo &PI = PHIs[i];
unsigned DstReg = 0;
DEBUG(dbgs() << "If-converting " << *PI.PHI);
LLVM_DEBUG(dbgs() << "If-converting " << *PI.PHI);
if (PI.TReg == PI.FReg) {
// We do not need the select instruction if both incoming values are
// equal.
@ -491,7 +492,7 @@ void SSAIfConv::rewritePHIOperands() {
DstReg = MRI->createVirtualRegister(MRI->getRegClass(PHIDst));
TII->insertSelect(*Head, FirstTerm, HeadDL,
DstReg, Cond, PI.TReg, PI.FReg);
DEBUG(dbgs() << " --> " << *std::prev(FirstTerm));
LLVM_DEBUG(dbgs() << " --> " << *std::prev(FirstTerm));
}
// Rewrite PHI operands TPred -> (DstReg, Head), remove FPred.
@ -505,7 +506,7 @@ void SSAIfConv::rewritePHIOperands() {
PI.PHI->RemoveOperand(i-2);
}
}
DEBUG(dbgs() << " --> " << *PI.PHI);
LLVM_DEBUG(dbgs() << " --> " << *PI.PHI);
}
}
@ -563,8 +564,8 @@ void SSAIfConv::convertIf(SmallVectorImpl<MachineBasicBlock*> &RemovedBlocks) {
assert(Head->succ_empty() && "Additional head successors?");
if (!ExtraPreds && Head->isLayoutSuccessor(Tail)) {
// Splice Tail onto the end of Head.
DEBUG(dbgs() << "Joining tail " << printMBBReference(*Tail) << " into head "
<< printMBBReference(*Head) << '\n');
LLVM_DEBUG(dbgs() << "Joining tail " << printMBBReference(*Tail)
<< " into head " << printMBBReference(*Head) << '\n');
Head->splice(Head->end(), Tail,
Tail->begin(), Tail->end());
Head->transferSuccessorsAndUpdatePHIs(Tail);
@ -572,12 +573,12 @@ void SSAIfConv::convertIf(SmallVectorImpl<MachineBasicBlock*> &RemovedBlocks) {
Tail->eraseFromParent();
} else {
// We need a branch to Tail, let code placement work it out later.
DEBUG(dbgs() << "Converting to unconditional branch.\n");
LLVM_DEBUG(dbgs() << "Converting to unconditional branch.\n");
SmallVector<MachineOperand, 0> EmptyCond;
TII->insertBranch(*Head, Tail, nullptr, EmptyCond, HeadDL);
Head->addSuccessor(Tail);
}
DEBUG(dbgs() << *Head);
LLVM_DEBUG(dbgs() << *Head);
}
@ -692,7 +693,7 @@ bool EarlyIfConverter::shouldConvertIf() {
MachineTraceMetrics::Trace TBBTrace = MinInstr->getTrace(IfConv.getTPred());
MachineTraceMetrics::Trace FBBTrace = MinInstr->getTrace(IfConv.getFPred());
DEBUG(dbgs() << "TBB: " << TBBTrace << "FBB: " << FBBTrace);
LLVM_DEBUG(dbgs() << "TBB: " << TBBTrace << "FBB: " << FBBTrace);
unsigned MinCrit = std::min(TBBTrace.getCriticalPath(),
FBBTrace.getCriticalPath());
@ -706,10 +707,10 @@ bool EarlyIfConverter::shouldConvertIf() {
if (IfConv.TBB != IfConv.Tail)
ExtraBlocks.push_back(IfConv.TBB);
unsigned ResLength = FBBTrace.getResourceLength(ExtraBlocks);
DEBUG(dbgs() << "Resource length " << ResLength
<< ", minimal critical path " << MinCrit << '\n');
LLVM_DEBUG(dbgs() << "Resource length " << ResLength
<< ", minimal critical path " << MinCrit << '\n');
if (ResLength > MinCrit + CritLimit) {
DEBUG(dbgs() << "Not enough available ILP.\n");
LLVM_DEBUG(dbgs() << "Not enough available ILP.\n");
return false;
}
@ -719,7 +720,7 @@ bool EarlyIfConverter::shouldConvertIf() {
MachineTraceMetrics::Trace HeadTrace = MinInstr->getTrace(IfConv.Head);
unsigned BranchDepth =
HeadTrace.getInstrCycles(*IfConv.Head->getFirstTerminator()).Depth;
DEBUG(dbgs() << "Branch depth: " << BranchDepth << '\n');
LLVM_DEBUG(dbgs() << "Branch depth: " << BranchDepth << '\n');
// Look at all the tail phis, and compute the critical path extension caused
// by inserting select instructions.
@ -728,15 +729,15 @@ bool EarlyIfConverter::shouldConvertIf() {
SSAIfConv::PHIInfo &PI = IfConv.PHIs[i];
unsigned Slack = TailTrace.getInstrSlack(*PI.PHI);
unsigned MaxDepth = Slack + TailTrace.getInstrCycles(*PI.PHI).Depth;
DEBUG(dbgs() << "Slack " << Slack << ":\t" << *PI.PHI);
LLVM_DEBUG(dbgs() << "Slack " << Slack << ":\t" << *PI.PHI);
// The condition is pulled into the critical path.
unsigned CondDepth = adjCycles(BranchDepth, PI.CondCycles);
if (CondDepth > MaxDepth) {
unsigned Extra = CondDepth - MaxDepth;
DEBUG(dbgs() << "Condition adds " << Extra << " cycles.\n");
LLVM_DEBUG(dbgs() << "Condition adds " << Extra << " cycles.\n");
if (Extra > CritLimit) {
DEBUG(dbgs() << "Exceeds limit of " << CritLimit << '\n');
LLVM_DEBUG(dbgs() << "Exceeds limit of " << CritLimit << '\n');
return false;
}
}
@ -745,9 +746,9 @@ bool EarlyIfConverter::shouldConvertIf() {
unsigned TDepth = adjCycles(TBBTrace.getPHIDepth(*PI.PHI), PI.TCycles);
if (TDepth > MaxDepth) {
unsigned Extra = TDepth - MaxDepth;
DEBUG(dbgs() << "TBB data adds " << Extra << " cycles.\n");
LLVM_DEBUG(dbgs() << "TBB data adds " << Extra << " cycles.\n");
if (Extra > CritLimit) {
DEBUG(dbgs() << "Exceeds limit of " << CritLimit << '\n');
LLVM_DEBUG(dbgs() << "Exceeds limit of " << CritLimit << '\n');
return false;
}
}
@ -756,9 +757,9 @@ bool EarlyIfConverter::shouldConvertIf() {
unsigned FDepth = adjCycles(FBBTrace.getPHIDepth(*PI.PHI), PI.FCycles);
if (FDepth > MaxDepth) {
unsigned Extra = FDepth - MaxDepth;
DEBUG(dbgs() << "FBB data adds " << Extra << " cycles.\n");
LLVM_DEBUG(dbgs() << "FBB data adds " << Extra << " cycles.\n");
if (Extra > CritLimit) {
DEBUG(dbgs() << "Exceeds limit of " << CritLimit << '\n');
LLVM_DEBUG(dbgs() << "Exceeds limit of " << CritLimit << '\n');
return false;
}
}
@ -783,8 +784,8 @@ bool EarlyIfConverter::tryConvertIf(MachineBasicBlock *MBB) {
}
bool EarlyIfConverter::runOnMachineFunction(MachineFunction &MF) {
DEBUG(dbgs() << "********** EARLY IF-CONVERSION **********\n"
<< "********** Function: " << MF.getName() << '\n');
LLVM_DEBUG(dbgs() << "********** EARLY IF-CONVERSION **********\n"
<< "********** Function: " << MF.getName() << '\n');
if (skipFunction(MF.getFunction()))
return false;

14
llvm/lib/CodeGen/ExecutionDomainFix.cpp
View File

@ -161,7 +161,7 @@ void ExecutionDomainFix::enterBasicBlock(
// This is the entry block.
if (MBB->pred_empty()) {
DEBUG(dbgs() << printMBBReference(*MBB) << ": entry\n");
LLVM_DEBUG(dbgs() << printMBBReference(*MBB) << ": entry\n");
return;
}
@ -200,9 +200,9 @@ void ExecutionDomainFix::enterBasicBlock(
force(rx, pdv->getFirstDomain());
}
}
DEBUG(dbgs() << printMBBReference(*MBB)
<< (!TraversedMBB.IsDone ? ": incomplete\n"
: ": all preds known\n"));
LLVM_DEBUG(dbgs() << printMBBReference(*MBB)
<< (!TraversedMBB.IsDone ? ": incomplete\n"
: ": all preds known\n"));
}
void ExecutionDomainFix::leaveBasicBlock(
@ -245,7 +245,7 @@ void ExecutionDomainFix::processDefs(MachineInstr *MI, bool Kill) {
continue;
for (int rx : regIndices(MO.getReg())) {
// This instruction explicitly defines rx.
DEBUG(dbgs() << printReg(RC->getRegister(rx), TRI) << ":\t" << *MI);
LLVM_DEBUG(dbgs() << printReg(RC->getRegister(rx), TRI) << ":\t" << *MI);
// Kill off domains redefined by generic instructions.
if (Kill)
@ -420,8 +420,8 @@ bool ExecutionDomainFix::runOnMachineFunction(MachineFunction &mf) {
LiveRegs.clear();
assert(NumRegs == RC->getNumRegs() && "Bad regclass");
DEBUG(dbgs() << "********** FIX EXECUTION DOMAIN: "
<< TRI->getRegClassName(RC) << " **********\n");
LLVM_DEBUG(dbgs() << "********** FIX EXECUTION DOMAIN: "
<< TRI->getRegClassName(RC) << " **********\n");
// If no relevant registers are used in the function, we can skip it
// completely.

31
llvm/lib/CodeGen/ExpandPostRAPseudos.cpp
View File

@ -93,11 +93,11 @@ bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) {
assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
"Inserted value must be in a physical register");
DEBUG(dbgs() << "subreg: CONVERTING: " << *MI);
LLVM_DEBUG(dbgs() << "subreg: CONVERTING: " << *MI);
if (MI->allDefsAreDead()) {
MI->setDesc(TII->get(TargetOpcode::KILL));
DEBUG(dbgs() << "subreg: replaced by: " << *MI);
LLVM_DEBUG(dbgs() << "subreg: replaced by: " << *MI);
return true;
}
@ -110,10 +110,10 @@ bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) {
MI->setDesc(TII->get(TargetOpcode::KILL));
MI->RemoveOperand(3); // SubIdx
MI->RemoveOperand(1); // Imm
DEBUG(dbgs() << "subreg: replace by: " << *MI);
LLVM_DEBUG(dbgs() << "subreg: replace by: " << *MI);
return true;
}
DEBUG(dbgs() << "subreg: eliminated!");
LLVM_DEBUG(dbgs() << "subreg: eliminated!");
} else {
TII->copyPhysReg(*MBB, MI, MI->getDebugLoc(), DstSubReg, InsReg,
MI->getOperand(2).isKill());
@ -122,10 +122,10 @@ bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) {
MachineBasicBlock::iterator CopyMI = MI;
--CopyMI;
CopyMI->addRegisterDefined(DstReg);
DEBUG(dbgs() << "subreg: " << *CopyMI);
LLVM_DEBUG(dbgs() << "subreg: " << *CopyMI);
}
DEBUG(dbgs() << '\n');
LLVM_DEBUG(dbgs() << '\n');
MBB->erase(MI);
return true;
}
@ -133,9 +133,9 @@ bool ExpandPostRA::LowerSubregToReg(MachineInstr *MI) {
bool ExpandPostRA::LowerCopy(MachineInstr *MI) {
if (MI->allDefsAreDead()) {
DEBUG(dbgs() << "dead copy: " << *MI);
LLVM_DEBUG(dbgs() << "dead copy: " << *MI);
MI->setDesc(TII->get(TargetOpcode::KILL));
DEBUG(dbgs() << "replaced by: " << *MI);
LLVM_DEBUG(dbgs() << "replaced by: " << *MI);
return true;
}
@ -144,14 +144,15 @@ bool ExpandPostRA::LowerCopy(MachineInstr *MI) {
bool IdentityCopy = (SrcMO.getReg() == DstMO.getReg());
if (IdentityCopy || SrcMO.isUndef()) {
DEBUG(dbgs() << (IdentityCopy ? "identity copy: " : "undef copy: ") << *MI);
LLVM_DEBUG(dbgs() << (IdentityCopy ? "identity copy: " : "undef copy: ")
<< *MI);
// No need to insert an identity copy instruction, but replace with a KILL
// if liveness is changed.
if (SrcMO.isUndef() || MI->getNumOperands() > 2) {
// We must make sure the super-register gets killed. Replace the
// instruction with KILL.
MI->setDesc(TII->get(TargetOpcode::KILL));
DEBUG(dbgs() << "replaced by: " << *MI);
LLVM_DEBUG(dbgs() << "replaced by: " << *MI);
return true;
}
// Vanilla identity copy.
@ -159,13 +160,13 @@ bool ExpandPostRA::LowerCopy(MachineInstr *MI) {
return true;
}
DEBUG(dbgs() << "real copy: " << *MI);
LLVM_DEBUG(dbgs() << "real copy: " << *MI);
TII->copyPhysReg(*MI->getParent(), MI, MI->getDebugLoc(),
DstMO.getReg(), SrcMO.getReg(), SrcMO.isKill());
if (MI->getNumOperands() > 2)
TransferImplicitOperands(MI);
DEBUG({
LLVM_DEBUG({
MachineBasicBlock::iterator dMI = MI;
dbgs() << "replaced by: " << *(--dMI);
});
@ -177,9 +178,9 @@ bool ExpandPostRA::LowerCopy(MachineInstr *MI) {
/// copies.
///
bool ExpandPostRA::runOnMachineFunction(MachineFunction &MF) {
DEBUG(dbgs() << "Machine Function\n"
<< "********** EXPANDING POST-RA PSEUDO INSTRS **********\n"
<< "********** Function: " << MF.getName() << '\n');
LLVM_DEBUG(dbgs() << "Machine Function\n"
<< "********** EXPANDING POST-RA PSEUDO INSTRS **********\n"
<< "********** Function: " << MF.getName() << '\n');
TRI = MF.getSubtarget().getRegisterInfo();
TII = MF.getSubtarget().getInstrInfo();

22
llvm/lib/CodeGen/FaultMaps.cpp
View File

@ -62,17 +62,17 @@ void FaultMaps::serializeToFaultMapSection() {
// Emit a dummy symbol to force section inclusion.
OS.EmitLabel(OutContext.getOrCreateSymbol(Twine("__LLVM_FaultMaps")));
DEBUG(dbgs() << "********** Fault Map Output **********\n");
LLVM_DEBUG(dbgs() << "********** Fault Map Output **********\n");
// Header
OS.EmitIntValue(FaultMapVersion, 1); // Version.
OS.EmitIntValue(0, 1); // Reserved.
OS.EmitIntValue(0, 2); // Reserved.
DEBUG(dbgs() << WFMP << "#functions = " << FunctionInfos.size() << "\n");
LLVM_DEBUG(dbgs() << WFMP << "#functions = " << FunctionInfos.size() << "\n");
OS.EmitIntValue(FunctionInfos.size(), 4);
DEBUG(dbgs() << WFMP << "functions:\n");
LLVM_DEBUG(dbgs() << WFMP << "functions:\n");
for (const auto &FFI : FunctionInfos)
emitFunctionInfo(FFI.first, FFI.second);
@ -82,25 +82,25 @@ void FaultMaps::emitFunctionInfo(const MCSymbol *FnLabel,
const FunctionFaultInfos &FFI) {
MCStreamer &OS = *AP.OutStreamer;
DEBUG(dbgs() << WFMP << " function addr: " << *FnLabel << "\n");
LLVM_DEBUG(dbgs() << WFMP << " function addr: " << *FnLabel << "\n");
OS.EmitSymbolValue(FnLabel, 8);
DEBUG(dbgs() << WFMP << " #faulting PCs: " << FFI.size() << "\n");
LLVM_DEBUG(dbgs() << WFMP << " #faulting PCs: " << FFI.size() << "\n");
OS.EmitIntValue(FFI.size(), 4);
OS.EmitIntValue(0, 4); // Reserved
for (auto &Fault : FFI) {
DEBUG(dbgs() << WFMP << " fault type: "
<< faultTypeToString(Fault.Kind) << "\n");
LLVM_DEBUG(dbgs() << WFMP << " fault type: "
<< faultTypeToString(Fault.Kind) << "\n");
OS.EmitIntValue(Fault.Kind, 4);
DEBUG(dbgs() << WFMP << " faulting PC offset: "
<< *Fault.FaultingOffsetExpr << "\n");
LLVM_DEBUG(dbgs() << WFMP << " faulting PC offset: "
<< *Fault.FaultingOffsetExpr << "\n");
OS.EmitValue(Fault.FaultingOffsetExpr, 4);
DEBUG(dbgs() << WFMP << " fault handler PC offset: "
<< *Fault.HandlerOffsetExpr << "\n");
LLVM_DEBUG(dbgs() << WFMP << " fault handler PC offset: "
<< *Fault.HandlerOffsetExpr << "\n");
OS.EmitValue(Fault.HandlerOffsetExpr, 4);
}
}

6
llvm/lib/CodeGen/GlobalISel/Combiner.cpp
View File

@ -40,7 +40,7 @@ bool Combiner::combineMachineInstrs(MachineFunction &MF) {
MRI = &MF.getRegInfo();
Builder.setMF(MF);
DEBUG(dbgs() << "Generic MI Combiner for: " << MF.getName() << '\n');
LLVM_DEBUG(dbgs() << "Generic MI Combiner for: " << MF.getName() << '\n');
MachineOptimizationRemarkEmitter MORE(MF, /*MBFI=*/nullptr);
@ -61,7 +61,7 @@ bool Combiner::combineMachineInstrs(MachineFunction &MF) {
++MII;
// Erase dead insts before even adding to the list.
if (isTriviallyDead(*CurMI, *MRI)) {
DEBUG(dbgs() << *CurMI << "Is dead; erasing.\n");
LLVM_DEBUG(dbgs() << *CurMI << "Is dead; erasing.\n");
CurMI->eraseFromParentAndMarkDBGValuesForRemoval();
continue;
}
@ -71,7 +71,7 @@ bool Combiner::combineMachineInstrs(MachineFunction &MF) {
// Main Loop. Process the instructions here.
while (!WorkList.empty()) {
MachineInstr *CurrInst = WorkList.pop_back_val();
DEBUG(dbgs() << "Try combining " << *CurrInst << "\n";);
LLVM_DEBUG(dbgs() << "Try combining " << *CurrInst << "\n";);
Changed |= CInfo.combine(*CurrInst, Builder);
}
MFChanged |= Changed;

2
llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
View File

@ -652,7 +652,7 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
const Value *Address = DI.getAddress();
if (!Address || isa<UndefValue>(Address)) {
DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
LLVM_DEBUG(dbgs() << "Dropping debug info for " << DI << "\n");
return true;
}

10
llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
View File

@ -65,7 +65,7 @@ bool InstructionSelect::runOnMachineFunction(MachineFunction &MF) {
MachineFunctionProperties::Property::FailedISel))
return false;
DEBUG(dbgs() << "Selecting function: " << MF.getName() << '\n');
LLVM_DEBUG(dbgs() << "Selecting function: " << MF.getName() << '\n');
const TargetPassConfig &TPC = getAnalysis<TargetPassConfig>();
const InstructionSelector *ISel = MF.getSubtarget().getInstructionSelector();
@ -116,12 +116,12 @@ bool InstructionSelect::runOnMachineFunction(MachineFunction &MF) {
else
--MII;
DEBUG(dbgs() << "Selecting: \n " << MI);
LLVM_DEBUG(dbgs() << "Selecting: \n " << MI);
// We could have folded this instruction away already, making it dead.
// If so, erase it.
if (isTriviallyDead(MI, MRI)) {
DEBUG(dbgs() << "Is dead; erasing.\n");
LLVM_DEBUG(dbgs() << "Is dead; erasing.\n");
MI.eraseFromParentAndMarkDBGValuesForRemoval();
continue;
}
@ -134,7 +134,7 @@ bool InstructionSelect::runOnMachineFunction(MachineFunction &MF) {
}
// Dump the range of instructions that MI expanded into.
DEBUG({
LLVM_DEBUG({
auto InsertedBegin = ReachedBegin ? MBB->begin() : std::next(MII);
dbgs() << "Into:\n";
for (auto &InsertedMI : make_range(InsertedBegin, AfterIt))
@ -218,7 +218,7 @@ bool InstructionSelect::runOnMachineFunction(MachineFunction &MF) {
auto &TLI = *MF.getSubtarget().getTargetLowering();
TLI.finalizeLowering(MF);
DEBUG({
LLVM_DEBUG({
dbgs() << "Rules covered by selecting function: " << MF.getName() << ":";
for (auto RuleID : CoverageInfo.covered())
dbgs() << " id" << RuleID;

10
llvm/lib/CodeGen/GlobalISel/Legalizer.cpp
View File

@ -72,7 +72,7 @@ bool Legalizer::runOnMachineFunction(MachineFunction &MF) {
if (MF.getProperties().hasProperty(
MachineFunctionProperties::Property::FailedISel))
return false;
DEBUG(dbgs() << "Legalize Machine IR for: " << MF.getName() << '\n');
LLVM_DEBUG(dbgs() << "Legalize Machine IR for: " << MF.getName() << '\n');
init(MF);
const TargetPassConfig &TPC = getAnalysis<TargetPassConfig>();
MachineOptimizationRemarkEmitter MORE(MF, /*MBFI=*/nullptr);
@ -112,7 +112,7 @@ bool Legalizer::runOnMachineFunction(MachineFunction &MF) {
else
InstList.insert(MI);
}
DEBUG(dbgs() << ".. .. New MI: " << *MI;);
LLVM_DEBUG(dbgs() << ".. .. New MI: " << *MI;);
});
const LegalizerInfo &LInfo(Helper.getLegalizerInfo());
LegalizationArtifactCombiner ArtCombiner(Helper.MIRBuilder, MF.getRegInfo(), LInfo);
@ -127,7 +127,7 @@ bool Legalizer::runOnMachineFunction(MachineFunction &MF) {
MachineInstr &MI = *InstList.pop_back_val();
assert(isPreISelGenericOpcode(MI.getOpcode()) && "Expecting generic opcode");
if (isTriviallyDead(MI, MRI)) {
DEBUG(dbgs() << MI << "Is dead; erasing.\n");
LLVM_DEBUG(dbgs() << MI << "Is dead; erasing.\n");
MI.eraseFromParentAndMarkDBGValuesForRemoval();
continue;
}
@ -148,7 +148,7 @@ bool Legalizer::runOnMachineFunction(MachineFunction &MF) {
MachineInstr &MI = *ArtifactList.pop_back_val();
assert(isPreISelGenericOpcode(MI.getOpcode()) && "Expecting generic opcode");
if (isTriviallyDead(MI, MRI)) {
DEBUG(dbgs() << MI << "Is dead; erasing.\n");
LLVM_DEBUG(dbgs() << MI << "Is dead; erasing.\n");
RemoveDeadInstFromLists(&MI);
MI.eraseFromParentAndMarkDBGValuesForRemoval();
continue;
@ -156,7 +156,7 @@ bool Legalizer::runOnMachineFunction(MachineFunction &MF) {
SmallVector<MachineInstr *, 4> DeadInstructions;
if (ArtCombiner.tryCombineInstruction(MI, DeadInstructions)) {
for (auto *DeadMI : DeadInstructions) {
DEBUG(dbgs() << ".. Erasing Dead Instruction " << *DeadMI);
LLVM_DEBUG(dbgs() << ".. Erasing Dead Instruction " << *DeadMI);
RemoveDeadInstFromLists(DeadMI);
DeadMI->eraseFromParentAndMarkDBGValuesForRemoval();
}

18
llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
View File

@ -35,34 +35,34 @@ LegalizerHelper::LegalizerHelper(MachineFunction &MF)
LegalizerHelper::LegalizeResult
LegalizerHelper::legalizeInstrStep(MachineInstr &MI) {
DEBUG(dbgs() << "Legalizing: "; MI.print(dbgs()));
LLVM_DEBUG(dbgs() << "Legalizing: "; MI.print(dbgs()));
auto Step = LI.getAction(MI, MRI);
switch (Step.Action) {
case Legal:
DEBUG(dbgs() << ".. Already legal\n");
LLVM_DEBUG(dbgs() << ".. Already legal\n");
return AlreadyLegal;
case Libcall:
DEBUG(dbgs() << ".. Convert to libcall\n");
LLVM_DEBUG(dbgs() << ".. Convert to libcall\n");
return libcall(MI);
case NarrowScalar:
DEBUG(dbgs() << ".. Narrow scalar\n");
LLVM_DEBUG(dbgs() << ".. Narrow scalar\n");
return narrowScalar(MI, Step.TypeIdx, Step.NewType);
case WidenScalar:
DEBUG(dbgs() << ".. Widen scalar\n");
LLVM_DEBUG(dbgs() << ".. Widen scalar\n");
return widenScalar(MI, Step.TypeIdx, Step.NewType);
case Lower:
DEBUG(dbgs() << ".. Lower\n");
LLVM_DEBUG(dbgs() << ".. Lower\n");
return lower(MI, Step.TypeIdx, Step.NewType);
case FewerElements:
DEBUG(dbgs() << ".. Reduce number of elements\n");
LLVM_DEBUG(dbgs() << ".. Reduce number of elements\n");
return fewerElementsVector(MI, Step.TypeIdx, Step.NewType);
case Custom:
DEBUG(dbgs() << ".. Custom legalization\n");
LLVM_DEBUG(dbgs() << ".. Custom legalization\n");
return LI.legalizeCustom(MI, MRI, MIRBuilder) ? Legalized
: UnableToLegalize;
default:
DEBUG(dbgs() << ".. Unable to legalize\n");
LLVM_DEBUG(dbgs() << ".. Unable to legalize\n");
return UnableToLegalize;
}
}

33
llvm/lib/CodeGen/GlobalISel/LegalizerInfo.cpp
View File

@ -58,18 +58,18 @@ raw_ostream &LegalityQuery::print(raw_ostream &OS) const {
}
LegalizeActionStep LegalizeRuleSet::apply(const LegalityQuery &Query) const {
DEBUG(dbgs() << "Applying legalizer ruleset to: "; Query.print(dbgs());
dbgs() << "\n");
LLVM_DEBUG(dbgs() << "Applying legalizer ruleset to: "; Query.print(dbgs());
dbgs() << "\n");
if (Rules.empty()) {
DEBUG(dbgs() << ".. fallback to legacy rules (no rules defined)\n");
LLVM_DEBUG(dbgs() << ".. fallback to legacy rules (no rules defined)\n");
return {LegalizeAction::UseLegacyRules, 0, LLT{}};
}
for (const auto &Rule : Rules) {
if (Rule.match(Query)) {
DEBUG(dbgs() << ".. match\n");
LLVM_DEBUG(dbgs() << ".. match\n");
std::pair<unsigned, LLT> Mutation = Rule.determineMutation(Query);
DEBUG(dbgs() << ".. .. " << (unsigned)Rule.getAction() << ", "
<< Mutation.first << ", " << Mutation.second << "\n");
LLVM_DEBUG(dbgs() << ".. .. " << (unsigned)Rule.getAction() << ", "
<< Mutation.first << ", " << Mutation.second << "\n");
assert((Query.Types[Mutation.first] != Mutation.second ||
Rule.getAction() == Lower ||
Rule.getAction() == MoreElements ||
@ -77,9 +77,9 @@ LegalizeActionStep LegalizeRuleSet::apply(const LegalityQuery &Query) const {
"Simple loop detected");
return {Rule.getAction(), Mutation.first, Mutation.second};
} else
DEBUG(dbgs() << ".. no match\n");
LLVM_DEBUG(dbgs() << ".. no match\n");
}
DEBUG(dbgs() << ".. unsupported\n");
LLVM_DEBUG(dbgs() << ".. unsupported\n");
return {LegalizeAction::Unsupported, 0, LLT{}};
}
@ -247,11 +247,11 @@ unsigned LegalizerInfo::getOpcodeIdxForOpcode(unsigned Opcode) const {
unsigned LegalizerInfo::getActionDefinitionsIdx(unsigned Opcode) const {
unsigned OpcodeIdx = getOpcodeIdxForOpcode(Opcode);
if (unsigned Alias = RulesForOpcode[OpcodeIdx].getAlias()) {
DEBUG(dbgs() << ".. opcode " << Opcode << " is aliased to " << Alias
<< "\n");
LLVM_DEBUG(dbgs() << ".. opcode " << Opcode << " is aliased to " << Alias
<< "\n");
OpcodeIdx = getOpcodeIdxForOpcode(Alias);
DEBUG(dbgs() << ".. opcode " << Alias << " is aliased to "
<< RulesForOpcode[OpcodeIdx].getAlias() << "\n");
LLVM_DEBUG(dbgs() << ".. opcode " << Alias << " is aliased to "
<< RulesForOpcode[OpcodeIdx].getAlias() << "\n");
assert(RulesForOpcode[OpcodeIdx].getAlias() == 0 && "Cannot chain aliases");
}
@ -305,13 +305,14 @@ LegalizerInfo::getAction(const LegalityQuery &Query) const {
for (unsigned i = 0; i < Query.Types.size(); ++i) {
auto Action = getAspectAction({Query.Opcode, i, Query.Types[i]});
if (Action.first != Legal) {
DEBUG(dbgs() << ".. (legacy) Type " << i << " Action="
<< (unsigned)Action.first << ", " << Action.second << "\n");
LLVM_DEBUG(dbgs() << ".. (legacy) Type " << i
<< " Action=" << (unsigned)Action.first << ", "
<< Action.second << "\n");
return {Action.first, i, Action.second};
} else
DEBUG(dbgs() << ".. (legacy) Type " << i << " Legal\n");
LLVM_DEBUG(dbgs() << ".. (legacy) Type " << i << " Legal\n");
}
DEBUG(dbgs() << ".. (legacy) Legal\n");
LLVM_DEBUG(dbgs() << ".. (legacy) Legal\n");
return {Legal, 0, LLT{}};
}

18
llvm/lib/CodeGen/GlobalISel/Localizer.cpp
View File

@ -59,7 +59,7 @@ bool Localizer::runOnMachineFunction(MachineFunction &MF) {
MachineFunctionProperties::Property::FailedISel))
return false;
DEBUG(dbgs() << "Localize instructions for: " << MF.getName() << '\n');
LLVM_DEBUG(dbgs() << "Localize instructions for: " << MF.getName() << '\n');
init(MF);
@ -73,7 +73,7 @@ bool Localizer::runOnMachineFunction(MachineFunction &MF) {
for (MachineInstr &MI : MBB) {
if (LocalizedInstrs.count(&MI) || !shouldLocalize(MI))
continue;
DEBUG(dbgs() << "Should localize: " << MI);
LLVM_DEBUG(dbgs() << "Should localize: " << MI);
assert(MI.getDesc().getNumDefs() == 1 &&
"More than one definition not supported yet");
unsigned Reg = MI.getOperand(0).getReg();
@ -85,12 +85,12 @@ bool Localizer::runOnMachineFunction(MachineFunction &MF) {
MachineOperand &MOUse = *MOIt++;
// Check if the use is already local.
MachineBasicBlock *InsertMBB;
DEBUG(MachineInstr &MIUse = *MOUse.getParent();
dbgs() << "Checking use: " << MIUse
<< " #Opd: " << MIUse.getOperandNo(&MOUse) << '\n');
LLVM_DEBUG(MachineInstr &MIUse = *MOUse.getParent();
dbgs() << "Checking use: " << MIUse
<< " #Opd: " << MIUse.getOperandNo(&MOUse) << '\n');
if (isLocalUse(MOUse, MI, InsertMBB))
continue;
DEBUG(dbgs() << "Fixing non-local use\n");
LLVM_DEBUG(dbgs() << "Fixing non-local use\n");
Changed = true;
auto MBBAndReg = std::make_pair(InsertMBB, Reg);
auto NewVRegIt = MBBWithLocalDef.find(MBBAndReg);
@ -111,10 +111,10 @@ bool Localizer::runOnMachineFunction(MachineFunction &MF) {
LocalizedMI->getOperand(0).setReg(NewReg);
NewVRegIt =
MBBWithLocalDef.insert(std::make_pair(MBBAndReg, NewReg)).first;
DEBUG(dbgs() << "Inserted: " << *LocalizedMI);
LLVM_DEBUG(dbgs() << "Inserted: " << *LocalizedMI);
}
DEBUG(dbgs() << "Update use with: " << printReg(NewVRegIt->second)
<< '\n');
LLVM_DEBUG(dbgs() << "Update use with: " << printReg(NewVRegIt->second)
<< '\n');
// Update the user reg.
MOUse.setReg(NewVRegIt->second);
}

44
llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp
View File

@ -76,7 +76,7 @@ RegBankSelect::RegBankSelect(Mode RunningMode)
if (RegBankSelectMode.getNumOccurrences() != 0) {
OptMode = RegBankSelectMode;
if (RegBankSelectMode != RunningMode)
DEBUG(dbgs() << "RegBankSelect mode overrided by command line\n");
LLVM_DEBUG(dbgs() << "RegBankSelect mode overrided by command line\n");
}
}
@ -123,11 +123,11 @@ bool RegBankSelect::assignmentMatch(
// Reg is free of assignment, a simple assignment will make the
// register bank to match.
OnlyAssign = CurRegBank == nullptr;
DEBUG(dbgs() << "Does assignment already match: ";
if (CurRegBank) dbgs() << *CurRegBank; else dbgs() << "none";
dbgs() << " against ";
assert(DesiredRegBrank && "The mapping must be valid");
dbgs() << *DesiredRegBrank << '\n';);
LLVM_DEBUG(dbgs() << "Does assignment already match: ";
if (CurRegBank) dbgs() << *CurRegBank; else dbgs() << "none";
dbgs() << " against ";
assert(DesiredRegBrank && "The mapping must be valid");
dbgs() << *DesiredRegBrank << '\n';);
return CurRegBank == DesiredRegBrank;
}
@ -160,8 +160,8 @@ bool RegBankSelect::repairReg(
// same types because the type is a placeholder when this function is called.
MachineInstr *MI =
MIRBuilder.buildInstrNoInsert(TargetOpcode::COPY).addDef(Dst).addUse(Src);
DEBUG(dbgs() << "Copy: " << printReg(Src) << " to: " << printReg(Dst)
<< '\n');
LLVM_DEBUG(dbgs() << "Copy: " << printReg(Src) << " to: " << printReg(Dst)
<< '\n');
// TODO:
// Check if MI is legal. if not, we need to legalize all the
// instructions we are going to insert.
@ -246,7 +246,7 @@ const RegisterBankInfo::InstructionMapping &RegBankSelect::findBestMapping(
MappingCost CurCost =
computeMapping(MI, *CurMapping, LocalRepairPts, &Cost);
if (CurCost < Cost) {
DEBUG(dbgs() << "New best: " << CurCost << '\n');
LLVM_DEBUG(dbgs() << "New best: " << CurCost << '\n');
Cost = CurCost;
BestMapping = CurMapping;
RepairPts.clear();
@ -398,11 +398,11 @@ RegBankSelect::MappingCost RegBankSelect::computeMapping(
MappingCost Cost(MBFI ? MBFI->getBlockFreq(MI.getParent()) : 1);
bool Saturated = Cost.addLocalCost(InstrMapping.getCost());
assert(!Saturated && "Possible mapping saturated the cost");
DEBUG(dbgs() << "Evaluating mapping cost for: " << MI);
DEBUG(dbgs() << "With: " << InstrMapping << '\n');
LLVM_DEBUG(dbgs() << "Evaluating mapping cost for: " << MI);
LLVM_DEBUG(dbgs() << "With: " << InstrMapping << '\n');
RepairPts.clear();
if (BestCost && Cost > *BestCost) {
DEBUG(dbgs() << "Mapping is too expensive from the start\n");
LLVM_DEBUG(dbgs() << "Mapping is too expensive from the start\n");
return Cost;
}
@ -418,17 +418,17 @@ RegBankSelect::MappingCost RegBankSelect::computeMapping(
unsigned Reg = MO.getReg();
if (!Reg)
continue;
DEBUG(dbgs() << "Opd" << OpIdx << '\n');
LLVM_DEBUG(dbgs() << "Opd" << OpIdx << '\n');
const RegisterBankInfo::ValueMapping &ValMapping =
InstrMapping.getOperandMapping(OpIdx);
// If Reg is already properly mapped, this is free.
bool Assign;
if (assignmentMatch(Reg, ValMapping, Assign)) {
DEBUG(dbgs() << "=> is free (match).\n");
LLVM_DEBUG(dbgs() << "=> is free (match).\n");
continue;
}
if (Assign) {
DEBUG(dbgs() << "=> is free (simple assignment).\n");
LLVM_DEBUG(dbgs() << "=> is free (simple assignment).\n");
RepairPts.emplace_back(RepairingPlacement(MI, OpIdx, *TRI, *this,
RepairingPlacement::Reassign));
continue;
@ -447,7 +447,7 @@ RegBankSelect::MappingCost RegBankSelect::computeMapping(
// Check that the materialization of the repairing is possible.
if (!RepairPt.canMaterialize()) {
DEBUG(dbgs() << "Mapping involves impossible repairing\n");
LLVM_DEBUG(dbgs() << "Mapping involves impossible repairing\n");
return MappingCost::ImpossibleCost();
}
@ -510,7 +510,7 @@ RegBankSelect::MappingCost RegBankSelect::computeMapping(
// Stop looking into what it takes to repair, this is already
// too expensive.
if (BestCost && Cost > *BestCost) {
DEBUG(dbgs() << "Mapping is too expensive, stop processing\n");
LLVM_DEBUG(dbgs() << "Mapping is too expensive, stop processing\n");
return Cost;
}
@ -520,7 +520,7 @@ RegBankSelect::MappingCost RegBankSelect::computeMapping(
break;
}
}
DEBUG(dbgs() << "Total cost is: " << Cost << "\n");
LLVM_DEBUG(dbgs() << "Total cost is: " << Cost << "\n");
return Cost;
}
@ -560,14 +560,14 @@ bool RegBankSelect::applyMapping(
}
// Second, rewrite the instruction.
DEBUG(dbgs() << "Actual mapping of the operands: " << OpdMapper << '\n');
LLVM_DEBUG(dbgs() << "Actual mapping of the operands: " << OpdMapper << '\n');
RBI->applyMapping(OpdMapper);
return true;
}
bool RegBankSelect::assignInstr(MachineInstr &MI) {
DEBUG(dbgs() << "Assign: " << MI);
LLVM_DEBUG(dbgs() << "Assign: " << MI);
// Remember the repairing placement for all the operands.
SmallVector<RepairingPlacement, 4> RepairPts;
@ -588,7 +588,7 @@ bool RegBankSelect::assignInstr(MachineInstr &MI) {
// Make sure the mapping is valid for MI.
assert(BestMapping->verify(MI) && "Invalid instruction mapping");
DEBUG(dbgs() << "Best Mapping: " << *BestMapping << '\n');
LLVM_DEBUG(dbgs() << "Best Mapping: " << *BestMapping << '\n');
// After this call, MI may not be valid anymore.
// Do not use it.
@ -601,7 +601,7 @@ bool RegBankSelect::runOnMachineFunction(MachineFunction &MF) {
MachineFunctionProperties::Property::FailedISel))
return false;
DEBUG(dbgs() << "Assign register banks for: " << MF.getName() << '\n');
LLVM_DEBUG(dbgs() << "Assign register banks for: " << MF.getName() << '\n');
const Function &F = MF.getFunction();
Mode SaveOptMode = OptMode;
if (F.hasFnAttribute(Attribute::OptimizeNone))

22
llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
View File

@ -73,7 +73,7 @@ bool RegisterBankInfo::verify(const TargetRegisterInfo &TRI) const {
const RegisterBank &RegBank = getRegBank(Idx);
assert(Idx == RegBank.getID() &&
"ID does not match the index in the array");
DEBUG(dbgs() << "Verify " << RegBank << '\n');
LLVM_DEBUG(dbgs() << "Verify " << RegBank << '\n');
assert(RegBank.verify(TRI) && "RegBank is invalid");
}
#endif // NDEBUG
@ -404,18 +404,18 @@ RegisterBankInfo::getInstrAlternativeMappings(const MachineInstr &MI) const {
void RegisterBankInfo::applyDefaultMapping(const OperandsMapper &OpdMapper) {
MachineInstr &MI = OpdMapper.getMI();
MachineRegisterInfo &MRI = OpdMapper.getMRI();
DEBUG(dbgs() << "Applying default-like mapping\n");
LLVM_DEBUG(dbgs() << "Applying default-like mapping\n");
for (unsigned OpIdx = 0,
EndIdx = OpdMapper.getInstrMapping().getNumOperands();
OpIdx != EndIdx; ++OpIdx) {
DEBUG(dbgs() << "OpIdx " << OpIdx);
LLVM_DEBUG(dbgs() << "OpIdx " << OpIdx);
MachineOperand &MO = MI.getOperand(OpIdx);
if (!MO.isReg()) {
DEBUG(dbgs() << " is not a register, nothing to be done\n");
LLVM_DEBUG(dbgs() << " is not a register, nothing to be done\n");
continue;
}
if (!MO.getReg()) {
DEBUG(dbgs() << " is %%noreg, nothing to be done\n");
LLVM_DEBUG(dbgs() << " is %%noreg, nothing to be done\n");
continue;
}
assert(OpdMapper.getInstrMapping().getOperandMapping(OpIdx).NumBreakDowns !=
@ -427,14 +427,14 @@ void RegisterBankInfo::applyDefaultMapping(const OperandsMapper &OpdMapper) {
iterator_range<SmallVectorImpl<unsigned>::const_iterator> NewRegs =
OpdMapper.getVRegs(OpIdx);
if (NewRegs.begin() == NewRegs.end()) {
DEBUG(dbgs() << " has not been repaired, nothing to be done\n");
LLVM_DEBUG(dbgs() << " has not been repaired, nothing to be done\n");
continue;
}
unsigned OrigReg = MO.getReg();
unsigned NewReg = *NewRegs.begin();
DEBUG(dbgs() << " changed, replace " << printReg(OrigReg, nullptr));
LLVM_DEBUG(dbgs() << " changed, replace " << printReg(OrigReg, nullptr));
MO.setReg(NewReg);
DEBUG(dbgs() << " with " << printReg(NewReg, nullptr));
LLVM_DEBUG(dbgs() << " with " << printReg(NewReg, nullptr));
// The OperandsMapper creates plain scalar, we may have to fix that.
// Check if the types match and if not, fix that.
@ -448,11 +448,11 @@ void RegisterBankInfo::applyDefaultMapping(const OperandsMapper &OpdMapper) {
assert(OrigTy.getSizeInBits() <= NewTy.getSizeInBits() &&
"Types with difference size cannot be handled by the default "
"mapping");
DEBUG(dbgs() << "\nChange type of new opd from " << NewTy << " to "
<< OrigTy);
LLVM_DEBUG(dbgs() << "\nChange type of new opd from " << NewTy << " to "
<< OrigTy);
MRI.setType(NewReg, OrigTy);
}
DEBUG(dbgs() << '\n');
LLVM_DEBUG(dbgs() << '\n');
}
}

2
llvm/lib/CodeGen/GlobalISel/Utils.cpp
View File

@ -101,7 +101,7 @@ bool llvm::constrainSelectedInstRegOperands(MachineInstr &I,
if (!MO.isReg())
continue;
DEBUG(dbgs() << "Converting operand: " << MO << '\n');
LLVM_DEBUG(dbgs() << "Converting operand: " << MO << '\n');
assert(MO.isReg() && "Unsupported non-reg operand");
unsigned Reg = MO.getReg();

4
llvm/lib/CodeGen/GlobalMerge.cpp
View File

@ -442,8 +442,8 @@ bool GlobalMerge::doMerge(const SmallVectorImpl<GlobalVariable *> &Globals,
Type *Int32Ty = Type::getInt32Ty(M.getContext());
auto &DL = M.getDataLayout();
DEBUG(dbgs() << " Trying to merge set, starts with #"
<< GlobalSet.find_first() << "\n");
LLVM_DEBUG(dbgs() << " Trying to merge set, starts with #"
<< GlobalSet.find_first() << "\n");
ssize_t i = GlobalSet.find_first();
while (i != -1) {

53
llvm/lib/CodeGen/IfConversion.cpp
View File

@ -361,14 +361,14 @@ bool IfConverter::runOnMachineFunction(MachineFunction &MF) {
getAnalysisIfAvailable<MachineModuleInfo>());
}
DEBUG(dbgs() << "\nIfcvt: function (" << ++FnNum << ") \'"
<< MF.getName() << "\'");
LLVM_DEBUG(dbgs() << "\nIfcvt: function (" << ++FnNum << ") \'"
<< MF.getName() << "\'");
if (FnNum < IfCvtFnStart || (IfCvtFnStop != -1 && FnNum > IfCvtFnStop)) {
DEBUG(dbgs() << " skipped\n");
LLVM_DEBUG(dbgs() << " skipped\n");
return false;
}
DEBUG(dbgs() << "\n");
LLVM_DEBUG(dbgs() << "\n");
MF.RenumberBlocks();
BBAnalysis.resize(MF.getNumBlockIDs());
@ -406,14 +406,14 @@ bool IfConverter::runOnMachineFunction(MachineFunction &MF) {
case ICSimpleFalse: {
bool isFalse = Kind == ICSimpleFalse;
if ((isFalse && DisableSimpleF) || (!isFalse && DisableSimple)) break;
DEBUG(dbgs() << "Ifcvt (Simple"
<< (Kind == ICSimpleFalse ? " false" : "")
<< "): " << printMBBReference(*BBI.BB) << " ("
<< ((Kind == ICSimpleFalse) ? BBI.FalseBB->getNumber()
: BBI.TrueBB->getNumber())
<< ") ");
LLVM_DEBUG(dbgs() << "Ifcvt (Simple"
<< (Kind == ICSimpleFalse ? " false" : "")
<< "): " << printMBBReference(*BBI.BB) << " ("
<< ((Kind == ICSimpleFalse) ? BBI.FalseBB->getNumber()
: BBI.TrueBB->getNumber())
<< ") ");
RetVal = IfConvertSimple(BBI, Kind);
DEBUG(dbgs() << (RetVal ? "succeeded!" : "failed!") << "\n");
LLVM_DEBUG(dbgs() << (RetVal ? "succeeded!" : "failed!") << "\n");
if (RetVal) {
if (isFalse) ++NumSimpleFalse;
else ++NumSimple;
@ -430,16 +430,16 @@ bool IfConverter::runOnMachineFunction(MachineFunction &MF) {
if (DisableTriangleR && !isFalse && isRev) break;
if (DisableTriangleF && isFalse && !isRev) break;
if (DisableTriangleFR && isFalse && isRev) break;
DEBUG(dbgs() << "Ifcvt (Triangle");
LLVM_DEBUG(dbgs() << "Ifcvt (Triangle");
if (isFalse)
DEBUG(dbgs() << " false");
LLVM_DEBUG(dbgs() << " false");
if (isRev)
DEBUG(dbgs() << " rev");
DEBUG(dbgs() << "): " << printMBBReference(*BBI.BB)
<< " (T:" << BBI.TrueBB->getNumber()
<< ",F:" << BBI.FalseBB->getNumber() << ") ");
LLVM_DEBUG(dbgs() << " rev");
LLVM_DEBUG(dbgs() << "): " << printMBBReference(*BBI.BB)
<< " (T:" << BBI.TrueBB->getNumber()
<< ",F:" << BBI.FalseBB->getNumber() << ") ");
RetVal = IfConvertTriangle(BBI, Kind);
DEBUG(dbgs() << (RetVal ? "succeeded!" : "failed!") << "\n");
LLVM_DEBUG(dbgs() << (RetVal ? "succeeded!" : "failed!") << "\n");
if (RetVal) {
if (isFalse) {
if (isRev) ++NumTriangleFRev;
@ -453,24 +453,25 @@ bool IfConverter::runOnMachineFunction(MachineFunction &MF) {
}
case ICDiamond:
if (DisableDiamond) break;
DEBUG(dbgs() << "Ifcvt (Diamond): " << printMBBReference(*BBI.BB)
<< " (T:" << BBI.TrueBB->getNumber()
<< ",F:" << BBI.FalseBB->getNumber() << ") ");
LLVM_DEBUG(dbgs() << "Ifcvt (Diamond): " << printMBBReference(*BBI.BB)
<< " (T:" << BBI.TrueBB->getNumber()
<< ",F:" << BBI.FalseBB->getNumber() << ") ");
RetVal = IfConvertDiamond(BBI, Kind, NumDups, NumDups2,
Token->TClobbersPred,
Token->FClobbersPred);
DEBUG(dbgs() << (RetVal ? "succeeded!" : "failed!") << "\n");
LLVM_DEBUG(dbgs() << (RetVal ? "succeeded!" : "failed!") << "\n");
if (RetVal) ++NumDiamonds;
break;
case ICForkedDiamond:
if (DisableForkedDiamond) break;
DEBUG(dbgs() << "Ifcvt (Forked Diamond): " << printMBBReference(*BBI.BB)
<< " (T:" << BBI.TrueBB->getNumber()
<< ",F:" << BBI.FalseBB->getNumber() << ") ");
LLVM_DEBUG(dbgs() << "Ifcvt (Forked Diamond): "
<< printMBBReference(*BBI.BB)
<< " (T:" << BBI.TrueBB->getNumber()
<< ",F:" << BBI.FalseBB->getNumber() << ") ");
RetVal = IfConvertForkedDiamond(BBI, Kind, NumDups, NumDups2,
Token->TClobbersPred,
Token->FClobbersPred);
DEBUG(dbgs() << (RetVal ? "succeeded!" : "failed!") << "\n");
LLVM_DEBUG(dbgs() << (RetVal ? "succeeded!" : "failed!") << "\n");
if (RetVal) ++NumForkedDiamonds;
break;
}

83
llvm/lib/CodeGen/InlineSpiller.cpp
View File

@ -336,7 +336,7 @@ void InlineSpiller::collectRegsToSpill() {
if (isRegToSpill(SnipReg))
continue;
RegsToSpill.push_back(SnipReg);
DEBUG(dbgs() << "\talso spill snippet " << SnipLI << '\n');
LLVM_DEBUG(dbgs() << "\talso spill snippet " << SnipLI << '\n');
++NumSnippets;
}
}
@ -388,8 +388,8 @@ bool InlineSpiller::hoistSpillInsideBB(LiveInterval &SpillLI,
LiveInterval &OrigLI = LIS.getInterval(Original);
VNInfo *OrigVNI = OrigLI.getVNInfoAt(Idx);
StackInt->MergeValueInAsValue(OrigLI, OrigVNI, StackInt->getValNumInfo(0));
DEBUG(dbgs() << "\tmerged orig valno " << OrigVNI->id << ": "
<< *StackInt << '\n');
LLVM_DEBUG(dbgs() << "\tmerged orig valno " << OrigVNI->id << ": "
<< *StackInt << '\n');
// We are going to spill SrcVNI immediately after its def, so clear out
// any later spills of the same value.
@ -410,7 +410,7 @@ bool InlineSpiller::hoistSpillInsideBB(LiveInterval &SpillLI,
MRI.getRegClass(SrcReg), &TRI);
--MII; // Point to store instruction.
LIS.InsertMachineInstrInMaps(*MII);
DEBUG(dbgs() << "\thoisted: " << SrcVNI->def << '\t' << *MII);
LLVM_DEBUG(dbgs() << "\thoisted: " << SrcVNI->def << '\t' << *MII);
HSpiller.addToMergeableSpills(*MII, StackSlot, Original);
++NumSpills;
@ -429,8 +429,8 @@ void InlineSpiller::eliminateRedundantSpills(LiveInterval &SLI, VNInfo *VNI) {
LiveInterval *LI;
std::tie(LI, VNI) = WorkList.pop_back_val();
unsigned Reg = LI->reg;
DEBUG(dbgs() << "Checking redundant spills for "
<< VNI->id << '@' << VNI->def << " in " << *LI << '\n');
LLVM_DEBUG(dbgs() << "Checking redundant spills for " << VNI->id << '@'
<< VNI->def << " in " << *LI << '\n');
// Regs to spill are taken care of.
if (isRegToSpill(Reg))
@ -438,7 +438,7 @@ void InlineSpiller::eliminateRedundantSpills(LiveInterval &SLI, VNInfo *VNI) {
// Add all of VNI's live range to StackInt.
StackInt->MergeValueInAsValue(*LI, VNI, StackInt->getValNumInfo(0));
DEBUG(dbgs() << "Merged to stack int: " << *StackInt << '\n');
LLVM_DEBUG(dbgs() << "Merged to stack int: " << *StackInt << '\n');
// Find all spills and copies of VNI.
for (MachineRegisterInfo::use_instr_nodbg_iterator
@ -466,7 +466,7 @@ void InlineSpiller::eliminateRedundantSpills(LiveInterval &SLI, VNInfo *VNI) {
// Erase spills.
int FI;
if (Reg == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot) {
DEBUG(dbgs() << "Redundant spill " << Idx << '\t' << MI);
LLVM_DEBUG(dbgs() << "Redundant spill " << Idx << '\t' << MI);
// eliminateDeadDefs won't normally remove stores, so switch opcode.
MI.setDesc(TII.get(TargetOpcode::KILL));
DeadDefs.push_back(&MI);
@ -528,13 +528,13 @@ bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg, MachineInstr &MI) {
VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx.getBaseIndex());
if (!ParentVNI) {
DEBUG(dbgs() << "\tadding <undef> flags: ");
LLVM_DEBUG(dbgs() << "\tadding <undef> flags: ");
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI.getOperand(i);
if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg)
MO.setIsUndef();
}
DEBUG(dbgs() << UseIdx << '\t' << MI);
LLVM_DEBUG(dbgs() << UseIdx << '\t' << MI);
return true;
}
@ -548,7 +548,7 @@ bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg, MachineInstr &MI) {
if (!Edit->canRematerializeAt(RM, OrigVNI, UseIdx, false)) {
markValueUsed(&VirtReg, ParentVNI);
DEBUG(dbgs() << "\tcannot remat for " << UseIdx << '\t' << MI);
LLVM_DEBUG(dbgs() << "\tcannot remat for " << UseIdx << '\t' << MI);
return false;
}
@ -556,7 +556,7 @@ bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg, MachineInstr &MI) {
// same register for uses and defs.
if (RI.Tied) {
markValueUsed(&VirtReg, ParentVNI);
DEBUG(dbgs() << "\tcannot remat tied reg: " << UseIdx << '\t' << MI);
LLVM_DEBUG(dbgs() << "\tcannot remat tied reg: " << UseIdx << '\t' << MI);
return false;
}
@ -582,8 +582,8 @@ bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg, MachineInstr &MI) {
NewMI->setDebugLoc(MI.getDebugLoc());
(void)DefIdx;
DEBUG(dbgs() << "\tremat: " << DefIdx << '\t'
<< *LIS.getInstructionFromIndex(DefIdx));
LLVM_DEBUG(dbgs() << "\tremat: " << DefIdx << '\t'
<< *LIS.getInstructionFromIndex(DefIdx));
// Replace operands
for (const auto &OpPair : Ops) {
@ -593,7 +593,7 @@ bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg, MachineInstr &MI) {
MO.setIsKill();
}
}
DEBUG(dbgs() << "\t " << UseIdx << '\t' << MI << '\n');
LLVM_DEBUG(dbgs() << "\t " << UseIdx << '\t' << MI << '\n');
++NumRemats;
return true;
@ -638,7 +638,7 @@ void InlineSpiller::reMaterializeAll() {
MI->addRegisterDead(Reg, &TRI);
if (!MI->allDefsAreDead())
continue;
DEBUG(dbgs() << "All defs dead: " << *MI);
LLVM_DEBUG(dbgs() << "All defs dead: " << *MI);
DeadDefs.push_back(MI);
}
}
@ -647,7 +647,7 @@ void InlineSpiller::reMaterializeAll() {
// deleted here.
if (DeadDefs.empty())
return;
DEBUG(dbgs() << "Remat created " << DeadDefs.size() << " dead defs.\n");
LLVM_DEBUG(dbgs() << "Remat created " << DeadDefs.size() << " dead defs.\n");
Edit->eliminateDeadDefs(DeadDefs, RegsToSpill, AA);
// LiveRangeEdit::eliminateDeadDef is used to remove dead define instructions
@ -670,7 +670,8 @@ void InlineSpiller::reMaterializeAll() {
RegsToSpill[ResultPos++] = Reg;
}
RegsToSpill.erase(RegsToSpill.begin() + ResultPos, RegsToSpill.end());
DEBUG(dbgs() << RegsToSpill.size() << " registers to spill after remat.\n");
LLVM_DEBUG(dbgs() << RegsToSpill.size()
<< " registers to spill after remat.\n");
}
//===----------------------------------------------------------------------===//
@ -692,7 +693,7 @@ bool InlineSpiller::coalesceStackAccess(MachineInstr *MI, unsigned Reg) {
if (!IsLoad)
HSpiller.rmFromMergeableSpills(*MI, StackSlot);
DEBUG(dbgs() << "Coalescing stack access: " << *MI);
LLVM_DEBUG(dbgs() << "Coalescing stack access: " << *MI);
LIS.RemoveMachineInstrFromMaps(*MI);
MI->eraseFromParent();
@ -849,8 +850,8 @@ foldMemoryOperand(ArrayRef<std::pair<MachineInstr *, unsigned>> Ops,
FoldMI->RemoveOperand(i - 1);
}
DEBUG(dumpMachineInstrRangeWithSlotIndex(MIS.begin(), MIS.end(), LIS,
"folded"));
LLVM_DEBUG(dumpMachineInstrRangeWithSlotIndex(MIS.begin(), MIS.end(), LIS,
"folded"));
if (!WasCopy)
++NumFolded;
@ -873,8 +874,8 @@ void InlineSpiller::insertReload(unsigned NewVReg,
LIS.InsertMachineInstrRangeInMaps(MIS.begin(), MI);
DEBUG(dumpMachineInstrRangeWithSlotIndex(MIS.begin(), MI, LIS, "reload",
NewVReg));
LLVM_DEBUG(dumpMachineInstrRangeWithSlotIndex(MIS.begin(), MI, LIS, "reload",
NewVReg));
++NumReloads;
}
@ -913,8 +914,8 @@ void InlineSpiller::insertSpill(unsigned NewVReg, bool isKill,
LIS.InsertMachineInstrRangeInMaps(std::next(MI), MIS.end());
DEBUG(dumpMachineInstrRangeWithSlotIndex(std::next(MI), MIS.end(), LIS,
"spill"));
LLVM_DEBUG(dumpMachineInstrRangeWithSlotIndex(std::next(MI), MIS.end(), LIS,
"spill"));
++NumSpills;
if (IsRealSpill)
HSpiller.addToMergeableSpills(*std::next(MI), StackSlot, Original);
@ -922,7 +923,7 @@ void InlineSpiller::insertSpill(unsigned NewVReg, bool isKill,
/// spillAroundUses - insert spill code around each use of Reg.
void InlineSpiller::spillAroundUses(unsigned Reg) {
DEBUG(dbgs() << "spillAroundUses " << printReg(Reg) << '\n');
LLVM_DEBUG(dbgs() << "spillAroundUses " << printReg(Reg) << '\n');
LiveInterval &OldLI = LIS.getInterval(Reg);
// Iterate over instructions using Reg.
@ -935,7 +936,7 @@ void InlineSpiller::spillAroundUses(unsigned Reg) {
if (MI->isDebugInstr()) {
// Modify DBG_VALUE now that the value is in a spill slot.
MachineBasicBlock *MBB = MI->getParent();
DEBUG(dbgs() << "Modifying debug info due to spill:\t" << *MI);
LLVM_DEBUG(dbgs() << "Modifying debug info due to spill:\t" << *MI);
buildDbgValueForSpill(*MBB, MI, *MI, StackSlot);
MBB->erase(MI);
continue;
@ -966,7 +967,7 @@ void InlineSpiller::spillAroundUses(unsigned Reg) {
if (SibReg && isSibling(SibReg)) {
// This may actually be a copy between snippets.
if (isRegToSpill(SibReg)) {
DEBUG(dbgs() << "Found new snippet copy: " << *MI);
LLVM_DEBUG(dbgs() << "Found new snippet copy: " << *MI);
SnippetCopies.insert(MI);
continue;
}
@ -1009,7 +1010,7 @@ void InlineSpiller::spillAroundUses(unsigned Reg) {
hasLiveDef = true;
}
}
DEBUG(dbgs() << "\trewrite: " << Idx << '\t' << *MI << '\n');
LLVM_DEBUG(dbgs() << "\trewrite: " << Idx << '\t' << *MI << '\n');
// FIXME: Use a second vreg if instruction has no tied ops.
if (RI.Writes)
@ -1035,7 +1036,7 @@ void InlineSpiller::spillAll() {
for (unsigned Reg : RegsToSpill)
StackInt->MergeSegmentsInAsValue(LIS.getInterval(Reg),
StackInt->getValNumInfo(0));
DEBUG(dbgs() << "Merged spilled regs: " << *StackInt << '\n');
LLVM_DEBUG(dbgs() << "Merged spilled regs: " << *StackInt << '\n');
// Spill around uses of all RegsToSpill.
for (unsigned Reg : RegsToSpill)
@ -1043,7 +1044,7 @@ void InlineSpiller::spillAll() {
// Hoisted spills may cause dead code.
if (!DeadDefs.empty()) {
DEBUG(dbgs() << "Eliminating " << DeadDefs.size() << " dead defs\n");
LLVM_DEBUG(dbgs() << "Eliminating " << DeadDefs.size() << " dead defs\n");
Edit->eliminateDeadDefs(DeadDefs, RegsToSpill, AA);
}
@ -1075,10 +1076,10 @@ void InlineSpiller::spill(LiveRangeEdit &edit) {
StackSlot = VRM.getStackSlot(Original);
StackInt = nullptr;
DEBUG(dbgs() << "Inline spilling "
<< TRI.getRegClassName(MRI.getRegClass(edit.getReg()))
<< ':' << edit.getParent()
<< "\nFrom original " << printReg(Original) << '\n');
LLVM_DEBUG(dbgs() << "Inline spilling "
<< TRI.getRegClassName(MRI.getRegClass(edit.getReg()))
<< ':' << edit.getParent() << "\nFrom original "
<< printReg(Original) << '\n');
assert(edit.getParent().isSpillable() &&
"Attempting to spill already spilled value.");
assert(DeadDefs.empty() && "Previous spill didn't remove dead defs");
@ -1262,11 +1263,11 @@ void HoistSpillHelper::getVisitOrders(
"Orders have different size with WorkSet");
#ifndef NDEBUG
DEBUG(dbgs() << "Orders size is " << Orders.size() << "\n");
LLVM_DEBUG(dbgs() << "Orders size is " << Orders.size() << "\n");
SmallVector<MachineDomTreeNode *, 32>::reverse_iterator RIt = Orders.rbegin();
for (; RIt != Orders.rend(); RIt++)
DEBUG(dbgs() << "BB" << (*RIt)->getBlock()->getNumber() << ",");
DEBUG(dbgs() << "\n");
LLVM_DEBUG(dbgs() << "BB" << (*RIt)->getBlock()->getNumber() << ",");
LLVM_DEBUG(dbgs() << "\n");
#endif
}
@ -1375,7 +1376,7 @@ void HoistSpillHelper::runHoistSpills(
// Current Block is the BB containing the new hoisted spill. Add it to
// SpillsToKeep. LiveReg is the source of the new spill.
SpillsToKeep[*RIt] = LiveReg;
DEBUG({
LLVM_DEBUG({
dbgs() << "spills in BB: ";
for (const auto Rspill : SpillsInSubTree)
dbgs() << Rspill->getBlock()->getNumber() << " ";
@ -1431,7 +1432,7 @@ void HoistSpillHelper::hoistAllSpills() {
if (Ent.second.empty())
continue;
DEBUG({
LLVM_DEBUG({
dbgs() << "\nFor Slot" << Slot << " and VN" << OrigVNI->id << ":\n"
<< "Equal spills in BB: ";
for (const auto spill : EqValSpills)
@ -1446,7 +1447,7 @@ void HoistSpillHelper::hoistAllSpills() {
runHoistSpills(OrigLI, *OrigVNI, EqValSpills, SpillsToRm, SpillsToIns);
DEBUG({
LLVM_DEBUG({
dbgs() << "Finally inserted spills in BB: ";
for (const auto Ispill : SpillsToIns)
dbgs() << Ispill.first->getNumber() << " ";

6
llvm/lib/CodeGen/InterleavedAccessPass.cpp
View File

@ -332,7 +332,7 @@ bool InterleavedAccess::lowerInterleavedLoad(
if (!tryReplaceExtracts(Extracts, Shuffles))
return false;
DEBUG(dbgs() << "IA: Found an interleaved load: " << *LI << "\n");
LLVM_DEBUG(dbgs() << "IA: Found an interleaved load: " << *LI << "\n");
// Try to create target specific intrinsics to replace the load and shuffles.
if (!TLI->lowerInterleavedLoad(LI, Shuffles, Indices, Factor))
@ -424,7 +424,7 @@ bool InterleavedAccess::lowerInterleavedStore(
if (!isReInterleaveMask(SVI->getShuffleMask(), Factor, MaxFactor, OpNumElts))
return false;
DEBUG(dbgs() << "IA: Found an interleaved store: " << *SI << "\n");
LLVM_DEBUG(dbgs() << "IA: Found an interleaved store: " << *SI << "\n");
// Try to create target specific intrinsics to replace the store and shuffle.
if (!TLI->lowerInterleavedStore(SI, SVI, Factor))
@ -441,7 +441,7 @@ bool InterleavedAccess::runOnFunction(Function &F) {
if (!TPC || !LowerInterleavedAccesses)
return false;
DEBUG(dbgs() << "*** " << getPassName() << ": " << F.getName() << "\n");
LLVM_DEBUG(dbgs() << "*** " << getPassName() << ": " << F.getName() << "\n");
DT = &getAnalysis<DominatorTreeWrapperPass>().getDomTree();
auto &TM = TPC->getTM<TargetMachine>();

12
llvm/lib/CodeGen/LazyMachineBlockFrequencyInfo.cpp
View File

@ -57,23 +57,23 @@ MachineBlockFrequencyInfo &
LazyMachineBlockFrequencyInfoPass::calculateIfNotAvailable() const {
auto *MBFI = getAnalysisIfAvailable<MachineBlockFrequencyInfo>();
if (MBFI) {
DEBUG(dbgs() << "MachineBlockFrequencyInfo is available\n");
LLVM_DEBUG(dbgs() << "MachineBlockFrequencyInfo is available\n");
return *MBFI;
}
auto &MBPI = getAnalysis<MachineBranchProbabilityInfo>();
auto *MLI = getAnalysisIfAvailable<MachineLoopInfo>();
auto *MDT = getAnalysisIfAvailable<MachineDominatorTree>();
DEBUG(dbgs() << "Building MachineBlockFrequencyInfo on the fly\n");
DEBUG(if (MLI) dbgs() << "LoopInfo is available\n");
LLVM_DEBUG(dbgs() << "Building MachineBlockFrequencyInfo on the fly\n");
LLVM_DEBUG(if (MLI) dbgs() << "LoopInfo is available\n");
if (!MLI) {
DEBUG(dbgs() << "Building LoopInfo on the fly\n");
LLVM_DEBUG(dbgs() << "Building LoopInfo on the fly\n");
// First create a dominator tree.
DEBUG(if (MDT) dbgs() << "DominatorTree is available\n");
LLVM_DEBUG(if (MDT) dbgs() << "DominatorTree is available\n");
if (!MDT) {
DEBUG(dbgs() << "Building DominatorTree on the fly\n");
LLVM_DEBUG(dbgs() << "Building DominatorTree on the fly\n");
OwnedMDT = make_unique<MachineDominatorTree>();
OwnedMDT->getBase().recalculate(*MF);
MDT = OwnedMDT.get();

42
llvm/lib/CodeGen/LiveDebugValues.cpp
View File

@ -480,8 +480,8 @@ void LiveDebugValues::transferSpillInst(MachineInstr &MI,
// Check if the register is the location of a debug value.
for (unsigned ID : OpenRanges.getVarLocs()) {
if (VarLocIDs[ID].isDescribedByReg() == Reg) {
DEBUG(dbgs() << "Spilling Register " << printReg(Reg, TRI) << '('
<< VarLocIDs[ID].Var.getVar()->getName() << ")\n");
LLVM_DEBUG(dbgs() << "Spilling Register " << printReg(Reg, TRI) << '('
<< VarLocIDs[ID].Var.getVar()->getName() << ")\n");
// Create a DBG_VALUE instruction to describe the Var in its spilled
// location, but don't insert it yet to avoid invalidating the
@ -494,8 +494,8 @@ void LiveDebugValues::transferSpillInst(MachineInstr &MI,
MachineInstr *SpDMI =
BuildMI(*MF, DMI->getDebugLoc(), DMI->getDesc(), true, SpillBase,
DMI->getDebugVariable(), SpillExpr);
DEBUG(dbgs() << "Creating DBG_VALUE inst for spill: ";
SpDMI->print(dbgs(), false, TII));
LLVM_DEBUG(dbgs() << "Creating DBG_VALUE inst for spill: ";
SpDMI->print(dbgs(), false, TII));
// The newly created DBG_VALUE instruction SpDMI must be inserted after
// MI. Keep track of the pairing.
@ -527,10 +527,12 @@ bool LiveDebugValues::transferTerminatorInst(MachineInstr &MI,
if (OpenRanges.empty())
return false;
DEBUG(for (unsigned ID : OpenRanges.getVarLocs()) {
// Copy OpenRanges to OutLocs, if not already present.
dbgs() << "Add to OutLocs: "; VarLocIDs[ID].dump();
});
LLVM_DEBUG(for (unsigned ID
: OpenRanges.getVarLocs()) {
// Copy OpenRanges to OutLocs, if not already present.
dbgs() << "Add to OutLocs: ";
VarLocIDs[ID].dump();
});
VarLocSet &VLS = OutLocs[CurMBB];
Changed = VLS |= OpenRanges.getVarLocs();
OpenRanges.clear();
@ -556,7 +558,7 @@ bool LiveDebugValues::transfer(MachineInstr &MI, OpenRangesSet &OpenRanges,
bool LiveDebugValues::join(MachineBasicBlock &MBB, VarLocInMBB &OutLocs,
VarLocInMBB &InLocs, const VarLocMap &VarLocIDs,
SmallPtrSet<const MachineBasicBlock *, 16> &Visited) {
DEBUG(dbgs() << "join MBB: " << MBB.getName() << "\n");
LLVM_DEBUG(dbgs() << "join MBB: " << MBB.getName() << "\n");
bool Changed = false;
VarLocSet InLocsT; // Temporary incoming locations.
@ -616,7 +618,7 @@ bool LiveDebugValues::join(MachineBasicBlock &MBB, VarLocInMBB &OutLocs,
DMI->getDebugVariable(), DMI->getDebugExpression());
if (DMI->isIndirectDebugValue())
MI->getOperand(1).setImm(DMI->getOperand(1).getImm());
DEBUG(dbgs() << "Inserted: "; MI->dump(););
LLVM_DEBUG(dbgs() << "Inserted: "; MI->dump(););
ILS.set(ID);
++NumInserted;
Changed = true;
@ -627,7 +629,7 @@ bool LiveDebugValues::join(MachineBasicBlock &MBB, VarLocInMBB &OutLocs,
/// Calculate the liveness information for the given machine function and
/// extend ranges across basic blocks.
bool LiveDebugValues::ExtendRanges(MachineFunction &MF) {
DEBUG(dbgs() << "\nDebug Range Extension\n");
LLVM_DEBUG(dbgs() << "\nDebug Range Extension\n");
bool Changed = false;
bool OLChanged = false;
@ -658,8 +660,8 @@ bool LiveDebugValues::ExtendRanges(MachineFunction &MF) {
transfer(MI, OpenRanges, OutLocs, VarLocIDs, Spills,
/*transferSpills=*/false);
DEBUG(printVarLocInMBB(MF, OutLocs, VarLocIDs, "OutLocs after initialization",
dbgs()));
LLVM_DEBUG(printVarLocInMBB(MF, OutLocs, VarLocIDs,
"OutLocs after initialization", dbgs()));
ReversePostOrderTraversal<MachineFunction *> RPOT(&MF);
unsigned int RPONumber = 0;
@ -679,7 +681,7 @@ bool LiveDebugValues::ExtendRanges(MachineFunction &MF) {
// thing twice. We could avoid this with a custom priority queue, but this
// is probably not worth it.
SmallPtrSet<MachineBasicBlock *, 16> OnPending;
DEBUG(dbgs() << "Processing Worklist\n");
LLVM_DEBUG(dbgs() << "Processing Worklist\n");
while (!Worklist.empty()) {
MachineBasicBlock *MBB = OrderToBB[Worklist.top()];
Worklist.pop();
@ -701,10 +703,10 @@ bool LiveDebugValues::ExtendRanges(MachineFunction &MF) {
SP.DebugInst);
Spills.clear();
DEBUG(printVarLocInMBB(MF, OutLocs, VarLocIDs,
"OutLocs after propagating", dbgs()));
DEBUG(printVarLocInMBB(MF, InLocs, VarLocIDs,
"InLocs after propagating", dbgs()));
LLVM_DEBUG(printVarLocInMBB(MF, OutLocs, VarLocIDs,
"OutLocs after propagating", dbgs()));
LLVM_DEBUG(printVarLocInMBB(MF, InLocs, VarLocIDs,
"InLocs after propagating", dbgs()));
if (OLChanged) {
OLChanged = false;
@ -721,8 +723,8 @@ bool LiveDebugValues::ExtendRanges(MachineFunction &MF) {
assert(Pending.empty() && "Pending should be empty");
}
DEBUG(printVarLocInMBB(MF, OutLocs, VarLocIDs, "Final OutLocs", dbgs()));
DEBUG(printVarLocInMBB(MF, InLocs, VarLocIDs, "Final InLocs", dbgs()));
LLVM_DEBUG(printVarLocInMBB(MF, OutLocs, VarLocIDs, "Final OutLocs", dbgs()));
LLVM_DEBUG(printVarLocInMBB(MF, InLocs, VarLocIDs, "Final InLocs", dbgs()));
return Changed;
}

46
llvm/lib/CodeGen/LiveDebugVariables.cpp
View File

@ -511,7 +511,7 @@ bool LDVImpl::handleDebugValue(MachineInstr &MI, SlotIndex Idx) {
if (MI.getNumOperands() != 4 ||
!(MI.getOperand(1).isReg() || MI.getOperand(1).isImm()) ||
!MI.getOperand(2).isMetadata()) {
DEBUG(dbgs() << "Can't handle " << MI);
LLVM_DEBUG(dbgs() << "Can't handle " << MI);
return false;
}
@ -530,8 +530,8 @@ bool LDVImpl::handleDebugValue(MachineInstr &MI, SlotIndex Idx) {
// The DBG_VALUE is described by a virtual register that does not have a
// live interval. Discard the DBG_VALUE.
Discard = true;
DEBUG(dbgs() << "Discarding debug info (no LIS interval): "
<< Idx << " " << MI);
LLVM_DEBUG(dbgs() << "Discarding debug info (no LIS interval): " << Idx
<< " " << MI);
} else {
// The DBG_VALUE is only valid if either Reg is live out from Idx, or Reg
// is defined dead at Idx (where Idx is the slot index for the instruction
@ -542,8 +542,8 @@ bool LDVImpl::handleDebugValue(MachineInstr &MI, SlotIndex Idx) {
// We have found a DBG_VALUE with the value in a virtual register that
// is not live. Discard the DBG_VALUE.
Discard = true;
DEBUG(dbgs() << "Discarding debug info (reg not live): "
<< Idx << " " << MI);
LLVM_DEBUG(dbgs() << "Discarding debug info (reg not live): " << Idx
<< " " << MI);
}
}
}
@ -688,7 +688,8 @@ void UserValue::addDefsFromCopies(
if (CopyValues.empty())
return;
DEBUG(dbgs() << "Got " << CopyValues.size() << " copies of " << *LI << '\n');
LLVM_DEBUG(dbgs() << "Got " << CopyValues.size() << " copies of " << *LI
<< '\n');
// Try to add defs of the copied values for each kill point.
for (unsigned i = 0, e = Kills.size(); i != e; ++i) {
@ -702,8 +703,8 @@ void UserValue::addDefsFromCopies(
LocMap::iterator I = locInts.find(Idx);
if (I.valid() && I.start() <= Idx)
continue;
DEBUG(dbgs() << "Kill at " << Idx << " covered by valno #"
<< DstVNI->id << " in " << *DstLI << '\n');
LLVM_DEBUG(dbgs() << "Kill at " << Idx << " covered by valno #"
<< DstVNI->id << " in " << *DstLI << '\n');
MachineInstr *CopyMI = LIS.getInstructionFromIndex(DstVNI->def);
assert(CopyMI && CopyMI->isCopy() && "Bad copy value");
unsigned LocNo = getLocationNo(CopyMI->getOperand(0));
@ -851,12 +852,12 @@ bool LDVImpl::runOnMachineFunction(MachineFunction &mf) {
MF = &mf;
LIS = &pass.getAnalysis<LiveIntervals>();
TRI = mf.getSubtarget().getRegisterInfo();
DEBUG(dbgs() << "********** COMPUTING LIVE DEBUG VARIABLES: "
<< mf.getName() << " **********\n");
LLVM_DEBUG(dbgs() << "********** COMPUTING LIVE DEBUG VARIABLES: "
<< mf.getName() << " **********\n");
bool Changed = collectDebugValues(mf);
computeIntervals();
DEBUG(print(dbgs()));
LLVM_DEBUG(print(dbgs()));
ModifiedMF = Changed;
return Changed;
}
@ -902,7 +903,7 @@ LiveDebugVariables::~LiveDebugVariables() {
bool
UserValue::splitLocation(unsigned OldLocNo, ArrayRef<unsigned> NewRegs,
LiveIntervals& LIS) {
DEBUG({
LLVM_DEBUG({
dbgs() << "Splitting Loc" << OldLocNo << '\t';
print(dbgs(), nullptr);
});
@ -985,8 +986,8 @@ UserValue::splitLocation(unsigned OldLocNo, ArrayRef<unsigned> NewRegs,
while (LocMapI.valid()) {
DbgValueLocation v = LocMapI.value();
if (v.locNo() == OldLocNo) {
DEBUG(dbgs() << "Erasing [" << LocMapI.start() << ';'
<< LocMapI.stop() << ")\n");
LLVM_DEBUG(dbgs() << "Erasing [" << LocMapI.start() << ';'
<< LocMapI.stop() << ")\n");
LocMapI.erase();
} else {
if (v.locNo() > OldLocNo)
@ -995,7 +996,10 @@ UserValue::splitLocation(unsigned OldLocNo, ArrayRef<unsigned> NewRegs,
}
}
DEBUG({dbgs() << "Split result: \t"; print(dbgs(), nullptr);});
LLVM_DEBUG({
dbgs() << "Split result: \t";
print(dbgs(), nullptr);
});
return DidChange;
}
@ -1213,11 +1217,11 @@ void UserValue::emitDebugValues(VirtRegMap *VRM, LiveIntervals &LIS,
if (trimmedDefs.count(Start))
Start = Start.getPrevIndex();
DEBUG(dbgs() << "\t[" << Start << ';' << Stop << "):" << Loc.locNo());
LLVM_DEBUG(dbgs() << "\t[" << Start << ';' << Stop << "):" << Loc.locNo());
MachineFunction::iterator MBB = LIS.getMBBFromIndex(Start)->getIterator();
SlotIndex MBBEnd = LIS.getMBBEndIdx(&*MBB);
DEBUG(dbgs() << ' ' << printMBBReference(*MBB) << '-' << MBBEnd);
LLVM_DEBUG(dbgs() << ' ' << printMBBReference(*MBB) << '-' << MBBEnd);
insertDebugValue(&*MBB, Start, Stop, Loc, Spilled, LIS, TII, TRI);
// This interval may span multiple basic blocks.
// Insert a DBG_VALUE into each one.
@ -1227,10 +1231,10 @@ void UserValue::emitDebugValues(VirtRegMap *VRM, LiveIntervals &LIS,
if (++MBB == MFEnd)
break;
MBBEnd = LIS.getMBBEndIdx(&*MBB);
DEBUG(dbgs() << ' ' << printMBBReference(*MBB) << '-' << MBBEnd);
LLVM_DEBUG(dbgs() << ' ' << printMBBReference(*MBB) << '-' << MBBEnd);
insertDebugValue(&*MBB, Start, Stop, Loc, Spilled, LIS, TII, TRI);
}
DEBUG(dbgs() << '\n');
LLVM_DEBUG(dbgs() << '\n');
if (MBB == MFEnd)
break;
@ -1239,13 +1243,13 @@ void UserValue::emitDebugValues(VirtRegMap *VRM, LiveIntervals &LIS,
}
void LDVImpl::emitDebugValues(VirtRegMap *VRM) {
DEBUG(dbgs() << "********** EMITTING LIVE DEBUG VARIABLES **********\n");
LLVM_DEBUG(dbgs() << "********** EMITTING LIVE DEBUG VARIABLES **********\n");
if (!MF)
return;
const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
BitVector SpilledLocations;
for (unsigned i = 0, e = userValues.size(); i != e; ++i) {
DEBUG(userValues[i]->print(dbgs(), TRI));
LLVM_DEBUG(userValues[i]->print(dbgs(), TRI));
userValues[i]->rewriteLocations(*VRM, *TRI, SpilledLocations);
userValues[i]->emitDebugValues(VRM, *LIS, *TII, *TRI, SpilledLocations);
}

45
llvm/lib/CodeGen/LiveIntervals.cpp
View File

@ -148,7 +148,7 @@ bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i)
getRegUnit(i);
}
DEBUG(dump());
LLVM_DEBUG(dump());
return true;
}
@ -311,7 +311,7 @@ void LiveIntervals::computeRegUnitRange(LiveRange &LR, unsigned Unit) {
/// entering the entry block or a landing pad.
void LiveIntervals::computeLiveInRegUnits() {
RegUnitRanges.resize(TRI->getNumRegUnits());
DEBUG(dbgs() << "Computing live-in reg-units in ABI blocks.\n");
LLVM_DEBUG(dbgs() << "Computing live-in reg-units in ABI blocks.\n");
// Keep track of the live range sets allocated.
SmallVector<unsigned, 8> NewRanges;
@ -324,7 +324,7 @@ void LiveIntervals::computeLiveInRegUnits() {
// Create phi-defs at Begin for all live-in registers.
SlotIndex Begin = Indexes->getMBBStartIdx(&MBB);
DEBUG(dbgs() << Begin << "\t" << printMBBReference(MBB));
LLVM_DEBUG(dbgs() << Begin << "\t" << printMBBReference(MBB));
for (const auto &LI : MBB.liveins()) {
for (MCRegUnitIterator Units(LI.PhysReg, TRI); Units.isValid(); ++Units) {
unsigned Unit = *Units;
@ -336,12 +336,12 @@ void LiveIntervals::computeLiveInRegUnits() {
}
VNInfo *VNI = LR->createDeadDef(Begin, getVNInfoAllocator());
(void)VNI;
DEBUG(dbgs() << ' ' << printRegUnit(Unit, TRI) << '#' << VNI->id);
LLVM_DEBUG(dbgs() << ' ' << printRegUnit(Unit, TRI) << '#' << VNI->id);
}
}
DEBUG(dbgs() << '\n');
LLVM_DEBUG(dbgs() << '\n');
}
DEBUG(dbgs() << "Created " << NewRanges.size() << " new intervals.\n");
LLVM_DEBUG(dbgs() << "Created " << NewRanges.size() << " new intervals.\n");
// Compute the 'normal' part of the ranges.
for (unsigned Unit : NewRanges)
@ -397,7 +397,7 @@ static void extendSegmentsToUses(LiveRange &LR, const SlotIndexes &Indexes,
}
// VNI is live-in to MBB.
DEBUG(dbgs() << " live-in at " << BlockStart << '\n');
LLVM_DEBUG(dbgs() << " live-in at " << BlockStart << '\n');
LR.addSegment(LiveRange::Segment(BlockStart, Idx, VNI));
// Make sure VNI is live-out from the predecessors.
@ -414,7 +414,7 @@ static void extendSegmentsToUses(LiveRange &LR, const SlotIndexes &Indexes,
bool LiveIntervals::shrinkToUses(LiveInterval *li,
SmallVectorImpl<MachineInstr*> *dead) {
DEBUG(dbgs() << "Shrink: " << *li << '\n');
LLVM_DEBUG(dbgs() << "Shrink: " << *li << '\n');
assert(TargetRegisterInfo::isVirtualRegister(li->reg)
&& "Can only shrink virtual registers");
@ -443,9 +443,10 @@ bool LiveIntervals::shrinkToUses(LiveInterval *li,
// This shouldn't happen: readsVirtualRegister returns true, but there is
// no live value. It is likely caused by a target getting <undef> flags
// wrong.
DEBUG(dbgs() << Idx << '\t' << UseMI
<< "Warning: Instr claims to read non-existent value in "
<< *li << '\n');
LLVM_DEBUG(
dbgs() << Idx << '\t' << UseMI
<< "Warning: Instr claims to read non-existent value in "
<< *li << '\n');
continue;
}
// Special case: An early-clobber tied operand reads and writes the
@ -466,7 +467,7 @@ bool LiveIntervals::shrinkToUses(LiveInterval *li,
// Handle dead values.
bool CanSeparate = computeDeadValues(*li, dead);
DEBUG(dbgs() << "Shrunk: " << *li << '\n');
LLVM_DEBUG(dbgs() << "Shrunk: " << *li << '\n');
return CanSeparate;
}
@ -496,7 +497,7 @@ bool LiveIntervals::computeDeadValues(LiveInterval &LI,
// This is a dead PHI. Remove it.
VNI->markUnused();
LI.removeSegment(I);
DEBUG(dbgs() << "Dead PHI at " << Def << " may separate interval\n");
LLVM_DEBUG(dbgs() << "Dead PHI at " << Def << " may separate interval\n");
MayHaveSplitComponents = true;
} else {
// This is a dead def. Make sure the instruction knows.
@ -504,7 +505,7 @@ bool LiveIntervals::computeDeadValues(LiveInterval &LI,
assert(MI && "No instruction defining live value");
MI->addRegisterDead(LI.reg, TRI);
if (dead && MI->allDefsAreDead()) {
DEBUG(dbgs() << "All defs dead: " << Def << '\t' << *MI);
LLVM_DEBUG(dbgs() << "All defs dead: " << Def << '\t' << *MI);
dead->push_back(MI);
}
}
@ -513,7 +514,7 @@ bool LiveIntervals::computeDeadValues(LiveInterval &LI,
}
void LiveIntervals::shrinkToUses(LiveInterval::SubRange &SR, unsigned Reg) {
DEBUG(dbgs() << "Shrink: " << SR << '\n');
LLVM_DEBUG(dbgs() << "Shrink: " << SR << '\n');
assert(TargetRegisterInfo::isVirtualRegister(Reg)
&& "Can only shrink virtual registers");
// Find all the values used, including PHI kills.
@ -572,13 +573,14 @@ void LiveIntervals::shrinkToUses(LiveInterval::SubRange &SR, unsigned Reg) {
continue;
if (VNI->isPHIDef()) {
// This is a dead PHI. Remove it.
DEBUG(dbgs() << "Dead PHI at " << VNI->def << " may separate interval\n");
LLVM_DEBUG(dbgs() << "Dead PHI at " << VNI->def
<< " may separate interval\n");
VNI->markUnused();
SR.removeSegment(*Segment);
}
}
DEBUG(dbgs() << "Shrunk: " << SR << '\n');
LLVM_DEBUG(dbgs() << "Shrunk: " << SR << '\n');
}
void LiveIntervals::extendToIndices(LiveRange &LR,
@ -943,7 +945,8 @@ public:
/// Update all live ranges touched by MI, assuming a move from OldIdx to
/// NewIdx.
void updateAllRanges(MachineInstr *MI) {
DEBUG(dbgs() << "handleMove " << OldIdx << " -> " << NewIdx << ": " << *MI);
LLVM_DEBUG(dbgs() << "handleMove " << OldIdx << " -> " << NewIdx << ": "
<< *MI);
bool hasRegMask = false;
for (MachineOperand &MO : MI->operands()) {
if (MO.isRegMask())
@ -993,7 +996,7 @@ private:
void updateRange(LiveRange &LR, unsigned Reg, LaneBitmask LaneMask) {
if (!Updated.insert(&LR).second)
return;
DEBUG({
LLVM_DEBUG({
dbgs() << " ";
if (TargetRegisterInfo::isVirtualRegister(Reg)) {
dbgs() << printReg(Reg);
@ -1008,7 +1011,7 @@ private:
handleMoveDown(LR);
else
handleMoveUp(LR, Reg, LaneMask);
DEBUG(dbgs() << " -->\t" << LR << '\n');
LLVM_DEBUG(dbgs() << " -->\t" << LR << '\n');
LR.verify();
}
@ -1611,7 +1614,7 @@ void LiveIntervals::splitSeparateComponents(LiveInterval &LI,
unsigned NumComp = ConEQ.Classify(LI);
if (NumComp <= 1)
return;
DEBUG(dbgs() << " Split " << NumComp << " components: " << LI << '\n');
LLVM_DEBUG(dbgs() << " Split " << NumComp << " components: " << LI << '\n');
unsigned Reg = LI.reg;
const TargetRegisterClass *RegClass = MRI->getRegClass(Reg);
for (unsigned I = 1; I < NumComp; ++I) {

16
llvm/lib/CodeGen/LiveRangeEdit.cpp
View File

@ -220,8 +220,8 @@ bool LiveRangeEdit::foldAsLoad(LiveInterval *LI,
if (!DefMI->isSafeToMove(nullptr, SawStore))
return false;
DEBUG(dbgs() << "Try to fold single def: " << *DefMI
<< " into single use: " << *UseMI);
LLVM_DEBUG(dbgs() << "Try to fold single def: " << *DefMI
<< " into single use: " << *UseMI);
SmallVector<unsigned, 8> Ops;
if (UseMI->readsWritesVirtualRegister(LI->reg, &Ops).second)
@ -230,7 +230,7 @@ bool LiveRangeEdit::foldAsLoad(LiveInterval *LI,
MachineInstr *FoldMI = TII.foldMemoryOperand(*UseMI, Ops, *DefMI, &LIS);
if (!FoldMI)
return false;
DEBUG(dbgs() << " folded: " << *FoldMI);
LLVM_DEBUG(dbgs() << " folded: " << *FoldMI);
LIS.ReplaceMachineInstrInMaps(*UseMI, *FoldMI);
UseMI->eraseFromParent();
DefMI->addRegisterDead(LI->reg, nullptr);
@ -267,18 +267,18 @@ void LiveRangeEdit::eliminateDeadDef(MachineInstr *MI, ToShrinkSet &ToShrink,
}
// Never delete inline asm.
if (MI->isInlineAsm()) {
DEBUG(dbgs() << "Won't delete: " << Idx << '\t' << *MI);
LLVM_DEBUG(dbgs() << "Won't delete: " << Idx << '\t' << *MI);
return;
}
// Use the same criteria as DeadMachineInstructionElim.
bool SawStore = false;
if (!MI->isSafeToMove(nullptr, SawStore)) {
DEBUG(dbgs() << "Can't delete: " << Idx << '\t' << *MI);
LLVM_DEBUG(dbgs() << "Can't delete: " << Idx << '\t' << *MI);
return;
}
DEBUG(dbgs() << "Deleting dead def " << Idx << '\t' << *MI);
LLVM_DEBUG(dbgs() << "Deleting dead def " << Idx << '\t' << *MI);
// Collect virtual registers to be erased after MI is gone.
SmallVector<unsigned, 8> RegsToErase;
@ -352,7 +352,7 @@ void LiveRangeEdit::eliminateDeadDef(MachineInstr *MI, ToShrinkSet &ToShrink,
continue;
MI->RemoveOperand(i-1);
}
DEBUG(dbgs() << "Converted physregs to:\t" << *MI);
LLVM_DEBUG(dbgs() << "Converted physregs to:\t" << *MI);
} else {
// If the dest of MI is an original reg and MI is reMaterializable,
// don't delete the inst. Replace the dest with a new reg, and keep
@ -465,7 +465,7 @@ LiveRangeEdit::calculateRegClassAndHint(MachineFunction &MF,
for (unsigned I = 0, Size = size(); I < Size; ++I) {
LiveInterval &LI = LIS.getInterval(get(I));
if (MRI.recomputeRegClass(LI.reg))
DEBUG({
LLVM_DEBUG({
const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
dbgs() << "Inflated " << printReg(LI.reg) << " to "
<< TRI->getRegClassName(MRI.getRegClass(LI.reg)) << '\n';

2
llvm/lib/CodeGen/LiveRangeShrink.cpp
View File

@ -111,7 +111,7 @@ bool LiveRangeShrink::runOnMachineFunction(MachineFunction &MF) {
MachineRegisterInfo &MRI = MF.getRegInfo();
DEBUG(dbgs() << "**** Analysing " << MF.getName() << '\n');
LLVM_DEBUG(dbgs() << "**** Analysing " << MF.getName() << '\n');
InstOrderMap IOM;
// Map from register to instruction order (value of IOM) where the

36
llvm/lib/CodeGen/LiveRegMatrix.cpp
View File

@ -102,37 +102,37 @@ static bool foreachUnit(const TargetRegisterInfo *TRI,
}
void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) {
DEBUG(dbgs() << "assigning " << printReg(VirtReg.reg, TRI)
<< " to " << printReg(PhysReg, TRI) << ':');
LLVM_DEBUG(dbgs() << "assigning " << printReg(VirtReg.reg, TRI) << " to "
<< printReg(PhysReg, TRI) << ':');
assert(!VRM->hasPhys(VirtReg.reg) && "Duplicate VirtReg assignment");
VRM->assignVirt2Phys(VirtReg.reg, PhysReg);
foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit,
const LiveRange &Range) {
DEBUG(dbgs() << ' ' << printRegUnit(Unit, TRI) << ' ' << Range);
Matrix[Unit].unify(VirtReg, Range);
return false;
});
foreachUnit(
TRI, VirtReg, PhysReg, [&](unsigned Unit, const LiveRange &Range) {
LLVM_DEBUG(dbgs() << ' ' << printRegUnit(Unit, TRI) << ' ' << Range);
Matrix[Unit].unify(VirtReg, Range);
return false;
});
++NumAssigned;
DEBUG(dbgs() << '\n');
LLVM_DEBUG(dbgs() << '\n');
}
void LiveRegMatrix::unassign(LiveInterval &VirtReg) {
unsigned PhysReg = VRM->getPhys(VirtReg.reg);
DEBUG(dbgs() << "unassigning " << printReg(VirtReg.reg, TRI)
<< " from " << printReg(PhysReg, TRI) << ':');
LLVM_DEBUG(dbgs() << "unassigning " << printReg(VirtReg.reg, TRI) << " from "
<< printReg(PhysReg, TRI) << ':');
VRM->clearVirt(VirtReg.reg);
foreachUnit(TRI, VirtReg, PhysReg, [&](unsigned Unit,
const LiveRange &Range) {
DEBUG(dbgs() << ' ' << printRegUnit(Unit, TRI));
Matrix[Unit].extract(VirtReg, Range);
return false;
});
foreachUnit(TRI, VirtReg, PhysReg,
[&](unsigned Unit, const LiveRange &Range) {
LLVM_DEBUG(dbgs() << ' ' << printRegUnit(Unit, TRI));
Matrix[Unit].extract(VirtReg, Range);
return false;
});
++NumUnassigned;
DEBUG(dbgs() << '\n');
LLVM_DEBUG(dbgs() << '\n');
}
bool LiveRegMatrix::isPhysRegUsed(unsigned PhysReg) const {

17
llvm/lib/CodeGen/LocalStackSlotAllocation.cpp
View File

@ -164,8 +164,8 @@ void LocalStackSlotPass::AdjustStackOffset(MachineFrameInfo &MFI,
Offset = (Offset + Align - 1) / Align * Align;
int64_t LocalOffset = StackGrowsDown ? -Offset : Offset;
DEBUG(dbgs() << "Allocate FI(" << FrameIdx << ") to local offset "
<< LocalOffset << "\n");
LLVM_DEBUG(dbgs() << "Allocate FI(" << FrameIdx << ") to local offset "
<< LocalOffset << "\n");
// Keep the offset available for base register allocation
LocalOffsets[FrameIdx] = LocalOffset;
// And tell MFI about it for PEI to use later
@ -351,7 +351,7 @@ bool LocalStackSlotPass::insertFrameReferenceRegisters(MachineFunction &Fn) {
assert(MFI.isObjectPreAllocated(FrameIdx) &&
"Only pre-allocated locals expected!");
DEBUG(dbgs() << "Considering: " << MI);
LLVM_DEBUG(dbgs() << "Considering: " << MI);
unsigned idx = 0;
for (unsigned f = MI.getNumOperands(); idx != f; ++idx) {
@ -367,7 +367,7 @@ bool LocalStackSlotPass::insertFrameReferenceRegisters(MachineFunction &Fn) {
int64_t Offset = 0;
int64_t FrameSizeAdjust = StackGrowsDown ? MFI.getLocalFrameSize() : 0;
DEBUG(dbgs() << " Replacing FI in: " << MI);
LLVM_DEBUG(dbgs() << " Replacing FI in: " << MI);
// If we have a suitable base register available, use it; otherwise
// create a new one. Note that any offset encoded in the
@ -377,7 +377,7 @@ bool LocalStackSlotPass::insertFrameReferenceRegisters(MachineFunction &Fn) {
if (UsedBaseReg &&
lookupCandidateBaseReg(BaseReg, BaseOffset, FrameSizeAdjust,
LocalOffset, MI, TRI)) {
DEBUG(dbgs() << " Reusing base register " << BaseReg << "\n");
LLVM_DEBUG(dbgs() << " Reusing base register " << BaseReg << "\n");
// We found a register to reuse.
Offset = FrameSizeAdjust + LocalOffset - BaseOffset;
} else {
@ -405,8 +405,9 @@ bool LocalStackSlotPass::insertFrameReferenceRegisters(MachineFunction &Fn) {
const TargetRegisterClass *RC = TRI->getPointerRegClass(*MF);
BaseReg = Fn.getRegInfo().createVirtualRegister(RC);
DEBUG(dbgs() << " Materializing base register " << BaseReg <<
" at frame local offset " << LocalOffset + InstrOffset << "\n");
LLVM_DEBUG(dbgs() << " Materializing base register " << BaseReg
<< " at frame local offset "
<< LocalOffset + InstrOffset << "\n");
// Tell the target to insert the instruction to initialize
// the base register.
@ -427,7 +428,7 @@ bool LocalStackSlotPass::insertFrameReferenceRegisters(MachineFunction &Fn) {
// Modify the instruction to use the new base register rather
// than the frame index operand.
TRI->resolveFrameIndex(MI, BaseReg, Offset);
DEBUG(dbgs() << "Resolved: " << MI);
LLVM_DEBUG(dbgs() << "Resolved: " << MI);
++NumReplacements;
}

89
llvm/lib/CodeGen/MIRCanonicalizerPass.cpp
View File

@ -141,7 +141,7 @@ rescheduleLexographically(std::vector<MachineInstr *> instructions,
for (auto &II : StringInstrMap) {
DEBUG({
LLVM_DEBUG({
dbgs() << "Splicing ";
II.second->dump();
dbgs() << " right before: ";
@ -233,7 +233,7 @@ static bool rescheduleCanonically(unsigned &PseudoIdempotentInstCount,
continue;
}
DEBUG(dbgs() << "Operand " << 0 << " of "; II->dump(); MO.dump(););
LLVM_DEBUG(dbgs() << "Operand " << 0 << " of "; II->dump(); MO.dump(););
MachineInstr *Def = II;
unsigned Distance = ~0U;
@ -280,7 +280,7 @@ static bool rescheduleCanonically(unsigned &PseudoIdempotentInstCount,
if (DefI == BBE || UseI == BBE)
continue;
DEBUG({
LLVM_DEBUG({
dbgs() << "Splicing ";
DefI->dump();
dbgs() << " right before: ";
@ -302,13 +302,15 @@ static bool rescheduleCanonically(unsigned &PseudoIdempotentInstCount,
if (UseI == MBB->instr_end())
continue;
DEBUG(dbgs() << "Rescheduling Multi-Use Instructions Lexographically.";);
LLVM_DEBUG(
dbgs() << "Rescheduling Multi-Use Instructions Lexographically.";);
Changed |= rescheduleLexographically(
E.second, MBB, [&]() -> MachineBasicBlock::iterator { return UseI; });
}
PseudoIdempotentInstCount = PseudoIdempotentInstructions.size();
DEBUG(dbgs() << "Rescheduling Idempotent Instructions Lexographically.";);
LLVM_DEBUG(
dbgs() << "Rescheduling Idempotent Instructions Lexographically.";);
Changed |= rescheduleLexographically(
PseudoIdempotentInstructions, MBB,
[&]() -> MachineBasicBlock::iterator { return MBB->begin(); });
@ -384,7 +386,7 @@ static std::vector<MachineInstr *> populateCandidates(MachineBasicBlock *MBB) {
if (!MI->mayStore() && !MI->isBranch() && !DoesMISideEffect)
continue;
DEBUG(dbgs() << "Found Candidate: "; MI->dump(););
LLVM_DEBUG(dbgs() << "Found Candidate: "; MI->dump(););
Candidates.push_back(MI);
}
@ -405,7 +407,7 @@ static void doCandidateWalk(std::vector<TypedVReg> &VRegs,
RegQueue.pop();
if (TReg.isFrameIndex()) {
DEBUG(dbgs() << "Popping frame index.\n";);
LLVM_DEBUG(dbgs() << "Popping frame index.\n";);
VRegs.push_back(TypedVReg(RSE_FrameIndex));
continue;
}
@ -414,7 +416,7 @@ static void doCandidateWalk(std::vector<TypedVReg> &VRegs,
unsigned Reg = TReg.getReg();
if (TargetRegisterInfo::isVirtualRegister(Reg)) {
DEBUG({
LLVM_DEBUG({
dbgs() << "Popping vreg ";
MRI.def_begin(Reg)->dump();
dbgs() << "\n";
@ -426,7 +428,7 @@ static void doCandidateWalk(std::vector<TypedVReg> &VRegs,
VRegs.push_back(TypedVReg(Reg));
}
} else {
DEBUG(dbgs() << "Popping physreg.\n";);
LLVM_DEBUG(dbgs() << "Popping physreg.\n";);
VRegs.push_back(TypedVReg(Reg));
continue;
}
@ -442,7 +444,7 @@ static void doCandidateWalk(std::vector<TypedVReg> &VRegs,
break;
}
DEBUG({
LLVM_DEBUG({
dbgs() << "\n========================\n";
dbgs() << "Visited MI: ";
Def->dump();
@ -454,7 +456,7 @@ static void doCandidateWalk(std::vector<TypedVReg> &VRegs,
MachineOperand &MO = Def->getOperand(I);
if (MO.isFI()) {
DEBUG(dbgs() << "Pushing frame index.\n";);
LLVM_DEBUG(dbgs() << "Pushing frame index.\n";);
RegQueue.push(TypedVReg(RSE_FrameIndex));
}
@ -526,7 +528,7 @@ GetVRegRenameMap(const std::vector<TypedVReg> &VRegs,
// from a copy from a frame index. So it's safe to skip by one.
unsigned LastRenameReg = NVC.incrementVirtualVReg();
(void)LastRenameReg;
DEBUG(dbgs() << "Skipping rename for FI " << LastRenameReg << "\n";);
LLVM_DEBUG(dbgs() << "Skipping rename for FI " << LastRenameReg << "\n";);
continue;
} else if (vreg.isCandidate()) {
@ -543,7 +545,7 @@ GetVRegRenameMap(const std::vector<TypedVReg> &VRegs,
} else if (!TargetRegisterInfo::isVirtualRegister(vreg.getReg())) {
unsigned LastRenameReg = NVC.incrementVirtualVReg();
(void)LastRenameReg;
DEBUG({
LLVM_DEBUG({
dbgs() << "Skipping rename for Phys Reg " << LastRenameReg << "\n";
});
continue;
@ -551,26 +553,27 @@ GetVRegRenameMap(const std::vector<TypedVReg> &VRegs,
auto Reg = vreg.getReg();
if (llvm::find(renamedInOtherBB, Reg) != renamedInOtherBB.end()) {
DEBUG(dbgs() << "Vreg " << Reg << " already renamed in other BB.\n";);
LLVM_DEBUG(dbgs() << "Vreg " << Reg
<< " already renamed in other BB.\n";);
continue;
}
auto Rename = NVC.createVirtualRegister(MRI.getRegClass(Reg));
if (VRegRenameMap.find(Reg) == VRegRenameMap.end()) {
DEBUG(dbgs() << "Mapping vreg ";);
LLVM_DEBUG(dbgs() << "Mapping vreg ";);
if (MRI.reg_begin(Reg) != MRI.reg_end()) {
DEBUG(auto foo = &*MRI.reg_begin(Reg); foo->dump(););
LLVM_DEBUG(auto foo = &*MRI.reg_begin(Reg); foo->dump(););
} else {
DEBUG(dbgs() << Reg;);
LLVM_DEBUG(dbgs() << Reg;);
}
DEBUG(dbgs() << " to ";);
LLVM_DEBUG(dbgs() << " to ";);
if (MRI.reg_begin(Rename) != MRI.reg_end()) {
DEBUG(auto foo = &*MRI.reg_begin(Rename); foo->dump(););
LLVM_DEBUG(auto foo = &*MRI.reg_begin(Rename); foo->dump(););
} else {
DEBUG(dbgs() << Rename;);
LLVM_DEBUG(dbgs() << Rename;);
}
DEBUG(dbgs() << "\n";);
LLVM_DEBUG(dbgs() << "\n";);
VRegRenameMap.insert(std::pair<unsigned, unsigned>(Reg, Rename));
}
@ -638,18 +641,19 @@ static bool runOnBasicBlock(MachineBasicBlock *MBB,
if (CanonicalizeBasicBlockNumber != ~0U) {
if (CanonicalizeBasicBlockNumber != basicBlockNum++)
return false;
DEBUG(dbgs() << "\n Canonicalizing BasicBlock " << MBB->getName() << "\n";);
LLVM_DEBUG(dbgs() << "\n Canonicalizing BasicBlock " << MBB->getName()
<< "\n";);
}
if (llvm::find(bbNames, MBB->getName()) != bbNames.end()) {
DEBUG({
LLVM_DEBUG({
dbgs() << "Found potentially duplicate BasicBlocks: " << MBB->getName()
<< "\n";
});
return false;
}
DEBUG({
LLVM_DEBUG({
dbgs() << "\n\n NEW BASIC BLOCK: " << MBB->getName() << " \n\n";
dbgs() << "\n\n================================================\n\n";
});
@ -659,16 +663,17 @@ static bool runOnBasicBlock(MachineBasicBlock *MBB,
MachineRegisterInfo &MRI = MF.getRegInfo();
bbNames.push_back(MBB->getName());
DEBUG(dbgs() << "\n\n NEW BASIC BLOCK: " << MBB->getName() << "\n\n";);
LLVM_DEBUG(dbgs() << "\n\n NEW BASIC BLOCK: " << MBB->getName() << "\n\n";);
DEBUG(dbgs() << "MBB Before Canonical Copy Propagation:\n"; MBB->dump(););
LLVM_DEBUG(dbgs() << "MBB Before Canonical Copy Propagation:\n";
MBB->dump(););
Changed |= propagateLocalCopies(MBB);
DEBUG(dbgs() << "MBB After Canonical Copy Propagation:\n"; MBB->dump(););
LLVM_DEBUG(dbgs() << "MBB After Canonical Copy Propagation:\n"; MBB->dump(););
DEBUG(dbgs() << "MBB Before Scheduling:\n"; MBB->dump(););
LLVM_DEBUG(dbgs() << "MBB Before Scheduling:\n"; MBB->dump(););
unsigned IdempotentInstCount = 0;
Changed |= rescheduleCanonically(IdempotentInstCount, MBB);
DEBUG(dbgs() << "MBB After Scheduling:\n"; MBB->dump(););
LLVM_DEBUG(dbgs() << "MBB After Scheduling:\n"; MBB->dump(););
std::vector<MachineInstr *> Candidates = populateCandidates(MBB);
std::vector<MachineInstr *> VisitedMIs;
@ -693,7 +698,7 @@ static bool runOnBasicBlock(MachineBasicBlock *MBB,
if (!(MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())))
continue;
DEBUG(dbgs() << "Enqueue register"; MO.dump(); dbgs() << "\n";);
LLVM_DEBUG(dbgs() << "Enqueue register"; MO.dump(); dbgs() << "\n";);
RegQueue.push(TypedVReg(MO.getReg()));
}
@ -710,7 +715,7 @@ static bool runOnBasicBlock(MachineBasicBlock *MBB,
if (!MO.isReg() && !MO.isFI())
continue;
DEBUG(dbgs() << "Enqueue Reg/FI"; MO.dump(); dbgs() << "\n";);
LLVM_DEBUG(dbgs() << "Enqueue Reg/FI"; MO.dump(); dbgs() << "\n";);
RegQueue.push(MO.isReg() ? TypedVReg(MO.getReg())
: TypedVReg(RSE_FrameIndex));
@ -752,8 +757,10 @@ static bool runOnBasicBlock(MachineBasicBlock *MBB,
Changed |= doDefKillClear(MBB);
DEBUG(dbgs() << "Updated MachineBasicBlock:\n"; MBB->dump(); dbgs() << "\n";);
DEBUG(dbgs() << "\n\n================================================\n\n");
LLVM_DEBUG(dbgs() << "Updated MachineBasicBlock:\n"; MBB->dump();
dbgs() << "\n";);
LLVM_DEBUG(
dbgs() << "\n\n================================================\n\n");
return Changed;
}
@ -763,19 +770,21 @@ bool MIRCanonicalizer::runOnMachineFunction(MachineFunction &MF) {
if (CanonicalizeFunctionNumber != ~0U) {
if (CanonicalizeFunctionNumber != functionNum++)
return false;
DEBUG(dbgs() << "\n Canonicalizing Function " << MF.getName() << "\n";);
LLVM_DEBUG(dbgs() << "\n Canonicalizing Function " << MF.getName()
<< "\n";);
}
// we need a valid vreg to create a vreg type for skipping all those
// stray vreg numbers so reach alignment/canonical vreg values.
std::vector<MachineBasicBlock *> RPOList = GetRPOList(MF);
DEBUG(dbgs() << "\n\n NEW MACHINE FUNCTION: " << MF.getName() << " \n\n";
dbgs() << "\n\n================================================\n\n";
dbgs() << "Total Basic Blocks: " << RPOList.size() << "\n";
for (auto MBB
: RPOList) { dbgs() << MBB->getName() << "\n"; } dbgs()
<< "\n\n================================================\n\n";);
LLVM_DEBUG(
dbgs() << "\n\n NEW MACHINE FUNCTION: " << MF.getName() << " \n\n";
dbgs() << "\n\n================================================\n\n";
dbgs() << "Total Basic Blocks: " << RPOList.size() << "\n";
for (auto MBB
: RPOList) { dbgs() << MBB->getName() << "\n"; } dbgs()
<< "\n\n================================================\n\n";);
std::vector<StringRef> BBNames;
std::vector<unsigned> RenamedInOtherBB;

14
llvm/lib/CodeGen/MachineBasicBlock.cpp
View File

@ -855,9 +855,9 @@ MachineBasicBlock *MachineBasicBlock::SplitCriticalEdge(MachineBasicBlock *Succ,
MachineBasicBlock *NMBB = MF->CreateMachineBasicBlock();
MF->insert(std::next(MachineFunction::iterator(this)), NMBB);
DEBUG(dbgs() << "Splitting critical edge: " << printMBBReference(*this)
<< " -- " << printMBBReference(*NMBB) << " -- "
<< printMBBReference(*Succ) << '\n');
LLVM_DEBUG(dbgs() << "Splitting critical edge: " << printMBBReference(*this)
<< " -- " << printMBBReference(*NMBB) << " -- "
<< printMBBReference(*Succ) << '\n');
LiveIntervals *LIS = P.getAnalysisIfAvailable<LiveIntervals>();
SlotIndexes *Indexes = P.getAnalysisIfAvailable<SlotIndexes>();
@ -886,7 +886,7 @@ MachineBasicBlock *MachineBasicBlock::SplitCriticalEdge(MachineBasicBlock *Succ,
if (TargetRegisterInfo::isPhysicalRegister(Reg) ||
LV->getVarInfo(Reg).removeKill(*MI)) {
KilledRegs.push_back(Reg);
DEBUG(dbgs() << "Removing terminator kill: " << *MI);
LLVM_DEBUG(dbgs() << "Removing terminator kill: " << *MI);
OI->setIsKill(false);
}
}
@ -977,7 +977,7 @@ MachineBasicBlock *MachineBasicBlock::SplitCriticalEdge(MachineBasicBlock *Succ,
continue;
if (TargetRegisterInfo::isVirtualRegister(Reg))
LV->getVarInfo(Reg).Kills.push_back(&*I);
DEBUG(dbgs() << "Restored terminator kill: " << *I);
LLVM_DEBUG(dbgs() << "Restored terminator kill: " << *I);
break;
}
}
@ -1110,8 +1110,8 @@ bool MachineBasicBlock::canSplitCriticalEdge(
// case that we can't handle. Since this never happens in properly optimized
// code, just skip those edges.
if (TBB && TBB == FBB) {
DEBUG(dbgs() << "Won't split critical edge after degenerate "
<< printMBBReference(*this) << '\n');
LLVM_DEBUG(dbgs() << "Won't split critical edge after degenerate "
<< printMBBReference(*this) << '\n');
return false;
}
return true;

161
llvm/lib/CodeGen/MachineBlockPlacement.cpp
View File

@ -643,7 +643,8 @@ BranchProbability MachineBlockPlacement::collectViableSuccessors(
if (SuccChain == &Chain) {
SkipSucc = true;
} else if (Succ != *SuccChain->begin()) {
DEBUG(dbgs() << " " << getBlockName(Succ) << " -> Mid chain!\n");
LLVM_DEBUG(dbgs() << " " << getBlockName(Succ)
<< " -> Mid chain!\n");
continue;
}
}
@ -1010,7 +1011,7 @@ MachineBlockPlacement::getBestTrellisSuccessor(
// If we have a trellis, and BB doesn't have the best fallthrough edges,
// we shouldn't choose any successor. We've already looked and there's a
// better fallthrough edge for all the successors.
DEBUG(dbgs() << "Trellis, but not one of the chosen edges.\n");
LLVM_DEBUG(dbgs() << "Trellis, but not one of the chosen edges.\n");
return Result;
}
@ -1027,10 +1028,11 @@ MachineBlockPlacement::getBestTrellisSuccessor(
canTailDuplicateUnplacedPreds(BB, Succ2, Chain, BlockFilter) &&
isProfitableToTailDup(BB, Succ2, MBPI->getEdgeProbability(BB, Succ1),
Chain, BlockFilter)) {
DEBUG(BranchProbability Succ2Prob = getAdjustedProbability(
MBPI->getEdgeProbability(BB, Succ2), AdjustedSumProb);
dbgs() << " Selected: " << getBlockName(Succ2)
<< ", probability: " << Succ2Prob << " (Tail Duplicate)\n");
LLVM_DEBUG(BranchProbability Succ2Prob = getAdjustedProbability(
MBPI->getEdgeProbability(BB, Succ2), AdjustedSumProb);
dbgs() << " Selected: " << getBlockName(Succ2)
<< ", probability: " << Succ2Prob
<< " (Tail Duplicate)\n");
Result.BB = Succ2;
Result.ShouldTailDup = true;
return Result;
@ -1041,10 +1043,10 @@ MachineBlockPlacement::getBestTrellisSuccessor(
ComputedEdges[BestB.Src] = { BestB.Dest, false };
auto TrellisSucc = BestA.Dest;
DEBUG(BranchProbability SuccProb = getAdjustedProbability(
MBPI->getEdgeProbability(BB, TrellisSucc), AdjustedSumProb);
dbgs() << " Selected: " << getBlockName(TrellisSucc)
<< ", probability: " << SuccProb << " (Trellis)\n");
LLVM_DEBUG(BranchProbability SuccProb = getAdjustedProbability(
MBPI->getEdgeProbability(BB, TrellisSucc), AdjustedSumProb);
dbgs() << " Selected: " << getBlockName(TrellisSucc)
<< ", probability: " << SuccProb << " (Trellis)\n");
Result.BB = TrellisSucc;
return Result;
}
@ -1150,7 +1152,7 @@ void MachineBlockPlacement::precomputeTriangleChains() {
if (TriangleChainCount == 0)
return;
DEBUG(dbgs() << "Pre-computing triangle chains.\n");
LLVM_DEBUG(dbgs() << "Pre-computing triangle chains.\n");
// Map from last block to the chain that contains it. This allows us to extend
// chains as we find new triangles.
DenseMap<const MachineBasicBlock *, TriangleChain> TriangleChainMap;
@ -1224,8 +1226,9 @@ void MachineBlockPlacement::precomputeTriangleChains() {
MachineBasicBlock *dst = Chain.Edges.back();
Chain.Edges.pop_back();
for (MachineBasicBlock *src : reverse(Chain.Edges)) {
DEBUG(dbgs() << "Marking edge: " << getBlockName(src) << "->" <<
getBlockName(dst) << " as pre-computed based on triangles.\n");
LLVM_DEBUG(dbgs() << "Marking edge: " << getBlockName(src) << "->"
<< getBlockName(dst)
<< " as pre-computed based on triangles.\n");
auto InsertResult = ComputedEdges.insert({src, {dst, true}});
assert(InsertResult.second && "Block seen twice.");
@ -1431,8 +1434,8 @@ bool MachineBlockPlacement::hasBetterLayoutPredecessor(
}
if (BadCFGConflict) {
DEBUG(dbgs() << " Not a candidate: " << getBlockName(Succ) << " -> " << SuccProb
<< " (prob) (non-cold CFG conflict)\n");
LLVM_DEBUG(dbgs() << " Not a candidate: " << getBlockName(Succ) << " -> "
<< SuccProb << " (prob) (non-cold CFG conflict)\n");
return true;
}
@ -1462,7 +1465,8 @@ MachineBlockPlacement::selectBestSuccessor(
auto AdjustedSumProb =
collectViableSuccessors(BB, Chain, BlockFilter, Successors);
DEBUG(dbgs() << "Selecting best successor for: " << getBlockName(BB) << "\n");
LLVM_DEBUG(dbgs() << "Selecting best successor for: " << getBlockName(BB)
<< "\n");
// if we already precomputed the best successor for BB, return that if still
// applicable.
@ -1503,18 +1507,18 @@ MachineBlockPlacement::selectBestSuccessor(
continue;
}
DEBUG(
dbgs() << " Candidate: " << getBlockName(Succ) << ", probability: "
<< SuccProb
LLVM_DEBUG(
dbgs() << " Candidate: " << getBlockName(Succ)
<< ", probability: " << SuccProb
<< (SuccChain.UnscheduledPredecessors != 0 ? " (CFG break)" : "")
<< "\n");
if (BestSucc.BB && BestProb >= SuccProb) {
DEBUG(dbgs() << " Not the best candidate, continuing\n");
LLVM_DEBUG(dbgs() << " Not the best candidate, continuing\n");
continue;
}
DEBUG(dbgs() << " Setting it as best candidate\n");
LLVM_DEBUG(dbgs() << " Setting it as best candidate\n");
BestSucc.BB = Succ;
BestProb = SuccProb;
}
@ -1539,10 +1543,9 @@ MachineBlockPlacement::selectBestSuccessor(
break;
if (canTailDuplicateUnplacedPreds(BB, Succ, Chain, BlockFilter)
&& (isProfitableToTailDup(BB, Succ, BestProb, Chain, BlockFilter))) {
DEBUG(
dbgs() << " Candidate: " << getBlockName(Succ) << ", probability: "
<< DupProb
<< " (Tail Duplicate)\n");
LLVM_DEBUG(dbgs() << " Candidate: " << getBlockName(Succ)
<< ", probability: " << DupProb
<< " (Tail Duplicate)\n");
BestSucc.BB = Succ;
BestSucc.ShouldTailDup = true;
break;
@ -1550,7 +1553,7 @@ MachineBlockPlacement::selectBestSuccessor(
}
if (BestSucc.BB)
DEBUG(dbgs() << " Selected: " << getBlockName(BestSucc.BB) << "\n");
LLVM_DEBUG(dbgs() << " Selected: " << getBlockName(BestSucc.BB) << "\n");
return BestSucc;
}
@ -1596,8 +1599,8 @@ MachineBasicBlock *MachineBlockPlacement::selectBestCandidateBlock(
"Found CFG-violating block");
BlockFrequency CandidateFreq = MBFI->getBlockFreq(MBB);
DEBUG(dbgs() << " " << getBlockName(MBB) << " -> ";
MBFI->printBlockFreq(dbgs(), CandidateFreq) << " (freq)\n");
LLVM_DEBUG(dbgs() << " " << getBlockName(MBB) << " -> ";
MBFI->printBlockFreq(dbgs(), CandidateFreq) << " (freq)\n");
// For ehpad, we layout the least probable first as to avoid jumping back
// from least probable landingpads to more probable ones.
@ -1723,8 +1726,8 @@ void MachineBlockPlacement::buildChain(
if (!BestSucc)
break;
DEBUG(dbgs() << "Unnatural loop CFG detected, forcibly merging the "
"layout successor until the CFG reduces\n");
LLVM_DEBUG(dbgs() << "Unnatural loop CFG detected, forcibly merging the "
"layout successor until the CFG reduces\n");
}
// Placement may have changed tail duplication opportunities.
@ -1743,15 +1746,15 @@ void MachineBlockPlacement::buildChain(
// Zero out UnscheduledPredecessors for the successor we're about to merge in case
// we selected a successor that didn't fit naturally into the CFG.
SuccChain.UnscheduledPredecessors = 0;
DEBUG(dbgs() << "Merging from " << getBlockName(BB) << " to "
<< getBlockName(BestSucc) << "\n");
LLVM_DEBUG(dbgs() << "Merging from " << getBlockName(BB) << " to "
<< getBlockName(BestSucc) << "\n");
markChainSuccessors(SuccChain, LoopHeaderBB, BlockFilter);
Chain.merge(BestSucc, &SuccChain);
BB = *std::prev(Chain.end());
}
DEBUG(dbgs() << "Finished forming chain for header block "
<< getBlockName(*Chain.begin()) << "\n");
LLVM_DEBUG(dbgs() << "Finished forming chain for header block "
<< getBlockName(*Chain.begin()) << "\n");
}
/// Find the best loop top block for layout.
@ -1784,17 +1787,17 @@ MachineBlockPlacement::findBestLoopTop(const MachineLoop &L,
if (!LoopBlockSet.count(*HeaderChain.begin()))
return L.getHeader();
DEBUG(dbgs() << "Finding best loop top for: " << getBlockName(L.getHeader())
<< "\n");
LLVM_DEBUG(dbgs() << "Finding best loop top for: "
<< getBlockName(L.getHeader()) << "\n");
BlockFrequency BestPredFreq;
MachineBasicBlock *BestPred = nullptr;
for (MachineBasicBlock *Pred : L.getHeader()->predecessors()) {
if (!LoopBlockSet.count(Pred))
continue;
DEBUG(dbgs() << " header pred: " << getBlockName(Pred) << ", has "
<< Pred->succ_size() << " successors, ";
MBFI->printBlockFreq(dbgs(), Pred) << " freq\n");
LLVM_DEBUG(dbgs() << " header pred: " << getBlockName(Pred) << ", has "
<< Pred->succ_size() << " successors, ";
MBFI->printBlockFreq(dbgs(), Pred) << " freq\n");
if (Pred->succ_size() > 1)
continue;
@ -1809,7 +1812,7 @@ MachineBlockPlacement::findBestLoopTop(const MachineLoop &L,
// If no direct predecessor is fine, just use the loop header.
if (!BestPred) {
DEBUG(dbgs() << " final top unchanged\n");
LLVM_DEBUG(dbgs() << " final top unchanged\n");
return L.getHeader();
}
@ -1819,7 +1822,7 @@ MachineBlockPlacement::findBestLoopTop(const MachineLoop &L,
*BestPred->pred_begin() != L.getHeader())
BestPred = *BestPred->pred_begin();
DEBUG(dbgs() << " final top: " << getBlockName(BestPred) << "\n");
LLVM_DEBUG(dbgs() << " final top: " << getBlockName(BestPred) << "\n");
return BestPred;
}
@ -1851,8 +1854,8 @@ MachineBlockPlacement::findBestLoopExit(const MachineLoop &L,
// blocks where rotating to exit with that block will reach an outer loop.
SmallPtrSet<MachineBasicBlock *, 4> BlocksExitingToOuterLoop;
DEBUG(dbgs() << "Finding best loop exit for: " << getBlockName(L.getHeader())
<< "\n");
LLVM_DEBUG(dbgs() << "Finding best loop exit for: "
<< getBlockName(L.getHeader()) << "\n");
for (MachineBasicBlock *MBB : L.getBlocks()) {
BlockChain &Chain = *BlockToChain[MBB];
// Ensure that this block is at the end of a chain; otherwise it could be
@ -1875,15 +1878,15 @@ MachineBlockPlacement::findBestLoopExit(const MachineLoop &L,
BlockChain &SuccChain = *BlockToChain[Succ];
// Don't split chains, either this chain or the successor's chain.
if (&Chain == &SuccChain) {
DEBUG(dbgs() << " exiting: " << getBlockName(MBB) << " -> "
<< getBlockName(Succ) << " (chain conflict)\n");
LLVM_DEBUG(dbgs() << " exiting: " << getBlockName(MBB) << " -> "
<< getBlockName(Succ) << " (chain conflict)\n");
continue;
}
auto SuccProb = MBPI->getEdgeProbability(MBB, Succ);
if (LoopBlockSet.count(Succ)) {
DEBUG(dbgs() << " looping: " << getBlockName(MBB) << " -> "
<< getBlockName(Succ) << " (" << SuccProb << ")\n");
LLVM_DEBUG(dbgs() << " looping: " << getBlockName(MBB) << " -> "
<< getBlockName(Succ) << " (" << SuccProb << ")\n");
HasLoopingSucc = true;
continue;
}
@ -1896,9 +1899,10 @@ MachineBlockPlacement::findBestLoopExit(const MachineLoop &L,
}
BlockFrequency ExitEdgeFreq = MBFI->getBlockFreq(MBB) * SuccProb;
DEBUG(dbgs() << " exiting: " << getBlockName(MBB) << " -> "
<< getBlockName(Succ) << " [L:" << SuccLoopDepth << "] (";
MBFI->printBlockFreq(dbgs(), ExitEdgeFreq) << ")\n");
LLVM_DEBUG(dbgs() << " exiting: " << getBlockName(MBB) << " -> "
<< getBlockName(Succ) << " [L:" << SuccLoopDepth
<< "] (";
MBFI->printBlockFreq(dbgs(), ExitEdgeFreq) << ")\n");
// Note that we bias this toward an existing layout successor to retain
// incoming order in the absence of better information. The exit must have
// a frequency higher than the current exit before we consider breaking
@ -1922,11 +1926,12 @@ MachineBlockPlacement::findBestLoopExit(const MachineLoop &L,
// Without a candidate exiting block or with only a single block in the
// loop, just use the loop header to layout the loop.
if (!ExitingBB) {
DEBUG(dbgs() << " No other candidate exit blocks, using loop header\n");
LLVM_DEBUG(
dbgs() << " No other candidate exit blocks, using loop header\n");
return nullptr;
}
if (L.getNumBlocks() == 1) {
DEBUG(dbgs() << " Loop has 1 block, using loop header as exit\n");
LLVM_DEBUG(dbgs() << " Loop has 1 block, using loop header as exit\n");
return nullptr;
}
@ -1937,7 +1942,8 @@ MachineBlockPlacement::findBestLoopExit(const MachineLoop &L,
!BlocksExitingToOuterLoop.count(ExitingBB))
return nullptr;
DEBUG(dbgs() << " Best exiting block: " << getBlockName(ExitingBB) << "\n");
LLVM_DEBUG(dbgs() << " Best exiting block: " << getBlockName(ExitingBB)
<< "\n");
return ExitingBB;
}
@ -2014,8 +2020,8 @@ void MachineBlockPlacement::rotateLoop(BlockChain &LoopChain,
return;
}
DEBUG(dbgs() << "Rotating loop to put exit " << getBlockName(ExitingBB)
<< " at bottom\n");
LLVM_DEBUG(dbgs() << "Rotating loop to put exit " << getBlockName(ExitingBB)
<< " at bottom\n");
std::rotate(LoopChain.begin(), std::next(ExitIt), LoopChain.end());
}
@ -2150,8 +2156,9 @@ void MachineBlockPlacement::rotateLoopWithProfile(
}
}
DEBUG(dbgs() << "The cost of loop rotation by making " << getBlockName(*Iter)
<< " to the top: " << Cost.getFrequency() << "\n");
LLVM_DEBUG(dbgs() << "The cost of loop rotation by making "
<< getBlockName(*Iter)
<< " to the top: " << Cost.getFrequency() << "\n");
if (Cost < SmallestRotationCost) {
SmallestRotationCost = Cost;
@ -2160,8 +2167,8 @@ void MachineBlockPlacement::rotateLoopWithProfile(
}
if (RotationPos != LoopChain.end()) {
DEBUG(dbgs() << "Rotate loop by making " << getBlockName(*RotationPos)
<< " to the top\n");
LLVM_DEBUG(dbgs() << "Rotate loop by making " << getBlockName(*RotationPos)
<< " to the top\n");
std::rotate(LoopChain.begin(), RotationPos, LoopChain.end());
}
}
@ -2265,7 +2272,7 @@ void MachineBlockPlacement::buildLoopChains(const MachineLoop &L) {
else
rotateLoop(LoopChain, PreferredLoopExit, LoopBlockSet);
DEBUG({
LLVM_DEBUG({
// Crash at the end so we get all of the debugging output first.
bool BadLoop = false;
if (LoopChain.UnscheduledPredecessors) {
@ -2324,9 +2331,9 @@ void MachineBlockPlacement::buildCFGChains() {
// Ensure that the layout successor is a viable block, as we know that
// fallthrough is a possibility.
assert(NextFI != FE && "Can't fallthrough past the last block.");
DEBUG(dbgs() << "Pre-merging due to unanalyzable fallthrough: "
<< getBlockName(BB) << " -> " << getBlockName(NextBB)
<< "\n");
LLVM_DEBUG(dbgs() << "Pre-merging due to unanalyzable fallthrough: "
<< getBlockName(BB) << " -> " << getBlockName(NextBB)
<< "\n");
Chain->merge(NextBB, nullptr);
#ifndef NDEBUG
BlocksWithUnanalyzableExits.insert(&*BB);
@ -2356,7 +2363,7 @@ void MachineBlockPlacement::buildCFGChains() {
#ifndef NDEBUG
using FunctionBlockSetType = SmallPtrSet<MachineBasicBlock *, 16>;
#endif
DEBUG({
LLVM_DEBUG({
// Crash at the end so we get all of the debugging output first.
bool BadFunc = false;
FunctionBlockSetType FunctionBlockSet;
@ -2381,11 +2388,11 @@ void MachineBlockPlacement::buildCFGChains() {
// Splice the blocks into place.
MachineFunction::iterator InsertPos = F->begin();
DEBUG(dbgs() << "[MBP] Function: "<< F->getName() << "\n");
LLVM_DEBUG(dbgs() << "[MBP] Function: " << F->getName() << "\n");
for (MachineBasicBlock *ChainBB : FunctionChain) {
DEBUG(dbgs() << (ChainBB == *FunctionChain.begin() ? "Placing chain "
: " ... ")
<< getBlockName(ChainBB) << "\n");
LLVM_DEBUG(dbgs() << (ChainBB == *FunctionChain.begin() ? "Placing chain "
: " ... ")
<< getBlockName(ChainBB) << "\n");
if (InsertPos != MachineFunction::iterator(ChainBB))
F->splice(InsertPos, ChainBB);
else
@ -2470,11 +2477,11 @@ void MachineBlockPlacement::optimizeBranches() {
MBPI->getEdgeProbability(ChainBB, FBB) >
MBPI->getEdgeProbability(ChainBB, TBB) &&
!TII->reverseBranchCondition(Cond)) {
DEBUG(dbgs() << "Reverse order of the two branches: "
<< getBlockName(ChainBB) << "\n");
DEBUG(dbgs() << " Edge probability: "
<< MBPI->getEdgeProbability(ChainBB, FBB) << " vs "
<< MBPI->getEdgeProbability(ChainBB, TBB) << "\n");
LLVM_DEBUG(dbgs() << "Reverse order of the two branches: "
<< getBlockName(ChainBB) << "\n");
LLVM_DEBUG(dbgs() << " Edge probability: "
<< MBPI->getEdgeProbability(ChainBB, FBB) << " vs "
<< MBPI->getEdgeProbability(ChainBB, TBB) << "\n");
DebugLoc dl; // FIXME: this is nowhere
TII->removeBranch(*ChainBB);
TII->insertBranch(*ChainBB, FBB, TBB, Cond, dl);
@ -2638,8 +2645,8 @@ bool MachineBlockPlacement::maybeTailDuplicateBlock(
if (!shouldTailDuplicate(BB))
return false;
DEBUG(dbgs() << "Redoing tail duplication for Succ#"
<< BB->getNumber() << "\n");
LLVM_DEBUG(dbgs() << "Redoing tail duplication for Succ#" << BB->getNumber()
<< "\n");
// This has to be a callback because none of it can be done after
// BB is deleted.
@ -2687,8 +2694,8 @@ bool MachineBlockPlacement::maybeTailDuplicateBlock(
if (RemBB == PreferredLoopExit)
PreferredLoopExit = nullptr;
DEBUG(dbgs() << "TailDuplicator deleted block: "
<< getBlockName(RemBB) << "\n");
LLVM_DEBUG(dbgs() << "TailDuplicator deleted block: "
<< getBlockName(RemBB) << "\n");
};
auto RemovalCallbackRef =
function_ref<void(MachineBasicBlock*)>(RemovalCallback);

17
llvm/lib/CodeGen/MachineCSE.cpp
View File

@ -178,8 +178,8 @@ bool MachineCSE::PerformTrivialCopyPropagation(MachineInstr *MI,
continue;
if (!MRI->constrainRegAttrs(SrcReg, Reg))
continue;
DEBUG(dbgs() << "Coalescing: " << *DefMI);
DEBUG(dbgs() << "*** to: " << *MI);
LLVM_DEBUG(dbgs() << "Coalescing: " << *DefMI);
LLVM_DEBUG(dbgs() << "*** to: " << *MI);
// Propagate SrcReg of copies to MI.
MO.setReg(SrcReg);
MRI->clearKillFlags(SrcReg);
@ -455,13 +455,13 @@ bool MachineCSE::isProfitableToCSE(unsigned CSReg, unsigned Reg,
}
void MachineCSE::EnterScope(MachineBasicBlock *MBB) {
DEBUG(dbgs() << "Entering: " << MBB->getName() << '\n');
LLVM_DEBUG(dbgs() << "Entering: " << MBB->getName() << '\n');
ScopeType *Scope = new ScopeType(VNT);
ScopeMap[MBB] = Scope;
}
void MachineCSE::ExitScope(MachineBasicBlock *MBB) {
DEBUG(dbgs() << "Exiting: " << MBB->getName() << '\n');
LLVM_DEBUG(dbgs() << "Exiting: " << MBB->getName() << '\n');
DenseMap<MachineBasicBlock*, ScopeType*>::iterator SI = ScopeMap.find(MBB);
assert(SI != ScopeMap.end());
delete SI->second;
@ -545,8 +545,8 @@ bool MachineCSE::ProcessBlock(MachineBasicBlock *MBB) {
// Found a common subexpression, eliminate it.
unsigned CSVN = VNT.lookup(MI);
MachineInstr *CSMI = Exps[CSVN];
DEBUG(dbgs() << "Examining: " << *MI);
DEBUG(dbgs() << "*** Found a common subexpression: " << *CSMI);
LLVM_DEBUG(dbgs() << "Examining: " << *MI);
LLVM_DEBUG(dbgs() << "*** Found a common subexpression: " << *CSMI);
// Check if it's profitable to perform this CSE.
bool DoCSE = true;
@ -580,7 +580,7 @@ bool MachineCSE::ProcessBlock(MachineBasicBlock *MBB) {
"Do not CSE physical register defs!");
if (!isProfitableToCSE(NewReg, OldReg, CSMI, MI)) {
DEBUG(dbgs() << "*** Not profitable, avoid CSE!\n");
LLVM_DEBUG(dbgs() << "*** Not profitable, avoid CSE!\n");
DoCSE = false;
break;
}
@ -589,7 +589,8 @@ bool MachineCSE::ProcessBlock(MachineBasicBlock *MBB) {
// within the constraints (register class, bank, or low-level type) of
// the old instruction.
if (!MRI->constrainRegAttrs(NewReg, OldReg)) {
DEBUG(dbgs() << "*** Not the same register constraints, avoid CSE!\n");
LLVM_DEBUG(
dbgs() << "*** Not the same register constraints, avoid CSE!\n");
DoCSE = false;
break;
}

51
llvm/lib/CodeGen/MachineCombiner.cpp
View File

@ -308,8 +308,8 @@ bool MachineCombiner::improvesCriticalPathLen(
unsigned NewRootDepth = getDepth(InsInstrs, InstrIdxForVirtReg, BlockTrace);
unsigned RootDepth = BlockTrace.getInstrCycles(*Root).Depth;
DEBUG(dbgs() << " Dependence data for " << *Root << "\tNewRootDepth: "
<< NewRootDepth << "\tRootDepth: " << RootDepth);
LLVM_DEBUG(dbgs() << " Dependence data for " << *Root << "\tNewRootDepth: "
<< NewRootDepth << "\tRootDepth: " << RootDepth);
// For a transform such as reassociation, the cost equation is
// conservatively calculated so that we must improve the depth (data
@ -317,9 +317,10 @@ bool MachineCombiner::improvesCriticalPathLen(
// Being conservative also protects against inaccuracies in the underlying
// machine trace metrics and CPU models.
if (getCombinerObjective(Pattern) == CombinerObjective::MustReduceDepth) {
DEBUG(dbgs() << "\tIt MustReduceDepth ");
DEBUG(NewRootDepth < RootDepth ? dbgs() << "\t and it does it\n"
: dbgs() << "\t but it does NOT do it\n");
LLVM_DEBUG(dbgs() << "\tIt MustReduceDepth ");
LLVM_DEBUG(NewRootDepth < RootDepth
? dbgs() << "\t and it does it\n"
: dbgs() << "\t but it does NOT do it\n");
return NewRootDepth < RootDepth;
}
@ -336,17 +337,17 @@ bool MachineCombiner::improvesCriticalPathLen(
unsigned NewCycleCount = NewRootDepth + NewRootLatency;
unsigned OldCycleCount =
RootDepth + RootLatency + (SlackIsAccurate ? RootSlack : 0);
DEBUG(dbgs() << "\n\tNewRootLatency: " << NewRootLatency << "\tRootLatency: "
<< RootLatency << "\n\tRootSlack: " << RootSlack
<< " SlackIsAccurate=" << SlackIsAccurate
<< "\n\tNewRootDepth + NewRootLatency = " << NewCycleCount
<< "\n\tRootDepth + RootLatency + RootSlack = "
<< OldCycleCount;);
DEBUG(NewCycleCount <= OldCycleCount
? dbgs() << "\n\t It IMPROVES PathLen because"
: dbgs() << "\n\t It DOES NOT improve PathLen because");
DEBUG(dbgs() << "\n\t\tNewCycleCount = " << NewCycleCount
<< ", OldCycleCount = " << OldCycleCount << "\n");
LLVM_DEBUG(dbgs() << "\n\tNewRootLatency: " << NewRootLatency
<< "\tRootLatency: " << RootLatency << "\n\tRootSlack: "
<< RootSlack << " SlackIsAccurate=" << SlackIsAccurate
<< "\n\tNewRootDepth + NewRootLatency = " << NewCycleCount
<< "\n\tRootDepth + RootLatency + RootSlack = "
<< OldCycleCount;);
LLVM_DEBUG(NewCycleCount <= OldCycleCount
? dbgs() << "\n\t It IMPROVES PathLen because"
: dbgs() << "\n\t It DOES NOT improve PathLen because");
LLVM_DEBUG(dbgs() << "\n\t\tNewCycleCount = " << NewCycleCount
<< ", OldCycleCount = " << OldCycleCount << "\n");
return NewCycleCount <= OldCycleCount;
}
@ -392,10 +393,10 @@ bool MachineCombiner::preservesResourceLen(
unsigned ResLenAfterCombine =
BlockTrace.getResourceLength(MBBarr, MSCInsArr, MSCDelArr);
DEBUG(dbgs() << "\t\tResource length before replacement: "
<< ResLenBeforeCombine << " and after: " << ResLenAfterCombine
<< "\n";);
DEBUG(
LLVM_DEBUG(dbgs() << "\t\tResource length before replacement: "
<< ResLenBeforeCombine
<< " and after: " << ResLenAfterCombine << "\n";);
LLVM_DEBUG(
ResLenAfterCombine <= ResLenBeforeCombine
? dbgs() << "\t\t As result it IMPROVES/PRESERVES Resource Length\n"
: dbgs() << "\t\t As result it DOES NOT improve/preserve Resource "
@ -492,7 +493,7 @@ void MachineCombiner::verifyPatternOrder(
/// sequence is shorter.
bool MachineCombiner::combineInstructions(MachineBasicBlock *MBB) {
bool Changed = false;
DEBUG(dbgs() << "Combining MBB " << MBB->getName() << "\n");
LLVM_DEBUG(dbgs() << "Combining MBB " << MBB->getName() << "\n");
bool IncrementalUpdate = false;
auto BlockIter = MBB->begin();
@ -555,7 +556,7 @@ bool MachineCombiner::combineInstructions(MachineBasicBlock *MBB) {
if (!NewInstCount)
continue;
DEBUG(if (dump_intrs) {
LLVM_DEBUG(if (dump_intrs) {
dbgs() << "\tFor the Pattern (" << (int)P << ") these instructions could be removed\n";
for (auto const *InstrPtr : DelInstrs) {
dbgs() << "\t\t" << STI->getSchedInfoStr(*InstrPtr) << ": ";
@ -640,9 +641,11 @@ bool MachineCombiner::runOnMachineFunction(MachineFunction &MF) {
MinInstr = nullptr;
OptSize = MF.getFunction().optForSize();
DEBUG(dbgs() << getPassName() << ": " << MF.getName() << '\n');
LLVM_DEBUG(dbgs() << getPassName() << ": " << MF.getName() << '\n');
if (!TII->useMachineCombiner()) {
DEBUG(dbgs() << " Skipping pass: Target does not support machine combiner\n");
LLVM_DEBUG(
dbgs()
<< " Skipping pass: Target does not support machine combiner\n");
return false;
}

34
llvm/lib/CodeGen/MachineCopyPropagation.cpp
View File

@ -181,7 +181,8 @@ void MachineCopyPropagation::ReadRegister(unsigned Reg) {
for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
Reg2MIMap::iterator CI = CopyMap.find(*AI);
if (CI != CopyMap.end()) {
DEBUG(dbgs() << "MCP: Copy is used - not dead: "; CI->second->dump());
LLVM_DEBUG(dbgs() << "MCP: Copy is used - not dead: ";
CI->second->dump());
MaybeDeadCopies.remove(CI->second);
}
}
@ -229,7 +230,7 @@ bool MachineCopyPropagation::eraseIfRedundant(MachineInstr &Copy, unsigned Src,
if (!isNopCopy(PrevCopy, Src, Def, TRI))
return false;
DEBUG(dbgs() << "MCP: copy is a NOP, removing: "; Copy.dump());
LLVM_DEBUG(dbgs() << "MCP: copy is a NOP, removing: "; Copy.dump());
// Copy was redundantly redefining either Src or Def. Remove earlier kill
// flags between Copy and PrevCopy because the value will be reused now.
@ -351,8 +352,9 @@ void MachineCopyPropagation::forwardUses(MachineInstr &MI) {
// FIXME: Don't handle partial uses of wider COPYs yet.
if (MOUse.getReg() != CopyDstReg) {
DEBUG(dbgs() << "MCP: FIXME! Not forwarding COPY to sub-register use:\n "
<< MI);
LLVM_DEBUG(
dbgs() << "MCP: FIXME! Not forwarding COPY to sub-register use:\n "
<< MI);
continue;
}
@ -367,20 +369,20 @@ void MachineCopyPropagation::forwardUses(MachineInstr &MI) {
continue;
if (!DebugCounter::shouldExecute(FwdCounter)) {
DEBUG(dbgs() << "MCP: Skipping forwarding due to debug counter:\n "
<< MI);
LLVM_DEBUG(dbgs() << "MCP: Skipping forwarding due to debug counter:\n "
<< MI);
continue;
}
DEBUG(dbgs() << "MCP: Replacing " << printReg(MOUse.getReg(), TRI)
<< "\n with " << printReg(CopySrcReg, TRI) << "\n in "
<< MI << " from " << Copy);
LLVM_DEBUG(dbgs() << "MCP: Replacing " << printReg(MOUse.getReg(), TRI)
<< "\n with " << printReg(CopySrcReg, TRI)
<< "\n in " << MI << " from " << Copy);
MOUse.setReg(CopySrcReg);
if (!CopySrc.isRenamable())
MOUse.setIsRenamable(false);
DEBUG(dbgs() << "MCP: After replacement: " << MI << "\n");
LLVM_DEBUG(dbgs() << "MCP: After replacement: " << MI << "\n");
// Clear kill markers that may have been invalidated.
for (MachineInstr &KMI :
@ -393,7 +395,7 @@ void MachineCopyPropagation::forwardUses(MachineInstr &MI) {
}
void MachineCopyPropagation::CopyPropagateBlock(MachineBasicBlock &MBB) {
DEBUG(dbgs() << "MCP: CopyPropagateBlock " << MBB.getName() << "\n");
LLVM_DEBUG(dbgs() << "MCP: CopyPropagateBlock " << MBB.getName() << "\n");
for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ) {
MachineInstr *MI = &*I;
@ -444,7 +446,7 @@ void MachineCopyPropagation::CopyPropagateBlock(MachineBasicBlock &MBB) {
ReadRegister(Reg);
}
DEBUG(dbgs() << "MCP: Copy is a deletion candidate: "; MI->dump());
LLVM_DEBUG(dbgs() << "MCP: Copy is a deletion candidate: "; MI->dump());
// Copy is now a candidate for deletion.
if (!MRI->isReserved(Def))
@ -536,8 +538,8 @@ void MachineCopyPropagation::CopyPropagateBlock(MachineBasicBlock &MBB) {
continue;
}
DEBUG(dbgs() << "MCP: Removing copy due to regmask clobbering: ";
MaybeDead->dump());
LLVM_DEBUG(dbgs() << "MCP: Removing copy due to regmask clobbering: ";
MaybeDead->dump());
// erase() will return the next valid iterator pointing to the next
// element after the erased one.
@ -569,8 +571,8 @@ void MachineCopyPropagation::CopyPropagateBlock(MachineBasicBlock &MBB) {
// since we don't want to trust live-in lists.
if (MBB.succ_empty()) {
for (MachineInstr *MaybeDead : MaybeDeadCopies) {
DEBUG(dbgs() << "MCP: Removing copy due to no live-out succ: ";
MaybeDead->dump());
LLVM_DEBUG(dbgs() << "MCP: Removing copy due to no live-out succ: ";
MaybeDead->dump());
assert(!MRI->isReserved(MaybeDead->getOperand(0).getReg()));
MaybeDead->eraseFromParent();
Changed = true;

6
llvm/lib/CodeGen/MachineFrameInfo.cpp
View File

@ -41,9 +41,9 @@ static inline unsigned clampStackAlignment(bool ShouldClamp, unsigned Align,
unsigned StackAlign) {
if (!ShouldClamp || Align <= StackAlign)
return Align;
DEBUG(dbgs() << "Warning: requested alignment " << Align
<< " exceeds the stack alignment " << StackAlign
<< " when stack realignment is off" << '\n');
LLVM_DEBUG(dbgs() << "Warning: requested alignment " << Align
<< " exceeds the stack alignment " << StackAlign
<< " when stack realignment is off" << '\n');
return StackAlign;
}

45
llvm/lib/CodeGen/MachineLICM.cpp
View File

@ -319,10 +319,10 @@ bool MachineLICMBase::runOnMachineFunction(MachineFunction &MF) {
PreRegAlloc = MRI->isSSA();
if (PreRegAlloc)
DEBUG(dbgs() << "******** Pre-regalloc Machine LICM: ");
LLVM_DEBUG(dbgs() << "******** Pre-regalloc Machine LICM: ");
else
DEBUG(dbgs() << "******** Post-regalloc Machine LICM: ");
DEBUG(dbgs() << MF.getName() << " ********\n");
LLVM_DEBUG(dbgs() << "******** Post-regalloc Machine LICM: ");
LLVM_DEBUG(dbgs() << MF.getName() << " ********\n");
if (PreRegAlloc) {
// Estimate register pressure during pre-regalloc pass.
@ -591,8 +591,9 @@ void MachineLICMBase::HoistPostRA(MachineInstr *MI, unsigned Def) {
// Now move the instructions to the predecessor, inserting it before any
// terminator instructions.
DEBUG(dbgs() << "Hoisting to " << printMBBReference(*Preheader) << " from "
<< printMBBReference(*MI->getParent()) << ": " << *MI);
LLVM_DEBUG(dbgs() << "Hoisting to " << printMBBReference(*Preheader)
<< " from " << printMBBReference(*MI->getParent()) << ": "
<< *MI);
// Splice the instruction to the preheader.
MachineBasicBlock *MBB = MI->getParent();
@ -629,14 +630,14 @@ bool MachineLICMBase::IsGuaranteedToExecute(MachineBasicBlock *BB) {
}
void MachineLICMBase::EnterScope(MachineBasicBlock *MBB) {
DEBUG(dbgs() << "Entering " << printMBBReference(*MBB) << '\n');
LLVM_DEBUG(dbgs() << "Entering " << printMBBReference(*MBB) << '\n');
// Remember livein register pressure.
BackTrace.push_back(RegPressure);
}
void MachineLICMBase::ExitScope(MachineBasicBlock *MBB) {
DEBUG(dbgs() << "Exiting " << printMBBReference(*MBB) << '\n');
LLVM_DEBUG(dbgs() << "Exiting " << printMBBReference(*MBB) << '\n');
BackTrace.pop_back();
}
@ -1208,7 +1209,7 @@ bool MachineLICMBase::IsProfitableToHoist(MachineInstr &MI) {
// Don't hoist a cheap instruction if it would create a copy in the loop.
if (CheapInstr && CreatesCopy) {
DEBUG(dbgs() << "Won't hoist cheap instr with loop PHI use: " << MI);
LLVM_DEBUG(dbgs() << "Won't hoist cheap instr with loop PHI use: " << MI);
return false;
}
@ -1227,7 +1228,7 @@ bool MachineLICMBase::IsProfitableToHoist(MachineInstr &MI) {
if (!TargetRegisterInfo::isVirtualRegister(Reg))
continue;
if (MO.isDef() && HasHighOperandLatency(MI, i, Reg)) {
DEBUG(dbgs() << "Hoist High Latency: " << MI);
LLVM_DEBUG(dbgs() << "Hoist High Latency: " << MI);
++NumHighLatency;
return true;
}
@ -1245,14 +1246,14 @@ bool MachineLICMBase::IsProfitableToHoist(MachineInstr &MI) {
// Visit BBs from header to current BB, if hoisting this doesn't cause
// high register pressure, then it's safe to proceed.
if (!CanCauseHighRegPressure(Cost, CheapInstr)) {
DEBUG(dbgs() << "Hoist non-reg-pressure: " << MI);
LLVM_DEBUG(dbgs() << "Hoist non-reg-pressure: " << MI);
++NumLowRP;
return true;
}
// Don't risk increasing register pressure if it would create copies.
if (CreatesCopy) {
DEBUG(dbgs() << "Won't hoist instr with loop PHI use: " << MI);
LLVM_DEBUG(dbgs() << "Won't hoist instr with loop PHI use: " << MI);
return false;
}
@ -1261,7 +1262,7 @@ bool MachineLICMBase::IsProfitableToHoist(MachineInstr &MI) {
// conservative.
if (AvoidSpeculation &&
(!IsGuaranteedToExecute(MI.getParent()) && !MayCSE(&MI))) {
DEBUG(dbgs() << "Won't speculate: " << MI);
LLVM_DEBUG(dbgs() << "Won't speculate: " << MI);
return false;
}
@ -1269,7 +1270,7 @@ bool MachineLICMBase::IsProfitableToHoist(MachineInstr &MI) {
// to be remat'ed.
if (!TII->isTriviallyReMaterializable(MI, AA) &&
!MI.isDereferenceableInvariantLoad(AA)) {
DEBUG(dbgs() << "Can't remat / high reg-pressure: " << MI);
LLVM_DEBUG(dbgs() << "Can't remat / high reg-pressure: " << MI);
return false;
}
@ -1366,7 +1367,7 @@ bool MachineLICMBase::EliminateCSE(MachineInstr *MI,
return false;
if (const MachineInstr *Dup = LookForDuplicate(MI, CI->second)) {
DEBUG(dbgs() << "CSEing " << *MI << " with " << *Dup);
LLVM_DEBUG(dbgs() << "CSEing " << *MI << " with " << *Dup);
// Replace virtual registers defined by MI by their counterparts defined
// by Dup.
@ -1446,14 +1447,14 @@ bool MachineLICMBase::Hoist(MachineInstr *MI, MachineBasicBlock *Preheader) {
// Now move the instructions to the predecessor, inserting it before any
// terminator instructions.
DEBUG({
dbgs() << "Hoisting " << *MI;
if (MI->getParent()->getBasicBlock())
dbgs() << " from " << printMBBReference(*MI->getParent());
if (Preheader->getBasicBlock())
dbgs() << " to " << printMBBReference(*Preheader);
dbgs() << "\n";
});
LLVM_DEBUG({
dbgs() << "Hoisting " << *MI;
if (MI->getParent()->getBasicBlock())
dbgs() << " from " << printMBBReference(*MI->getParent());
if (Preheader->getBasicBlock())
dbgs() << " to " << printMBBReference(*Preheader);
dbgs() << "\n";
});
// If this is the first instruction being hoisted to the preheader,
// initialize the CSE map with potential common expressions.

17
llvm/lib/CodeGen/MachineOutliner.cpp
View File

@ -1112,11 +1112,11 @@ void MachineOutliner::prune(Candidate &C,
// Remove C from the CandidateList.
C.InCandidateList = false;
DEBUG(dbgs() << "- Removed a Candidate \n";
dbgs() << "--- Num fns left for candidate: " << F.getOccurrenceCount()
<< "\n";
dbgs() << "--- Candidate's functions's benefit: " << F.getBenefit()
<< "\n";);
LLVM_DEBUG(dbgs() << "- Removed a Candidate \n";
dbgs() << "--- Num fns left for candidate: "
<< F.getOccurrenceCount() << "\n";
dbgs() << "--- Candidate's functions's benefit: " << F.getBenefit()
<< "\n";);
}
void MachineOutliner::pruneOverlaps(
@ -1441,7 +1441,7 @@ bool MachineOutliner::outline(
NumOutlined++;
}
DEBUG(dbgs() << "OutlinedSomething = " << OutlinedSomething << "\n";);
LLVM_DEBUG(dbgs() << "OutlinedSomething = " << OutlinedSomething << "\n";);
return OutlinedSomething;
}
@ -1461,8 +1461,9 @@ bool MachineOutliner::runOnModule(Module &M) {
// Does the target implement the MachineOutliner? If it doesn't, quit here.
if (!TII->useMachineOutliner()) {
// No. So we're done.
DEBUG(dbgs()
<< "Skipping pass: Target does not support the MachineOutliner.\n");
LLVM_DEBUG(
dbgs()
<< "Skipping pass: Target does not support the MachineOutliner.\n");
return false;
}

80
llvm/lib/CodeGen/MachinePipeliner.cpp
View File

@ -886,7 +886,7 @@ void SwingSchedulerDAG::schedule() {
Topo.InitDAGTopologicalSorting();
postprocessDAG();
changeDependences();
DEBUG({
LLVM_DEBUG({
for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
SUnits[su].dumpAll(this);
});
@ -906,8 +906,8 @@ void SwingSchedulerDAG::schedule() {
RecMII = 0;
MII = std::max(ResMII, RecMII);
DEBUG(dbgs() << "MII = " << MII << " (rec=" << RecMII << ", res=" << ResMII
<< ")\n");
LLVM_DEBUG(dbgs() << "MII = " << MII << " (rec=" << RecMII
<< ", res=" << ResMII << ")\n");
// Can't schedule a loop without a valid MII.
if (MII == 0)
@ -925,7 +925,7 @@ void SwingSchedulerDAG::schedule() {
checkNodeSets(NodeSets);
DEBUG({
LLVM_DEBUG({
for (auto &I : NodeSets) {
dbgs() << " Rec NodeSet ";
I.dump();
@ -938,7 +938,7 @@ void SwingSchedulerDAG::schedule() {
removeDuplicateNodes(NodeSets);
DEBUG({
LLVM_DEBUG({
for (auto &I : NodeSets) {
dbgs() << " NodeSet ";
I.dump();
@ -1634,7 +1634,7 @@ static bool ignoreDependence(const SDep &D, bool isPred) {
void SwingSchedulerDAG::computeNodeFunctions(NodeSetType &NodeSets) {
ScheduleInfo.resize(SUnits.size());
DEBUG({
LLVM_DEBUG({
for (ScheduleDAGTopologicalSort::const_iterator I = Topo.begin(),
E = Topo.end();
I != E; ++I) {
@ -1696,7 +1696,7 @@ void SwingSchedulerDAG::computeNodeFunctions(NodeSetType &NodeSets) {
for (NodeSet &I : NodeSets)
I.computeNodeSetInfo(this);
DEBUG({
LLVM_DEBUG({
for (unsigned i = 0; i < SUnits.size(); i++) {
dbgs() << "\tNode " << i << ":\n";
dbgs() << "\t ASAP = " << getASAP(&SUnits[i]) << "\n";
@ -1883,9 +1883,10 @@ void SwingSchedulerDAG::registerPressureFilter(NodeSetType &NodeSets) {
CriticalPSets,
RecRegPressure.MaxSetPressure);
if (RPDelta.Excess.isValid()) {
DEBUG(dbgs() << "Excess register pressure: SU(" << SU->NodeNum << ") "
<< TRI->getRegPressureSetName(RPDelta.Excess.getPSet())
<< ":" << RPDelta.Excess.getUnitInc());
LLVM_DEBUG(
dbgs() << "Excess register pressure: SU(" << SU->NodeNum << ") "
<< TRI->getRegPressureSetName(RPDelta.Excess.getPSet())
<< ":" << RPDelta.Excess.getUnitInc());
NS.setExceedPressure(SU);
break;
}
@ -1936,7 +1937,7 @@ void SwingSchedulerDAG::checkNodeSets(NodeSetType &NodeSets) {
return;
}
NodeSets.clear();
DEBUG(dbgs() << "Clear recurrence node-sets\n");
LLVM_DEBUG(dbgs() << "Clear recurrence node-sets\n");
return;
}
@ -2082,28 +2083,28 @@ void SwingSchedulerDAG::computeNodeOrder(NodeSetType &NodeSets) {
NodeOrder.clear();
for (auto &Nodes : NodeSets) {
DEBUG(dbgs() << "NodeSet size " << Nodes.size() << "\n");
LLVM_DEBUG(dbgs() << "NodeSet size " << Nodes.size() << "\n");
OrderKind Order;
SmallSetVector<SUnit *, 8> N;
if (pred_L(NodeOrder, N) && isSubset(N, Nodes)) {
R.insert(N.begin(), N.end());
Order = BottomUp;
DEBUG(dbgs() << " Bottom up (preds) ");
LLVM_DEBUG(dbgs() << " Bottom up (preds) ");
} else if (succ_L(NodeOrder, N) && isSubset(N, Nodes)) {
R.insert(N.begin(), N.end());
Order = TopDown;
DEBUG(dbgs() << " Top down (succs) ");
LLVM_DEBUG(dbgs() << " Top down (succs) ");
} else if (isIntersect(N, Nodes, R)) {
// If some of the successors are in the existing node-set, then use the
// top-down ordering.
Order = TopDown;
DEBUG(dbgs() << " Top down (intersect) ");
LLVM_DEBUG(dbgs() << " Top down (intersect) ");
} else if (NodeSets.size() == 1) {
for (auto &N : Nodes)
if (N->Succs.size() == 0)
R.insert(N);
Order = BottomUp;
DEBUG(dbgs() << " Bottom up (all) ");
LLVM_DEBUG(dbgs() << " Bottom up (all) ");
} else {
// Find the node with the highest ASAP.
SUnit *maxASAP = nullptr;
@ -2114,7 +2115,7 @@ void SwingSchedulerDAG::computeNodeOrder(NodeSetType &NodeSets) {
}
R.insert(maxASAP);
Order = BottomUp;
DEBUG(dbgs() << " Bottom up (default) ");
LLVM_DEBUG(dbgs() << " Bottom up (default) ");
}
while (!R.empty()) {
@ -2137,7 +2138,7 @@ void SwingSchedulerDAG::computeNodeOrder(NodeSetType &NodeSets) {
maxHeight = I;
}
NodeOrder.insert(maxHeight);
DEBUG(dbgs() << maxHeight->NodeNum << " ");
LLVM_DEBUG(dbgs() << maxHeight->NodeNum << " ");
R.remove(maxHeight);
for (const auto &I : maxHeight->Succs) {
if (Nodes.count(I.getSUnit()) == 0)
@ -2160,7 +2161,7 @@ void SwingSchedulerDAG::computeNodeOrder(NodeSetType &NodeSets) {
}
}
Order = BottomUp;
DEBUG(dbgs() << "\n Switching order to bottom up ");
LLVM_DEBUG(dbgs() << "\n Switching order to bottom up ");
SmallSetVector<SUnit *, 8> N;
if (pred_L(NodeOrder, N, &Nodes))
R.insert(N.begin(), N.end());
@ -2182,7 +2183,7 @@ void SwingSchedulerDAG::computeNodeOrder(NodeSetType &NodeSets) {
maxDepth = I;
}
NodeOrder.insert(maxDepth);
DEBUG(dbgs() << maxDepth->NodeNum << " ");
LLVM_DEBUG(dbgs() << maxDepth->NodeNum << " ");
R.remove(maxDepth);
if (Nodes.isExceedSU(maxDepth)) {
Order = TopDown;
@ -2209,16 +2210,16 @@ void SwingSchedulerDAG::computeNodeOrder(NodeSetType &NodeSets) {
}
}
Order = TopDown;
DEBUG(dbgs() << "\n Switching order to top down ");
LLVM_DEBUG(dbgs() << "\n Switching order to top down ");
SmallSetVector<SUnit *, 8> N;
if (succ_L(NodeOrder, N, &Nodes))
R.insert(N.begin(), N.end());
}
}
DEBUG(dbgs() << "\nDone with Nodeset\n");
LLVM_DEBUG(dbgs() << "\nDone with Nodeset\n");
}
DEBUG({
LLVM_DEBUG({
dbgs() << "Node order: ";
for (SUnit *I : NodeOrder)
dbgs() << " " << I->NodeNum << " ";
@ -2237,7 +2238,7 @@ bool SwingSchedulerDAG::schedulePipeline(SMSchedule &Schedule) {
for (unsigned II = MII; II < MII + 10 && !scheduleFound; ++II) {
Schedule.reset();
Schedule.setInitiationInterval(II);
DEBUG(dbgs() << "Try to schedule with " << II << "\n");
LLVM_DEBUG(dbgs() << "Try to schedule with " << II << "\n");
SetVector<SUnit *>::iterator NI = NodeOrder.begin();
SetVector<SUnit *>::iterator NE = NodeOrder.end();
@ -2254,12 +2255,12 @@ bool SwingSchedulerDAG::schedulePipeline(SMSchedule &Schedule) {
int SchedStart = INT_MIN;
Schedule.computeStart(SU, &EarlyStart, &LateStart, &SchedEnd, &SchedStart,
II, this);
DEBUG({
LLVM_DEBUG({
dbgs() << "Inst (" << SU->NodeNum << ") ";
SU->getInstr()->dump();
dbgs() << "\n";
});
DEBUG({
LLVM_DEBUG({
dbgs() << "\tes: " << EarlyStart << " ls: " << LateStart
<< " me: " << SchedEnd << " ms: " << SchedStart << "\n";
});
@ -2295,7 +2296,7 @@ bool SwingSchedulerDAG::schedulePipeline(SMSchedule &Schedule) {
Schedule.getMaxStageCount() > (unsigned)SwpMaxStages)
scheduleFound = false;
DEBUG({
LLVM_DEBUG({
if (!scheduleFound)
dbgs() << "\tCan't schedule\n";
});
@ -2306,7 +2307,7 @@ bool SwingSchedulerDAG::schedulePipeline(SMSchedule &Schedule) {
scheduleFound = Schedule.isValidSchedule(this);
}
DEBUG(dbgs() << "Schedule Found? " << scheduleFound << "\n");
LLVM_DEBUG(dbgs() << "Schedule Found? " << scheduleFound << "\n");
if (scheduleFound)
Schedule.finalizeSchedule(this);
@ -2376,7 +2377,7 @@ void SwingSchedulerDAG::generatePipelinedLoop(SMSchedule &Schedule) {
generatePhis(KernelBB, PrologBBs.back(), KernelBB, KernelBB, Schedule, VRMap,
InstrMap, MaxStageCount, MaxStageCount, false);
DEBUG(dbgs() << "New block\n"; KernelBB->dump(););
LLVM_DEBUG(dbgs() << "New block\n"; KernelBB->dump(););
SmallVector<MachineBasicBlock *, 4> EpilogBBs;
// Generate the epilog instructions to complete the pipeline.
@ -2445,7 +2446,7 @@ void SwingSchedulerDAG::generateProlog(SMSchedule &Schedule, unsigned LastStage,
}
}
rewritePhiValues(NewBB, i, Schedule, VRMap, InstrMap);
DEBUG({
LLVM_DEBUG({
dbgs() << "prolog:\n";
NewBB->dump();
});
@ -2527,7 +2528,7 @@ void SwingSchedulerDAG::generateEpilog(SMSchedule &Schedule, unsigned LastStage,
InstrMap, LastStage, EpilogStage, i == 1);
PredBB = NewBB;
DEBUG({
LLVM_DEBUG({
dbgs() << "epilog:\n";
NewBB->dump();
});
@ -3625,7 +3626,7 @@ bool SMSchedule::insert(SUnit *SU, int StartCycle, int EndCycle, int II) {
}
if (ST.getInstrInfo()->isZeroCost(SU->getInstr()->getOpcode()) ||
Resources->canReserveResources(*SU->getInstr())) {
DEBUG({
LLVM_DEBUG({
dbgs() << "\tinsert at cycle " << curCycle << " ";
SU->getInstr()->dump();
});
@ -3638,7 +3639,7 @@ bool SMSchedule::insert(SUnit *SU, int StartCycle, int EndCycle, int II) {
FirstCycle = curCycle;
return true;
}
DEBUG({
LLVM_DEBUG({
dbgs() << "\tfailed to insert at cycle " << curCycle << " ";
SU->getInstr()->dump();
});
@ -4034,18 +4035,19 @@ void SwingSchedulerDAG::checkValidNodeOrder(const NodeSetType &Circuits) const {
Circuits.begin(), Circuits.end(),
[SU](const NodeSet &Circuit) { return Circuit.count(SU); });
if (InCircuit)
DEBUG(dbgs() << "In a circuit, predecessor ";);
LLVM_DEBUG(dbgs() << "In a circuit, predecessor ";);
else {
Valid = false;
NumNodeOrderIssues++;
DEBUG(dbgs() << "Predecessor ";);
LLVM_DEBUG(dbgs() << "Predecessor ";);
}
DEBUG(dbgs() << Pred->NodeNum << " and successor " << Succ->NodeNum
<< " are scheduled before node " << SU->NodeNum << "\n";);
LLVM_DEBUG(dbgs() << Pred->NodeNum << " and successor " << Succ->NodeNum
<< " are scheduled before node " << SU->NodeNum
<< "\n";);
}
}
DEBUG({
LLVM_DEBUG({
if (!Valid)
dbgs() << "Invalid node order found!\n";
});
@ -4188,7 +4190,7 @@ void SMSchedule::finalizeSchedule(SwingSchedulerDAG *SSD) {
SSD->fixupRegisterOverlaps(cycleInstrs);
}
DEBUG(dump(););
LLVM_DEBUG(dump(););
}
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)

2
llvm/lib/CodeGen/MachineRegionInfo.cpp
View File

@ -90,7 +90,7 @@ bool MachineRegionInfoPass::runOnMachineFunction(MachineFunction &F) {
RI.recalculate(F, DT, PDT, DF);
DEBUG(RI.dump());
LLVM_DEBUG(RI.dump());
return false;
}

2
llvm/lib/CodeGen/MachineSSAUpdater.cpp
View File

@ -204,7 +204,7 @@ unsigned MachineSSAUpdater::GetValueInMiddleOfBlock(MachineBasicBlock *BB) {
// If the client wants to know about all new instructions, tell it.
if (InsertedPHIs) InsertedPHIs->push_back(InsertedPHI);
DEBUG(dbgs() << " Inserted PHI: " << *InsertedPHI << "\n");
LLVM_DEBUG(dbgs() << " Inserted PHI: " << *InsertedPHI << "\n");
return InsertedPHI->getOperand(0).getReg();
}

362
llvm/lib/CodeGen/MachineScheduler.cpp
View File

@ -361,7 +361,7 @@ bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) {
} else if (!mf.getSubtarget().enableMachineScheduler())
return false;
DEBUG(dbgs() << "Before MISched:\n"; mf.print(dbgs()));
LLVM_DEBUG(dbgs() << "Before MISched:\n"; mf.print(dbgs()));
// Initialize the context of the pass.
MF = &mf;
@ -373,7 +373,7 @@ bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) {
LIS = &getAnalysis<LiveIntervals>();
if (VerifyScheduling) {
DEBUG(LIS->dump());
LLVM_DEBUG(LIS->dump());
MF->verify(this, "Before machine scheduling.");
}
RegClassInfo->runOnMachineFunction(*MF);
@ -383,7 +383,7 @@ bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) {
std::unique_ptr<ScheduleDAGInstrs> Scheduler(createMachineScheduler());
scheduleRegions(*Scheduler, false);
DEBUG(LIS->dump());
LLVM_DEBUG(LIS->dump());
if (VerifyScheduling)
MF->verify(this, "After machine scheduling.");
return true;
@ -397,10 +397,10 @@ bool PostMachineScheduler::runOnMachineFunction(MachineFunction &mf) {
if (!EnablePostRAMachineSched)
return false;
} else if (!mf.getSubtarget().enablePostRAScheduler()) {
DEBUG(dbgs() << "Subtarget disables post-MI-sched.\n");
LLVM_DEBUG(dbgs() << "Subtarget disables post-MI-sched.\n");
return false;
}
DEBUG(dbgs() << "Before post-MI-sched:\n"; mf.print(dbgs()));
LLVM_DEBUG(dbgs() << "Before post-MI-sched:\n"; mf.print(dbgs()));
// Initialize the context of the pass.
MF = &mf;
@ -548,12 +548,13 @@ void MachineSchedulerBase::scheduleRegions(ScheduleDAGInstrs &Scheduler,
Scheduler.exitRegion();
continue;
}
DEBUG(dbgs() << "********** MI Scheduling **********\n");
DEBUG(dbgs() << MF->getName() << ":" << printMBBReference(*MBB) << " "
<< MBB->getName() << "\n From: " << *I << " To: ";
if (RegionEnd != MBB->end()) dbgs() << *RegionEnd;
else dbgs() << "End";
dbgs() << " RegionInstrs: " << NumRegionInstrs << '\n');
LLVM_DEBUG(dbgs() << "********** MI Scheduling **********\n");
LLVM_DEBUG(dbgs() << MF->getName() << ":" << printMBBReference(*MBB)
<< " " << MBB->getName() << "\n From: " << *I
<< " To: ";
if (RegionEnd != MBB->end()) dbgs() << *RegionEnd;
else dbgs() << "End";
dbgs() << " RegionInstrs: " << NumRegionInstrs << '\n');
if (DumpCriticalPathLength) {
errs() << MF->getName();
errs() << ":%bb. " << MBB->getNumber();
@ -750,8 +751,8 @@ bool ScheduleDAGMI::checkSchedLimit() {
/// does not consider liveness or register pressure. It is useful for PostRA
/// scheduling and potentially other custom schedulers.
void ScheduleDAGMI::schedule() {
DEBUG(dbgs() << "ScheduleDAGMI::schedule starting\n");
DEBUG(SchedImpl->dumpPolicy());
LLVM_DEBUG(dbgs() << "ScheduleDAGMI::schedule starting\n");
LLVM_DEBUG(SchedImpl->dumpPolicy());
// Build the DAG.
buildSchedGraph(AA);
@ -763,14 +764,10 @@ void ScheduleDAGMI::schedule() {
SmallVector<SUnit*, 8> TopRoots, BotRoots;
findRootsAndBiasEdges(TopRoots, BotRoots);
DEBUG(
if (EntrySU.getInstr() != nullptr)
EntrySU.dumpAll(this);
for (const SUnit &SU : SUnits)
SU.dumpAll(this);
if (ExitSU.getInstr() != nullptr)
ExitSU.dumpAll(this);
);
LLVM_DEBUG(if (EntrySU.getInstr() != nullptr) EntrySU.dumpAll(this);
for (const SUnit &SU
: SUnits) SU.dumpAll(this);
if (ExitSU.getInstr() != nullptr) ExitSU.dumpAll(this););
if (ViewMISchedDAGs) viewGraph();
// Initialize the strategy before modifying the DAG.
@ -782,7 +779,7 @@ void ScheduleDAGMI::schedule() {
bool IsTopNode = false;
while (true) {
DEBUG(dbgs() << "** ScheduleDAGMI::schedule picking next node\n");
LLVM_DEBUG(dbgs() << "** ScheduleDAGMI::schedule picking next node\n");
SUnit *SU = SchedImpl->pickNode(IsTopNode);
if (!SU) break;
@ -822,7 +819,7 @@ void ScheduleDAGMI::schedule() {
placeDebugValues();
DEBUG({
LLVM_DEBUG({
dbgs() << "*** Final schedule for "
<< printMBBReference(*begin()->getParent()) << " ***\n";
dumpSchedule();
@ -1017,7 +1014,7 @@ void ScheduleDAGMILive::initRegPressure() {
// Close the RPTracker to finalize live ins.
RPTracker.closeRegion();
DEBUG(RPTracker.dump());
LLVM_DEBUG(RPTracker.dump());
// Initialize the live ins and live outs.
TopRPTracker.addLiveRegs(RPTracker.getPressure().LiveInRegs);
@ -1032,8 +1029,8 @@ void ScheduleDAGMILive::initRegPressure() {
BotRPTracker.initLiveThru(RPTracker);
if (!BotRPTracker.getLiveThru().empty()) {
TopRPTracker.initLiveThru(BotRPTracker.getLiveThru());
DEBUG(dbgs() << "Live Thru: ";
dumpRegSetPressure(BotRPTracker.getLiveThru(), TRI));
LLVM_DEBUG(dbgs() << "Live Thru: ";
dumpRegSetPressure(BotRPTracker.getLiveThru(), TRI));
};
// For each live out vreg reduce the pressure change associated with other
@ -1047,12 +1044,10 @@ void ScheduleDAGMILive::initRegPressure() {
updatePressureDiffs(LiveUses);
}
DEBUG(
dbgs() << "Top Pressure:\n";
dumpRegSetPressure(TopRPTracker.getRegSetPressureAtPos(), TRI);
dbgs() << "Bottom Pressure:\n";
dumpRegSetPressure(BotRPTracker.getRegSetPressureAtPos(), TRI);
);
LLVM_DEBUG(dbgs() << "Top Pressure:\n";
dumpRegSetPressure(TopRPTracker.getRegSetPressureAtPos(), TRI);
dbgs() << "Bottom Pressure:\n";
dumpRegSetPressure(BotRPTracker.getRegSetPressureAtPos(), TRI););
assert((BotRPTracker.getPos() == RegionEnd ||
(RegionEnd->isDebugInstr() &&
@ -1067,17 +1062,16 @@ void ScheduleDAGMILive::initRegPressure() {
for (unsigned i = 0, e = RegionPressure.size(); i < e; ++i) {
unsigned Limit = RegClassInfo->getRegPressureSetLimit(i);
if (RegionPressure[i] > Limit) {
DEBUG(dbgs() << TRI->getRegPressureSetName(i)
<< " Limit " << Limit
<< " Actual " << RegionPressure[i] << "\n");
LLVM_DEBUG(dbgs() << TRI->getRegPressureSetName(i) << " Limit " << Limit
<< " Actual " << RegionPressure[i] << "\n");
RegionCriticalPSets.push_back(PressureChange(i));
}
}
DEBUG(dbgs() << "Excess PSets: ";
for (const PressureChange &RCPS : RegionCriticalPSets)
dbgs() << TRI->getRegPressureSetName(
RCPS.getPSet()) << " ";
dbgs() << "\n");
LLVM_DEBUG(dbgs() << "Excess PSets: ";
for (const PressureChange &RCPS
: RegionCriticalPSets) dbgs()
<< TRI->getRegPressureSetName(RCPS.getPSet()) << " ";
dbgs() << "\n");
}
void ScheduleDAGMILive::
@ -1098,10 +1092,11 @@ updateScheduledPressure(const SUnit *SU,
}
unsigned Limit = RegClassInfo->getRegPressureSetLimit(ID);
if (NewMaxPressure[ID] >= Limit - 2) {
DEBUG(dbgs() << " " << TRI->getRegPressureSetName(ID) << ": "
<< NewMaxPressure[ID]
<< ((NewMaxPressure[ID] > Limit) ? " > " : " <= ") << Limit
<< "(+ " << BotRPTracker.getLiveThru()[ID] << " livethru)\n");
LLVM_DEBUG(dbgs() << " " << TRI->getRegPressureSetName(ID) << ": "
<< NewMaxPressure[ID]
<< ((NewMaxPressure[ID] > Limit) ? " > " : " <= ")
<< Limit << "(+ " << BotRPTracker.getLiveThru()[ID]
<< " livethru)\n");
}
}
}
@ -1131,17 +1126,14 @@ void ScheduleDAGMILive::updatePressureDiffs(
PressureDiff &PDiff = getPressureDiff(&SU);
PDiff.addPressureChange(Reg, Decrement, &MRI);
DEBUG(
dbgs() << " UpdateRegP: SU(" << SU.NodeNum << ") "
<< printReg(Reg, TRI) << ':' << PrintLaneMask(P.LaneMask)
<< ' ' << *SU.getInstr();
dbgs() << " to ";
PDiff.dump(*TRI);
);
LLVM_DEBUG(dbgs() << " UpdateRegP: SU(" << SU.NodeNum << ") "
<< printReg(Reg, TRI) << ':'
<< PrintLaneMask(P.LaneMask) << ' ' << *SU.getInstr();
dbgs() << " to "; PDiff.dump(*TRI););
}
} else {
assert(P.LaneMask.any());
DEBUG(dbgs() << " LiveReg: " << printVRegOrUnit(Reg, TRI) << "\n");
LLVM_DEBUG(dbgs() << " LiveReg: " << printVRegOrUnit(Reg, TRI) << "\n");
// This may be called before CurrentBottom has been initialized. However,
// BotRPTracker must have a valid position. We want the value live into the
// instruction or live out of the block, so ask for the previous
@ -1169,12 +1161,9 @@ void ScheduleDAGMILive::updatePressureDiffs(
if (LRQ.valueIn() == VNI) {
PressureDiff &PDiff = getPressureDiff(SU);
PDiff.addPressureChange(Reg, true, &MRI);
DEBUG(
dbgs() << " UpdateRegP: SU(" << SU->NodeNum << ") "
<< *SU->getInstr();
dbgs() << " to ";
PDiff.dump(*TRI);
);
LLVM_DEBUG(dbgs() << " UpdateRegP: SU(" << SU->NodeNum << ") "
<< *SU->getInstr();
dbgs() << " to "; PDiff.dump(*TRI););
}
}
}
@ -1193,8 +1182,8 @@ void ScheduleDAGMILive::updatePressureDiffs(
/// ScheduleDAGMILive then it will want to override this virtual method in order
/// to update any specialized state.
void ScheduleDAGMILive::schedule() {
DEBUG(dbgs() << "ScheduleDAGMILive::schedule starting\n");
DEBUG(SchedImpl->dumpPolicy());
LLVM_DEBUG(dbgs() << "ScheduleDAGMILive::schedule starting\n");
LLVM_DEBUG(SchedImpl->dumpPolicy());
buildDAGWithRegPressure();
Topo.InitDAGTopologicalSorting();
@ -1208,26 +1197,22 @@ void ScheduleDAGMILive::schedule() {
// This may initialize a DFSResult to be used for queue priority.
SchedImpl->initialize(this);
DEBUG(
if (EntrySU.getInstr() != nullptr)
EntrySU.dumpAll(this);
for (const SUnit &SU : SUnits) {
SU.dumpAll(this);
if (ShouldTrackPressure) {
dbgs() << " Pressure Diff : ";
getPressureDiff(&SU).dump(*TRI);
}
dbgs() << " Single Issue : ";
if (SchedModel.mustBeginGroup(SU.getInstr()) &&
SchedModel.mustEndGroup(SU.getInstr()))
dbgs() << "true;";
else
dbgs() << "false;";
dbgs() << '\n';
}
if (ExitSU.getInstr() != nullptr)
ExitSU.dumpAll(this);
);
LLVM_DEBUG(if (EntrySU.getInstr() != nullptr) EntrySU.dumpAll(this);
for (const SUnit &SU
: SUnits) {
SU.dumpAll(this);
if (ShouldTrackPressure) {
dbgs() << " Pressure Diff : ";
getPressureDiff(&SU).dump(*TRI);
}
dbgs() << " Single Issue : ";
if (SchedModel.mustBeginGroup(SU.getInstr()) &&
SchedModel.mustEndGroup(SU.getInstr()))
dbgs() << "true;";
else
dbgs() << "false;";
dbgs() << '\n';
} if (ExitSU.getInstr() != nullptr) ExitSU.dumpAll(this););
if (ViewMISchedDAGs) viewGraph();
// Initialize ready queues now that the DAG and priority data are finalized.
@ -1235,7 +1220,7 @@ void ScheduleDAGMILive::schedule() {
bool IsTopNode = false;
while (true) {
DEBUG(dbgs() << "** ScheduleDAGMILive::schedule picking next node\n");
LLVM_DEBUG(dbgs() << "** ScheduleDAGMILive::schedule picking next node\n");
SUnit *SU = SchedImpl->pickNode(IsTopNode);
if (!SU) break;
@ -1263,7 +1248,7 @@ void ScheduleDAGMILive::schedule() {
placeDebugValues();
DEBUG({
LLVM_DEBUG({
dbgs() << "*** Final schedule for "
<< printMBBReference(*begin()->getParent()) << " ***\n";
dumpSchedule();
@ -1380,13 +1365,13 @@ unsigned ScheduleDAGMILive::computeCyclicCriticalPath() {
} else
CyclicLatency = 0;
DEBUG(dbgs() << "Cyclic Path: SU(" << DefSU->NodeNum << ") -> SU("
<< SU->NodeNum << ") = " << CyclicLatency << "c\n");
LLVM_DEBUG(dbgs() << "Cyclic Path: SU(" << DefSU->NodeNum << ") -> SU("
<< SU->NodeNum << ") = " << CyclicLatency << "c\n");
if (CyclicLatency > MaxCyclicLatency)
MaxCyclicLatency = CyclicLatency;
}
}
DEBUG(dbgs() << "Cyclic Critical Path: " << MaxCyclicLatency << "c\n");
LLVM_DEBUG(dbgs() << "Cyclic Critical Path: " << MaxCyclicLatency << "c\n");
return MaxCyclicLatency;
}
@ -1430,10 +1415,8 @@ void ScheduleDAGMILive::scheduleMI(SUnit *SU, bool IsTopNode) {
TopRPTracker.advance(RegOpers);
assert(TopRPTracker.getPos() == CurrentTop && "out of sync");
DEBUG(
dbgs() << "Top Pressure:\n";
dumpRegSetPressure(TopRPTracker.getRegSetPressureAtPos(), TRI);
);
LLVM_DEBUG(dbgs() << "Top Pressure:\n"; dumpRegSetPressure(
TopRPTracker.getRegSetPressureAtPos(), TRI););
updateScheduledPressure(SU, TopRPTracker.getPressure().MaxSetPressure);
}
@ -1469,10 +1452,8 @@ void ScheduleDAGMILive::scheduleMI(SUnit *SU, bool IsTopNode) {
SmallVector<RegisterMaskPair, 8> LiveUses;
BotRPTracker.recede(RegOpers, &LiveUses);
assert(BotRPTracker.getPos() == CurrentBottom && "out of sync");
DEBUG(
dbgs() << "Bottom Pressure:\n";
dumpRegSetPressure(BotRPTracker.getRegSetPressureAtPos(), TRI);
);
LLVM_DEBUG(dbgs() << "Bottom Pressure:\n"; dumpRegSetPressure(
BotRPTracker.getRegSetPressureAtPos(), TRI););
updateScheduledPressure(SU, BotRPTracker.getPressure().MaxSetPressure);
updatePressureDiffs(LiveUses);
@ -1572,8 +1553,8 @@ void BaseMemOpClusterMutation::clusterNeighboringMemOps(
*SUb->getInstr(), MemOpRecords[Idx+1].BaseReg,
ClusterLength) &&
DAG->addEdge(SUb, SDep(SUa, SDep::Cluster))) {
DEBUG(dbgs() << "Cluster ld/st SU(" << SUa->NodeNum << ") - SU("
<< SUb->NodeNum << ")\n");
LLVM_DEBUG(dbgs() << "Cluster ld/st SU(" << SUa->NodeNum << ") - SU("
<< SUb->NodeNum << ")\n");
// Copy successor edges from SUa to SUb. Interleaving computation
// dependent on SUa can prevent load combining due to register reuse.
// Predecessor edges do not need to be copied from SUb to SUa since nearby
@ -1581,7 +1562,8 @@ void BaseMemOpClusterMutation::clusterNeighboringMemOps(
for (const SDep &Succ : SUa->Succs) {
if (Succ.getSUnit() == SUb)
continue;
DEBUG(dbgs() << " Copy Succ SU(" << Succ.getSUnit()->NodeNum << ")\n");
LLVM_DEBUG(dbgs() << " Copy Succ SU(" << Succ.getSUnit()->NodeNum
<< ")\n");
DAG->addEdge(Succ.getSUnit(), SDep(SUb, SDep::Artificial));
}
++ClusterLength;
@ -1790,18 +1772,18 @@ void CopyConstrain::constrainLocalCopy(SUnit *CopySU, ScheduleDAGMILive *DAG) {
return;
GlobalUses.push_back(Pred.getSUnit());
}
DEBUG(dbgs() << "Constraining copy SU(" << CopySU->NodeNum << ")\n");
LLVM_DEBUG(dbgs() << "Constraining copy SU(" << CopySU->NodeNum << ")\n");
// Add the weak edges.
for (SmallVectorImpl<SUnit*>::const_iterator
I = LocalUses.begin(), E = LocalUses.end(); I != E; ++I) {
DEBUG(dbgs() << " Local use SU(" << (*I)->NodeNum << ") -> SU("
<< GlobalSU->NodeNum << ")\n");
LLVM_DEBUG(dbgs() << " Local use SU(" << (*I)->NodeNum << ") -> SU("
<< GlobalSU->NodeNum << ")\n");
DAG->addEdge(GlobalSU, SDep(*I, SDep::Weak));
}
for (SmallVectorImpl<SUnit*>::const_iterator
I = GlobalUses.begin(), E = GlobalUses.end(); I != E; ++I) {
DEBUG(dbgs() << " Global use SU(" << (*I)->NodeNum << ") -> SU("
<< FirstLocalSU->NodeNum << ")\n");
LLVM_DEBUG(dbgs() << " Global use SU(" << (*I)->NodeNum << ") -> SU("
<< FirstLocalSU->NodeNum << ")\n");
DAG->addEdge(FirstLocalSU, SDep(*I, SDep::Weak));
}
}
@ -1959,16 +1941,16 @@ bool SchedBoundary::checkHazard(SUnit *SU) {
unsigned uops = SchedModel->getNumMicroOps(SU->getInstr());
if ((CurrMOps > 0) && (CurrMOps + uops > SchedModel->getIssueWidth())) {
DEBUG(dbgs() << " SU(" << SU->NodeNum << ") uops="
<< SchedModel->getNumMicroOps(SU->getInstr()) << '\n');
LLVM_DEBUG(dbgs() << " SU(" << SU->NodeNum << ") uops="
<< SchedModel->getNumMicroOps(SU->getInstr()) << '\n');
return true;
}
if (CurrMOps > 0 &&
((isTop() && SchedModel->mustBeginGroup(SU->getInstr())) ||
(!isTop() && SchedModel->mustEndGroup(SU->getInstr())))) {
DEBUG(dbgs() << " hazard: SU(" << SU->NodeNum << ") must "
<< (isTop()? "begin" : "end") << " group\n");
LLVM_DEBUG(dbgs() << " hazard: SU(" << SU->NodeNum << ") must "
<< (isTop() ? "begin" : "end") << " group\n");
return true;
}
@ -1984,9 +1966,9 @@ bool SchedBoundary::checkHazard(SUnit *SU) {
#ifndef NDEBUG
MaxObservedStall = std::max(Cycles, MaxObservedStall);
#endif
DEBUG(dbgs() << " SU(" << SU->NodeNum << ") "
<< SchedModel->getResourceName(ResIdx)
<< "=" << NRCycle << "c\n");
LLVM_DEBUG(dbgs() << " SU(" << SU->NodeNum << ") "
<< SchedModel->getResourceName(ResIdx) << "="
<< NRCycle << "c\n");
return true;
}
}
@ -2007,8 +1989,8 @@ findMaxLatency(ArrayRef<SUnit*> ReadySUs) {
}
}
if (LateSU) {
DEBUG(dbgs() << Available.getName() << " RemLatency SU("
<< LateSU->NodeNum << ") " << RemLatency << "c\n");
LLVM_DEBUG(dbgs() << Available.getName() << " RemLatency SU("
<< LateSU->NodeNum << ") " << RemLatency << "c\n");
}
return RemLatency;
}
@ -2024,8 +2006,8 @@ getOtherResourceCount(unsigned &OtherCritIdx) {
unsigned OtherCritCount = Rem->RemIssueCount
+ (RetiredMOps * SchedModel->getMicroOpFactor());
DEBUG(dbgs() << " " << Available.getName() << " + Remain MOps: "
<< OtherCritCount / SchedModel->getMicroOpFactor() << '\n');
LLVM_DEBUG(dbgs() << " " << Available.getName() << " + Remain MOps: "
<< OtherCritCount / SchedModel->getMicroOpFactor() << '\n');
for (unsigned PIdx = 1, PEnd = SchedModel->getNumProcResourceKinds();
PIdx != PEnd; ++PIdx) {
unsigned OtherCount = getResourceCount(PIdx) + Rem->RemainingCounts[PIdx];
@ -2035,9 +2017,10 @@ getOtherResourceCount(unsigned &OtherCritIdx) {
}
}
if (OtherCritIdx) {
DEBUG(dbgs() << " " << Available.getName() << " + Remain CritRes: "
<< OtherCritCount / SchedModel->getResourceFactor(OtherCritIdx)
<< " " << SchedModel->getResourceName(OtherCritIdx) << "\n");
LLVM_DEBUG(
dbgs() << " " << Available.getName() << " + Remain CritRes: "
<< OtherCritCount / SchedModel->getResourceFactor(OtherCritIdx)
<< " " << SchedModel->getResourceName(OtherCritIdx) << "\n");
}
return OtherCritCount;
}
@ -2101,7 +2084,8 @@ void SchedBoundary::bumpCycle(unsigned NextCycle) {
checkResourceLimit(SchedModel->getLatencyFactor(), getCriticalCount(),
getScheduledLatency());
DEBUG(dbgs() << "Cycle: " << CurrCycle << ' ' << Available.getName() << '\n');
LLVM_DEBUG(dbgs() << "Cycle: " << CurrCycle << ' ' << Available.getName()
<< '\n');
}
void SchedBoundary::incExecutedResources(unsigned PIdx, unsigned Count) {
@ -2121,8 +2105,8 @@ unsigned SchedBoundary::
countResource(unsigned PIdx, unsigned Cycles, unsigned NextCycle) {
unsigned Factor = SchedModel->getResourceFactor(PIdx);
unsigned Count = Factor * Cycles;
DEBUG(dbgs() << " " << SchedModel->getResourceName(PIdx)
<< " +" << Cycles << "x" << Factor << "u\n");
LLVM_DEBUG(dbgs() << " " << SchedModel->getResourceName(PIdx) << " +"
<< Cycles << "x" << Factor << "u\n");
// Update Executed resources counts.
incExecutedResources(PIdx, Count);
@ -2133,16 +2117,17 @@ countResource(unsigned PIdx, unsigned Cycles, unsigned NextCycle) {
// becomes the critical resource.
if (ZoneCritResIdx != PIdx && (getResourceCount(PIdx) > getCriticalCount())) {
ZoneCritResIdx = PIdx;
DEBUG(dbgs() << " *** Critical resource "
<< SchedModel->getResourceName(PIdx) << ": "
<< getResourceCount(PIdx) / SchedModel->getLatencyFactor() << "c\n");
LLVM_DEBUG(dbgs() << " *** Critical resource "
<< SchedModel->getResourceName(PIdx) << ": "
<< getResourceCount(PIdx) / SchedModel->getLatencyFactor()
<< "c\n");
}
// For reserved resources, record the highest cycle using the resource.
unsigned NextAvailable = getNextResourceCycle(PIdx, Cycles);
if (NextAvailable > CurrCycle) {
DEBUG(dbgs() << " Resource conflict: "
<< SchedModel->getProcResource(PIdx)->Name << " reserved until @"
<< NextAvailable << "\n");
LLVM_DEBUG(dbgs() << " Resource conflict: "
<< SchedModel->getProcResource(PIdx)->Name
<< " reserved until @" << NextAvailable << "\n");
}
return NextAvailable;
}
@ -2167,7 +2152,7 @@ void SchedBoundary::bumpNode(SUnit *SU) {
"Cannot schedule this instruction's MicroOps in the current cycle.");
unsigned ReadyCycle = (isTop() ? SU->TopReadyCycle : SU->BotReadyCycle);
DEBUG(dbgs() << " Ready @" << ReadyCycle << "c\n");
LLVM_DEBUG(dbgs() << " Ready @" << ReadyCycle << "c\n");
unsigned NextCycle = CurrCycle;
switch (SchedModel->getMicroOpBufferSize()) {
@ -2177,7 +2162,7 @@ void SchedBoundary::bumpNode(SUnit *SU) {
case 1:
if (ReadyCycle > NextCycle) {
NextCycle = ReadyCycle;
DEBUG(dbgs() << " *** Stall until: " << ReadyCycle << "\n");
LLVM_DEBUG(dbgs() << " *** Stall until: " << ReadyCycle << "\n");
}
break;
default:
@ -2206,8 +2191,9 @@ void SchedBoundary::bumpNode(SUnit *SU) {
if ((int)(ScaledMOps - getResourceCount(ZoneCritResIdx))
>= (int)SchedModel->getLatencyFactor()) {
ZoneCritResIdx = 0;
DEBUG(dbgs() << " *** Critical resource NumMicroOps: "
<< ScaledMOps / SchedModel->getLatencyFactor() << "c\n");
LLVM_DEBUG(dbgs() << " *** Critical resource NumMicroOps: "
<< ScaledMOps / SchedModel->getLatencyFactor()
<< "c\n");
}
}
for (TargetSchedModel::ProcResIter
@ -2243,13 +2229,13 @@ void SchedBoundary::bumpNode(SUnit *SU) {
unsigned &BotLatency = isTop() ? DependentLatency : ExpectedLatency;
if (SU->getDepth() > TopLatency) {
TopLatency = SU->getDepth();
DEBUG(dbgs() << " " << Available.getName()
<< " TopLatency SU(" << SU->NodeNum << ") " << TopLatency << "c\n");
LLVM_DEBUG(dbgs() << " " << Available.getName() << " TopLatency SU("
<< SU->NodeNum << ") " << TopLatency << "c\n");
}
if (SU->getHeight() > BotLatency) {
BotLatency = SU->getHeight();
DEBUG(dbgs() << " " << Available.getName()
<< " BotLatency SU(" << SU->NodeNum << ") " << BotLatency << "c\n");
LLVM_DEBUG(dbgs() << " " << Available.getName() << " BotLatency SU("
<< SU->NodeNum << ") " << BotLatency << "c\n");
}
// If we stall for any reason, bump the cycle.
if (NextCycle > CurrCycle)
@ -2273,17 +2259,17 @@ void SchedBoundary::bumpNode(SUnit *SU) {
// currCycle to X.
if ((isTop() && SchedModel->mustEndGroup(SU->getInstr())) ||
(!isTop() && SchedModel->mustBeginGroup(SU->getInstr()))) {
DEBUG(dbgs() << " Bump cycle to "
<< (isTop() ? "end" : "begin") << " group\n");
LLVM_DEBUG(dbgs() << " Bump cycle to " << (isTop() ? "end" : "begin")
<< " group\n");
bumpCycle(++NextCycle);
}
while (CurrMOps >= SchedModel->getIssueWidth()) {
DEBUG(dbgs() << " *** Max MOps " << CurrMOps
<< " at cycle " << CurrCycle << '\n');
LLVM_DEBUG(dbgs() << " *** Max MOps " << CurrMOps << " at cycle "
<< CurrCycle << '\n');
bumpCycle(++NextCycle);
}
DEBUG(dumpScheduledState());
LLVM_DEBUG(dumpScheduledState());
}
/// Release pending ready nodes in to the available queue. This makes them
@ -2356,8 +2342,8 @@ SUnit *SchedBoundary::pickOnlyChoice() {
releasePending();
}
DEBUG(Pending.dump());
DEBUG(Available.dump());
LLVM_DEBUG(Pending.dump());
LLVM_DEBUG(Available.dump());
if (Available.size() == 1)
return *Available.begin();
@ -2455,27 +2441,24 @@ void GenericSchedulerBase::setPolicy(CandPolicy &Policy, bool IsPostRA,
if (!OtherResLimited) {
if (IsPostRA || (RemLatency + CurrZone.getCurrCycle() > Rem.CriticalPath)) {
Policy.ReduceLatency |= true;
DEBUG(dbgs() << " " << CurrZone.Available.getName()
<< " RemainingLatency " << RemLatency << " + "
<< CurrZone.getCurrCycle() << "c > CritPath "
<< Rem.CriticalPath << "\n");
LLVM_DEBUG(dbgs() << " " << CurrZone.Available.getName()
<< " RemainingLatency " << RemLatency << " + "
<< CurrZone.getCurrCycle() << "c > CritPath "
<< Rem.CriticalPath << "\n");
}
}
// If the same resource is limiting inside and outside the zone, do nothing.
if (CurrZone.getZoneCritResIdx() == OtherCritIdx)
return;
DEBUG(
if (CurrZone.isResourceLimited()) {
dbgs() << " " << CurrZone.Available.getName() << " ResourceLimited: "
<< SchedModel->getResourceName(CurrZone.getZoneCritResIdx())
<< "\n";
}
if (OtherResLimited)
dbgs() << " RemainingLimit: "
<< SchedModel->getResourceName(OtherCritIdx) << "\n";
if (!CurrZone.isResourceLimited() && !OtherResLimited)
dbgs() << " Latency limited both directions.\n");
LLVM_DEBUG(if (CurrZone.isResourceLimited()) {
dbgs() << " " << CurrZone.Available.getName() << " ResourceLimited: "
<< SchedModel->getResourceName(CurrZone.getZoneCritResIdx()) << "\n";
} if (OtherResLimited) dbgs()
<< " RemainingLimit: "
<< SchedModel->getResourceName(OtherCritIdx) << "\n";
if (!CurrZone.isResourceLimited() && !OtherResLimited) dbgs()
<< " Latency limited both directions.\n");
if (CurrZone.isResourceLimited() && !Policy.ReduceResIdx)
Policy.ReduceResIdx = CurrZone.getZoneCritResIdx();
@ -2623,8 +2606,8 @@ bool tryLatency(GenericSchedulerBase::SchedCandidate &TryCand,
} // end namespace llvm
static void tracePick(GenericSchedulerBase::CandReason Reason, bool IsTop) {
DEBUG(dbgs() << "Pick " << (IsTop ? "Top " : "Bot ")
<< GenericSchedulerBase::getReasonStr(Reason) << '\n');
LLVM_DEBUG(dbgs() << "Pick " << (IsTop ? "Top " : "Bot ")
<< GenericSchedulerBase::getReasonStr(Reason) << '\n');
}
static void tracePick(const GenericSchedulerBase::SchedCandidate &Cand) {
@ -2746,14 +2729,14 @@ void GenericScheduler::checkAcyclicLatency() {
Rem.IsAcyclicLatencyLimited = InFlightCount > BufferLimit;
DEBUG(dbgs() << "IssueCycles="
<< Rem.RemIssueCount / SchedModel->getLatencyFactor() << "c "
<< "IterCycles=" << IterCount / SchedModel->getLatencyFactor()
<< "c NumIters=" << (AcyclicCount + IterCount-1) / IterCount
<< " InFlight=" << InFlightCount / SchedModel->getMicroOpFactor()
<< "m BufferLim=" << SchedModel->getMicroOpBufferSize() << "m\n";
if (Rem.IsAcyclicLatencyLimited)
dbgs() << " ACYCLIC LATENCY LIMIT\n");
LLVM_DEBUG(
dbgs() << "IssueCycles="
<< Rem.RemIssueCount / SchedModel->getLatencyFactor() << "c "
<< "IterCycles=" << IterCount / SchedModel->getLatencyFactor()
<< "c NumIters=" << (AcyclicCount + IterCount - 1) / IterCount
<< " InFlight=" << InFlightCount / SchedModel->getMicroOpFactor()
<< "m BufferLim=" << SchedModel->getMicroOpBufferSize() << "m\n";
if (Rem.IsAcyclicLatencyLimited) dbgs() << " ACYCLIC LATENCY LIMIT\n");
}
void GenericScheduler::registerRoots() {
@ -2764,7 +2747,7 @@ void GenericScheduler::registerRoots() {
if (SU->getDepth() > Rem.CriticalPath)
Rem.CriticalPath = SU->getDepth();
}
DEBUG(dbgs() << "Critical Path(GS-RR ): " << Rem.CriticalPath << '\n');
LLVM_DEBUG(dbgs() << "Critical Path(GS-RR ): " << Rem.CriticalPath << '\n');
if (DumpCriticalPathLength) {
errs() << "Critical Path(GS-RR ): " << Rem.CriticalPath << " \n";
}
@ -2879,10 +2862,10 @@ void GenericScheduler::initCandidate(SchedCandidate &Cand, SUnit *SU,
}
}
}
DEBUG(if (Cand.RPDelta.Excess.isValid())
dbgs() << " Try SU(" << Cand.SU->NodeNum << ") "
<< TRI->getRegPressureSetName(Cand.RPDelta.Excess.getPSet())
<< ":" << Cand.RPDelta.Excess.getUnitInc() << "\n");
LLVM_DEBUG(if (Cand.RPDelta.Excess.isValid()) dbgs()
<< " Try SU(" << Cand.SU->NodeNum << ") "
<< TRI->getRegPressureSetName(Cand.RPDelta.Excess.getPSet()) << ":"
<< Cand.RPDelta.Excess.getUnitInc() << "\n");
}
/// Apply a set of heursitics to a new candidate. Heuristics are currently
@ -3023,7 +3006,7 @@ void GenericScheduler::pickNodeFromQueue(SchedBoundary &Zone,
if (TryCand.ResDelta == SchedResourceDelta())
TryCand.initResourceDelta(DAG, SchedModel);
Cand.setBest(TryCand);
DEBUG(traceCandidate(Cand));
LLVM_DEBUG(traceCandidate(Cand));
}
}
}
@ -3052,14 +3035,14 @@ SUnit *GenericScheduler::pickNodeBidirectional(bool &IsTopNode) {
setPolicy(TopPolicy, /*IsPostRA=*/false, Top, &Bot);
// See if BotCand is still valid (because we previously scheduled from Top).
DEBUG(dbgs() << "Picking from Bot:\n");
LLVM_DEBUG(dbgs() << "Picking from Bot:\n");
if (!BotCand.isValid() || BotCand.SU->isScheduled ||
BotCand.Policy != BotPolicy) {
BotCand.reset(CandPolicy());
pickNodeFromQueue(Bot, BotPolicy, DAG->getBotRPTracker(), BotCand);
assert(BotCand.Reason != NoCand && "failed to find the first candidate");
} else {
DEBUG(traceCandidate(BotCand));
LLVM_DEBUG(traceCandidate(BotCand));
#ifndef NDEBUG
if (VerifyScheduling) {
SchedCandidate TCand;
@ -3072,14 +3055,14 @@ SUnit *GenericScheduler::pickNodeBidirectional(bool &IsTopNode) {
}
// Check if the top Q has a better candidate.
DEBUG(dbgs() << "Picking from Top:\n");
LLVM_DEBUG(dbgs() << "Picking from Top:\n");
if (!TopCand.isValid() || TopCand.SU->isScheduled ||
TopCand.Policy != TopPolicy) {
TopCand.reset(CandPolicy());
pickNodeFromQueue(Top, TopPolicy, DAG->getTopRPTracker(), TopCand);
assert(TopCand.Reason != NoCand && "failed to find the first candidate");
} else {
DEBUG(traceCandidate(TopCand));
LLVM_DEBUG(traceCandidate(TopCand));
#ifndef NDEBUG
if (VerifyScheduling) {
SchedCandidate TCand;
@ -3099,7 +3082,7 @@ SUnit *GenericScheduler::pickNodeBidirectional(bool &IsTopNode) {
tryCandidate(Cand, TopCand, nullptr);
if (TopCand.Reason != NoCand) {
Cand.setBest(TopCand);
DEBUG(traceCandidate(Cand));
LLVM_DEBUG(traceCandidate(Cand));
}
IsTopNode = Cand.AtTop;
@ -3148,7 +3131,8 @@ SUnit *GenericScheduler::pickNode(bool &IsTopNode) {
if (SU->isBottomReady())
Bot.removeReady(SU);
DEBUG(dbgs() << "Scheduling SU(" << SU->NodeNum << ") " << *SU->getInstr());
LLVM_DEBUG(dbgs() << "Scheduling SU(" << SU->NodeNum << ") "
<< *SU->getInstr());
return SU;
}
@ -3169,8 +3153,8 @@ void GenericScheduler::reschedulePhysRegCopies(SUnit *SU, bool isTop) {
MachineInstr *Copy = DepSU->getInstr();
if (!Copy->isCopy())
continue;
DEBUG(dbgs() << " Rescheduling physreg copy ";
Dep.getSUnit()->dump(DAG));
LLVM_DEBUG(dbgs() << " Rescheduling physreg copy ";
Dep.getSUnit()->dump(DAG));
DAG->moveInstruction(Copy, InsertPos);
}
}
@ -3249,7 +3233,7 @@ void PostGenericScheduler::registerRoots() {
if (SU->getDepth() > Rem.CriticalPath)
Rem.CriticalPath = SU->getDepth();
}
DEBUG(dbgs() << "Critical Path: (PGS-RR) " << Rem.CriticalPath << '\n');
LLVM_DEBUG(dbgs() << "Critical Path: (PGS-RR) " << Rem.CriticalPath << '\n');
if (DumpCriticalPathLength) {
errs() << "Critical Path(PGS-RR ): " << Rem.CriticalPath << " \n";
}
@ -3307,7 +3291,7 @@ void PostGenericScheduler::pickNodeFromQueue(SchedCandidate &Cand) {
tryCandidate(Cand, TryCand);
if (TryCand.Reason != NoCand) {
Cand.setBest(TryCand);
DEBUG(traceCandidate(Cand));
LLVM_DEBUG(traceCandidate(Cand));
}
}
}
@ -3339,7 +3323,8 @@ SUnit *PostGenericScheduler::pickNode(bool &IsTopNode) {
IsTopNode = true;
Top.removeReady(SU);
DEBUG(dbgs() << "Scheduling SU(" << SU->NodeNum << ") " << *SU->getInstr());
LLVM_DEBUG(dbgs() << "Scheduling SU(" << SU->NodeNum << ") "
<< *SU->getInstr());
return SU;
}
@ -3428,12 +3413,15 @@ public:
SUnit *SU = ReadyQ.back();
ReadyQ.pop_back();
IsTopNode = false;
DEBUG(dbgs() << "Pick node " << "SU(" << SU->NodeNum << ") "
<< " ILP: " << DAG->getDFSResult()->getILP(SU)
<< " Tree: " << DAG->getDFSResult()->getSubtreeID(SU) << " @"
<< DAG->getDFSResult()->getSubtreeLevel(
DAG->getDFSResult()->getSubtreeID(SU)) << '\n'
<< "Scheduling " << *SU->getInstr());
LLVM_DEBUG(dbgs() << "Pick node "
<< "SU(" << SU->NodeNum << ") "
<< " ILP: " << DAG->getDFSResult()->getILP(SU)
<< " Tree: " << DAG->getDFSResult()->getSubtreeID(SU)
<< " @"
<< DAG->getDFSResult()->getSubtreeLevel(
DAG->getDFSResult()->getSubtreeID(SU))
<< '\n'
<< "Scheduling " << *SU->getInstr());
return SU;
}

34
llvm/lib/CodeGen/MachineSink.cpp
View File

@ -211,8 +211,8 @@ bool MachineSinking::PerformTrivialForwardCoalescing(MachineInstr &MI,
MachineInstr *DefMI = MRI->getVRegDef(SrcReg);
if (DefMI->isCopyLike())
return false;
DEBUG(dbgs() << "Coalescing: " << *DefMI);
DEBUG(dbgs() << "*** to: " << MI);
LLVM_DEBUG(dbgs() << "Coalescing: " << *DefMI);
LLVM_DEBUG(dbgs() << "*** to: " << MI);
MRI->replaceRegWith(DstReg, SrcReg);
MI.eraseFromParent();
@ -296,7 +296,7 @@ bool MachineSinking::runOnMachineFunction(MachineFunction &MF) {
if (skipFunction(MF.getFunction()))
return false;
DEBUG(dbgs() << "******** Machine Sinking ********\n");
LLVM_DEBUG(dbgs() << "******** Machine Sinking ********\n");
TII = MF.getSubtarget().getInstrInfo();
TRI = MF.getSubtarget().getRegisterInfo();
@ -323,14 +323,14 @@ bool MachineSinking::runOnMachineFunction(MachineFunction &MF) {
for (auto &Pair : ToSplit) {
auto NewSucc = Pair.first->SplitCriticalEdge(Pair.second, *this);
if (NewSucc != nullptr) {
DEBUG(dbgs() << " *** Splitting critical edge: "
<< printMBBReference(*Pair.first) << " -- "
<< printMBBReference(*NewSucc) << " -- "
<< printMBBReference(*Pair.second) << '\n');
LLVM_DEBUG(dbgs() << " *** Splitting critical edge: "
<< printMBBReference(*Pair.first) << " -- "
<< printMBBReference(*NewSucc) << " -- "
<< printMBBReference(*Pair.second) << '\n');
MadeChange = true;
++NumSplit;
} else
DEBUG(dbgs() << " *** Not legal to break critical edge\n");
LLVM_DEBUG(dbgs() << " *** Not legal to break critical edge\n");
}
// If this iteration over the code changed anything, keep iterating.
if (!MadeChange) break;
@ -804,7 +804,7 @@ bool MachineSinking::SinkInstruction(MachineInstr &MI, bool &SawStore,
return false;
}
DEBUG(dbgs() << "Sink instr " << MI << "\tinto block " << *SuccToSinkTo);
LLVM_DEBUG(dbgs() << "Sink instr " << MI << "\tinto block " << *SuccToSinkTo);
// If the block has multiple predecessors, this is a critical edge.
// Decide if we can sink along it or need to break the edge.
@ -814,26 +814,26 @@ bool MachineSinking::SinkInstruction(MachineInstr &MI, bool &SawStore,
bool TryBreak = false;
bool store = true;
if (!MI.isSafeToMove(AA, store)) {
DEBUG(dbgs() << " *** NOTE: Won't sink load along critical edge.\n");
LLVM_DEBUG(dbgs() << " *** NOTE: Won't sink load along critical edge.\n");
TryBreak = true;
}
// We don't want to sink across a critical edge if we don't dominate the
// successor. We could be introducing calculations to new code paths.
if (!TryBreak && !DT->dominates(ParentBlock, SuccToSinkTo)) {
DEBUG(dbgs() << " *** NOTE: Critical edge found\n");
LLVM_DEBUG(dbgs() << " *** NOTE: Critical edge found\n");
TryBreak = true;
}
// Don't sink instructions into a loop.
if (!TryBreak && LI->isLoopHeader(SuccToSinkTo)) {
DEBUG(dbgs() << " *** NOTE: Loop header found\n");
LLVM_DEBUG(dbgs() << " *** NOTE: Loop header found\n");
TryBreak = true;
}
// Otherwise we are OK with sinking along a critical edge.
if (!TryBreak)
DEBUG(dbgs() << "Sinking along critical edge.\n");
LLVM_DEBUG(dbgs() << "Sinking along critical edge.\n");
else {
// Mark this edge as to be split.
// If the edge can actually be split, the next iteration of the main loop
@ -841,8 +841,8 @@ bool MachineSinking::SinkInstruction(MachineInstr &MI, bool &SawStore,
bool Status =
PostponeSplitCriticalEdge(MI, ParentBlock, SuccToSinkTo, BreakPHIEdge);
if (!Status)
DEBUG(dbgs() << " *** PUNTING: Not legal or profitable to "
"break critical edge\n");
LLVM_DEBUG(dbgs() << " *** PUNTING: Not legal or profitable to "
"break critical edge\n");
// The instruction will not be sunk this time.
return false;
}
@ -855,8 +855,8 @@ bool MachineSinking::SinkInstruction(MachineInstr &MI, bool &SawStore,
bool Status = PostponeSplitCriticalEdge(MI, ParentBlock,
SuccToSinkTo, BreakPHIEdge);
if (!Status)
DEBUG(dbgs() << " *** PUNTING: Not legal or profitable to "
"break critical edge\n");
LLVM_DEBUG(dbgs() << " *** PUNTING: Not legal or profitable to "
"break critical edge\n");
// The instruction will not be sunk this time.
return false;
}

54
llvm/lib/CodeGen/MachineTraceMetrics.cpp
View File

@ -396,8 +396,8 @@ MachineTraceMetrics::getEnsemble(MachineTraceMetrics::Strategy strategy) {
}
void MachineTraceMetrics::invalidate(const MachineBasicBlock *MBB) {
DEBUG(dbgs() << "Invalidate traces through " << printMBBReference(*MBB)
<< '\n');
LLVM_DEBUG(dbgs() << "Invalidate traces through " << printMBBReference(*MBB)
<< '\n');
BlockInfo[MBB->getNumber()].invalidate();
for (unsigned i = 0; i != TS_NumStrategies; ++i)
if (Ensembles[i])
@ -477,8 +477,8 @@ public:
/// Compute the trace through MBB.
void MachineTraceMetrics::Ensemble::computeTrace(const MachineBasicBlock *MBB) {
DEBUG(dbgs() << "Computing " << getName() << " trace through "
<< printMBBReference(*MBB) << '\n');
LLVM_DEBUG(dbgs() << "Computing " << getName() << " trace through "
<< printMBBReference(*MBB) << '\n');
// Set up loop bounds for the backwards post-order traversal.
LoopBounds Bounds(BlockInfo, MTM.Loops);
@ -486,11 +486,11 @@ void MachineTraceMetrics::Ensemble::computeTrace(const MachineBasicBlock *MBB) {
Bounds.Downward = false;
Bounds.Visited.clear();
for (auto I : inverse_post_order_ext(MBB, Bounds)) {
DEBUG(dbgs() << " pred for " << printMBBReference(*I) << ": ");
LLVM_DEBUG(dbgs() << " pred for " << printMBBReference(*I) << ": ");
TraceBlockInfo &TBI = BlockInfo[I->getNumber()];
// All the predecessors have been visited, pick the preferred one.
TBI.Pred = pickTracePred(I);
DEBUG({
LLVM_DEBUG({
if (TBI.Pred)
dbgs() << printMBBReference(*TBI.Pred) << '\n';
else
@ -504,11 +504,11 @@ void MachineTraceMetrics::Ensemble::computeTrace(const MachineBasicBlock *MBB) {
Bounds.Downward = true;
Bounds.Visited.clear();
for (auto I : post_order_ext(MBB, Bounds)) {
DEBUG(dbgs() << " succ for " << printMBBReference(*I) << ": ");
LLVM_DEBUG(dbgs() << " succ for " << printMBBReference(*I) << ": ");
TraceBlockInfo &TBI = BlockInfo[I->getNumber()];
// All the successors have been visited, pick the preferred one.
TBI.Succ = pickTraceSucc(I);
DEBUG({
LLVM_DEBUG({
if (TBI.Succ)
dbgs() << printMBBReference(*TBI.Succ) << '\n';
else
@ -531,8 +531,8 @@ MachineTraceMetrics::Ensemble::invalidate(const MachineBasicBlock *BadMBB) {
WorkList.push_back(BadMBB);
do {
const MachineBasicBlock *MBB = WorkList.pop_back_val();
DEBUG(dbgs() << "Invalidate " << printMBBReference(*MBB) << ' '
<< getName() << " height.\n");
LLVM_DEBUG(dbgs() << "Invalidate " << printMBBReference(*MBB) << ' '
<< getName() << " height.\n");
// Find any MBB predecessors that have MBB as their preferred successor.
// They are the only ones that need to be invalidated.
for (const MachineBasicBlock *Pred : MBB->predecessors()) {
@ -556,8 +556,8 @@ MachineTraceMetrics::Ensemble::invalidate(const MachineBasicBlock *BadMBB) {
WorkList.push_back(BadMBB);
do {
const MachineBasicBlock *MBB = WorkList.pop_back_val();
DEBUG(dbgs() << "Invalidate " << printMBBReference(*MBB) << ' '
<< getName() << " depth.\n");
LLVM_DEBUG(dbgs() << "Invalidate " << printMBBReference(*MBB) << ' '
<< getName() << " depth.\n");
// Find any MBB successors that have MBB as their preferred predecessor.
// They are the only ones that need to be invalidated.
for (const MachineBasicBlock *Succ : MBB->successors()) {
@ -813,9 +813,9 @@ updateDepth(MachineTraceMetrics::TraceBlockInfo &TBI, const MachineInstr &UseMI,
if (TBI.HasValidInstrHeights) {
// Update critical path length.
TBI.CriticalPath = std::max(TBI.CriticalPath, Cycle + MICycles.Height);
DEBUG(dbgs() << TBI.CriticalPath << '\t' << Cycle << '\t' << UseMI);
LLVM_DEBUG(dbgs() << TBI.CriticalPath << '\t' << Cycle << '\t' << UseMI);
} else {
DEBUG(dbgs() << Cycle << '\t' << UseMI);
LLVM_DEBUG(dbgs() << Cycle << '\t' << UseMI);
}
}
@ -860,13 +860,13 @@ computeInstrDepths(const MachineBasicBlock *MBB) {
// Go through trace blocks in top-down order, stopping after the center block.
while (!Stack.empty()) {
MBB = Stack.pop_back_val();
DEBUG(dbgs() << "\nDepths for " << printMBBReference(*MBB) << ":\n");
LLVM_DEBUG(dbgs() << "\nDepths for " << printMBBReference(*MBB) << ":\n");
TraceBlockInfo &TBI = BlockInfo[MBB->getNumber()];
TBI.HasValidInstrDepths = true;
TBI.CriticalPath = 0;
// Print out resource depths here as well.
DEBUG({
LLVM_DEBUG({
dbgs() << format("%7u Instructions\n", TBI.InstrDepth);
ArrayRef<unsigned> PRDepths = getProcResourceDepths(MBB->getNumber());
for (unsigned K = 0; K != PRDepths.size(); ++K)
@ -1045,12 +1045,12 @@ computeInstrHeights(const MachineBasicBlock *MBB) {
SmallVector<DataDep, 8> Deps;
for (;!Stack.empty(); Stack.pop_back()) {
MBB = Stack.back();
DEBUG(dbgs() << "Heights for " << printMBBReference(*MBB) << ":\n");
LLVM_DEBUG(dbgs() << "Heights for " << printMBBReference(*MBB) << ":\n");
TraceBlockInfo &TBI = BlockInfo[MBB->getNumber()];
TBI.HasValidInstrHeights = true;
TBI.CriticalPath = 0;
DEBUG({
LLVM_DEBUG({
dbgs() << format("%7u Instructions\n", TBI.InstrHeight);
ArrayRef<unsigned> PRHeights = getProcResourceHeights(MBB->getNumber());
for (unsigned K = 0; K != PRHeights.size(); ++K)
@ -1081,7 +1081,7 @@ computeInstrHeights(const MachineBasicBlock *MBB) {
if (!Deps.empty()) {
// Loop header PHI heights are all 0.
unsigned Height = TBI.Succ ? Cycles.lookup(&PHI).Height : 0;
DEBUG(dbgs() << "pred\t" << Height << '\t' << PHI);
LLVM_DEBUG(dbgs() << "pred\t" << Height << '\t' << PHI);
if (pushDepHeight(Deps.front(), PHI, Height, Heights, MTM.SchedModel,
MTM.TII))
addLiveIns(Deps.front().DefMI, Deps.front().DefOp, Stack);
@ -1122,38 +1122,38 @@ computeInstrHeights(const MachineBasicBlock *MBB) {
InstrCycles &MICycles = Cycles[&MI];
MICycles.Height = Cycle;
if (!TBI.HasValidInstrDepths) {
DEBUG(dbgs() << Cycle << '\t' << MI);
LLVM_DEBUG(dbgs() << Cycle << '\t' << MI);
continue;
}
// Update critical path length.
TBI.CriticalPath = std::max(TBI.CriticalPath, Cycle + MICycles.Depth);
DEBUG(dbgs() << TBI.CriticalPath << '\t' << Cycle << '\t' << MI);
LLVM_DEBUG(dbgs() << TBI.CriticalPath << '\t' << Cycle << '\t' << MI);
}
// Update virtual live-in heights. They were added by addLiveIns() with a 0
// height because the final height isn't known until now.
DEBUG(dbgs() << printMBBReference(*MBB) << " Live-ins:");
LLVM_DEBUG(dbgs() << printMBBReference(*MBB) << " Live-ins:");
for (LiveInReg &LIR : TBI.LiveIns) {
const MachineInstr *DefMI = MTM.MRI->getVRegDef(LIR.Reg);
LIR.Height = Heights.lookup(DefMI);
DEBUG(dbgs() << ' ' << printReg(LIR.Reg) << '@' << LIR.Height);
LLVM_DEBUG(dbgs() << ' ' << printReg(LIR.Reg) << '@' << LIR.Height);
}
// Transfer the live regunits to the live-in list.
for (SparseSet<LiveRegUnit>::const_iterator
RI = RegUnits.begin(), RE = RegUnits.end(); RI != RE; ++RI) {
TBI.LiveIns.push_back(LiveInReg(RI->RegUnit, RI->Cycle));
DEBUG(dbgs() << ' ' << printRegUnit(RI->RegUnit, MTM.TRI)
<< '@' << RI->Cycle);
LLVM_DEBUG(dbgs() << ' ' << printRegUnit(RI->RegUnit, MTM.TRI) << '@'
<< RI->Cycle);
}
DEBUG(dbgs() << '\n');
LLVM_DEBUG(dbgs() << '\n');
if (!TBI.HasValidInstrDepths)
continue;
// Add live-ins to the critical path length.
TBI.CriticalPath = std::max(TBI.CriticalPath,
computeCrossBlockCriticalPath(TBI));
DEBUG(dbgs() << "Critical path: " << TBI.CriticalPath << '\n');
LLVM_DEBUG(dbgs() << "Critical path: " << TBI.CriticalPath << '\n');
}
}

20
llvm/lib/CodeGen/MacroFusion.cpp
View File

@ -66,11 +66,11 @@ static bool fuseInstructionPair(ScheduleDAGMI &DAG, SUnit &FirstSU,
if (SI.getSUnit() == &FirstSU)
SI.setLatency(0);
DEBUG(dbgs() << "Macro fuse: ";
FirstSU.print(dbgs(), &DAG); dbgs() << " - ";
SecondSU.print(dbgs(), &DAG); dbgs() << " / ";
dbgs() << DAG.TII->getName(FirstSU.getInstr()->getOpcode()) << " - " <<
DAG.TII->getName(SecondSU.getInstr()->getOpcode()) << '\n'; );
LLVM_DEBUG(
dbgs() << "Macro fuse: "; FirstSU.print(dbgs(), &DAG); dbgs() << " - ";
SecondSU.print(dbgs(), &DAG); dbgs() << " / ";
dbgs() << DAG.TII->getName(FirstSU.getInstr()->getOpcode()) << " - "
<< DAG.TII->getName(SecondSU.getInstr()->getOpcode()) << '\n';);
// Make data dependencies from the FirstSU also dependent on the SecondSU to
// prevent them from being scheduled between the FirstSU and the SecondSU.
@ -80,9 +80,8 @@ static bool fuseInstructionPair(ScheduleDAGMI &DAG, SUnit &FirstSU,
if (SI.isWeak() || isHazard(SI) ||
SU == &DAG.ExitSU || SU == &SecondSU || SU->isPred(&SecondSU))
continue;
DEBUG(dbgs() << " Bind ";
SecondSU.print(dbgs(), &DAG); dbgs() << " - ";
SU->print(dbgs(), &DAG); dbgs() << '\n';);
LLVM_DEBUG(dbgs() << " Bind "; SecondSU.print(dbgs(), &DAG);
dbgs() << " - "; SU->print(dbgs(), &DAG); dbgs() << '\n';);
DAG.addEdge(SU, SDep(&SecondSU, SDep::Artificial));
}
@ -93,9 +92,8 @@ static bool fuseInstructionPair(ScheduleDAGMI &DAG, SUnit &FirstSU,
SUnit *SU = SI.getSUnit();
if (SI.isWeak() || isHazard(SI) || &FirstSU == SU || FirstSU.isSucc(SU))
continue;
DEBUG(dbgs() << " Bind ";
SU->print(dbgs(), &DAG); dbgs() << " - ";
FirstSU.print(dbgs(), &DAG); dbgs() << '\n';);
LLVM_DEBUG(dbgs() << " Bind "; SU->print(dbgs(), &DAG); dbgs() << " - ";
FirstSU.print(dbgs(), &DAG); dbgs() << '\n';);
DAG.addEdge(&FirstSU, SDep(SU, SDep::Artificial));
}

23
llvm/lib/CodeGen/PHIElimination.cpp
View File

@ -270,7 +270,8 @@ void PHIElimination::LowerPHINode(MachineBasicBlock &MBB,
IncomingReg = entry;
reusedIncoming = true;
++NumReused;
DEBUG(dbgs() << "Reusing " << printReg(IncomingReg) << " for " << *MPhi);
LLVM_DEBUG(dbgs() << "Reusing " << printReg(IncomingReg) << " for "
<< *MPhi);
} else {
const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
entry = IncomingReg = MF.getRegInfo().createVirtualRegister(RC);
@ -295,9 +296,9 @@ void PHIElimination::LowerPHINode(MachineBasicBlock &MBB,
// AfterPHIsIt, so it appears before the current PHICopy.
if (reusedIncoming)
if (MachineInstr *OldKill = VI.findKill(&MBB)) {
DEBUG(dbgs() << "Remove old kill from " << *OldKill);
LLVM_DEBUG(dbgs() << "Remove old kill from " << *OldKill);
LV->removeVirtualRegisterKilled(IncomingReg, *OldKill);
DEBUG(MBB.dump());
LLVM_DEBUG(MBB.dump());
}
// Add information to LiveVariables to know that the incoming value is
@ -593,9 +594,9 @@ bool PHIElimination::SplitPHIEdges(MachineFunction &MF,
if (!ShouldSplit && !NoPhiElimLiveOutEarlyExit)
continue;
if (ShouldSplit) {
DEBUG(dbgs() << printReg(Reg) << " live-out before critical edge "
<< printMBBReference(*PreMBB) << " -> "
<< printMBBReference(MBB) << ": " << *BBI);
LLVM_DEBUG(dbgs() << printReg(Reg) << " live-out before critical edge "
<< printMBBReference(*PreMBB) << " -> "
<< printMBBReference(MBB) << ": " << *BBI);
}
// If Reg is not live-in to MBB, it means it must be live-in to some
@ -610,10 +611,12 @@ bool PHIElimination::SplitPHIEdges(MachineFunction &MF,
// Check for a loop exiting edge.
if (!ShouldSplit && CurLoop != PreLoop) {
DEBUG({
LLVM_DEBUG({
dbgs() << "Split wouldn't help, maybe avoid loop copies?\n";
if (PreLoop) dbgs() << "PreLoop: " << *PreLoop;
if (CurLoop) dbgs() << "CurLoop: " << *CurLoop;
if (PreLoop)
dbgs() << "PreLoop: " << *PreLoop;
if (CurLoop)
dbgs() << "CurLoop: " << *CurLoop;
});
// This edge could be entering a loop, exiting a loop, or it could be
// both: Jumping directly form one loop to the header of a sibling
@ -624,7 +627,7 @@ bool PHIElimination::SplitPHIEdges(MachineFunction &MF,
if (!ShouldSplit && !SplitAllCriticalEdges)
continue;
if (!PreMBB->SplitCriticalEdge(&MBB, *this)) {
DEBUG(dbgs() << "Failed to split critical edge.\n");
LLVM_DEBUG(dbgs() << "Failed to split critical edge.\n");
continue;
}
Changed = true;

49
llvm/lib/CodeGen/PeepholeOptimizer.cpp
View File

@ -696,7 +696,8 @@ bool PeepholeOptimizer::findNextSource(RegSubRegPair RegSubReg,
// An existent entry with multiple sources is a PHI cycle we must avoid.
// Otherwise it's an entry with a valid next source we already found.
if (CurSrcRes.getNumSources() > 1) {
DEBUG(dbgs() << "findNextSource: found PHI cycle, aborting...\n");
LLVM_DEBUG(dbgs()
<< "findNextSource: found PHI cycle, aborting...\n");
return false;
}
break;
@ -709,7 +710,7 @@ bool PeepholeOptimizer::findNextSource(RegSubRegPair RegSubReg,
if (NumSrcs > 1) {
PHICount++;
if (PHICount >= RewritePHILimit) {
DEBUG(dbgs() << "findNextSource: PHI limit reached\n");
LLVM_DEBUG(dbgs() << "findNextSource: PHI limit reached\n");
return false;
}
@ -1143,9 +1144,9 @@ getNewSource(MachineRegisterInfo *MRI, const TargetInstrInfo *TII,
// Build the new PHI node and return its def register as the new source.
MachineInstr &OrigPHI = const_cast<MachineInstr &>(*Res.getInst());
MachineInstr &NewPHI = insertPHI(*MRI, *TII, NewPHISrcs, OrigPHI);
DEBUG(dbgs() << "-- getNewSource\n");
DEBUG(dbgs() << " Replacing: " << OrigPHI);
DEBUG(dbgs() << " With: " << NewPHI);
LLVM_DEBUG(dbgs() << "-- getNewSource\n");
LLVM_DEBUG(dbgs() << " Replacing: " << OrigPHI);
LLVM_DEBUG(dbgs() << " With: " << NewPHI);
const MachineOperand &MODef = NewPHI.getOperand(0);
return RegSubRegPair(MODef.getReg(), MODef.getSubReg());
}
@ -1241,9 +1242,9 @@ PeepholeOptimizer::rewriteSource(MachineInstr &CopyLike,
NewCopy->getOperand(0).setIsUndef();
}
DEBUG(dbgs() << "-- RewriteSource\n");
DEBUG(dbgs() << " Replacing: " << CopyLike);
DEBUG(dbgs() << " With: " << *NewCopy);
LLVM_DEBUG(dbgs() << "-- RewriteSource\n");
LLVM_DEBUG(dbgs() << " Replacing: " << CopyLike);
LLVM_DEBUG(dbgs() << " With: " << *NewCopy);
MRI->replaceRegWith(Def.Reg, NewVReg);
MRI->clearKillFlags(NewVReg);
@ -1462,7 +1463,8 @@ bool PeepholeOptimizer::foldRedundantNAPhysCopy(
if (PrevCopy == NAPhysToVirtMIs.end()) {
// We can't remove the copy: there was an intervening clobber of the
// non-allocatable physical register after the copy to virtual.
DEBUG(dbgs() << "NAPhysCopy: intervening clobber forbids erasing " << MI);
LLVM_DEBUG(dbgs() << "NAPhysCopy: intervening clobber forbids erasing "
<< MI);
return false;
}
@ -1470,7 +1472,7 @@ bool PeepholeOptimizer::foldRedundantNAPhysCopy(
if (PrevDstReg == SrcReg) {
// Remove the virt->phys copy: we saw the virtual register definition, and
// the non-allocatable physical register's state hasn't changed since then.
DEBUG(dbgs() << "NAPhysCopy: erasing " << MI);
LLVM_DEBUG(dbgs() << "NAPhysCopy: erasing " << MI);
++NumNAPhysCopies;
return true;
}
@ -1479,7 +1481,7 @@ bool PeepholeOptimizer::foldRedundantNAPhysCopy(
// register get a copy of the non-allocatable physical register, and we only
// track one such copy. Avoid getting confused by this new non-allocatable
// physical register definition, and remove it from the tracked copies.
DEBUG(dbgs() << "NAPhysCopy: missed opportunity " << MI);
LLVM_DEBUG(dbgs() << "NAPhysCopy: missed opportunity " << MI);
NAPhysToVirtMIs.erase(PrevCopy);
return false;
}
@ -1575,15 +1577,15 @@ bool PeepholeOptimizer::optimizeRecurrence(MachineInstr &PHI) {
if (findTargetRecurrence(PHI.getOperand(0).getReg(), TargetRegs, RC)) {
// Commutes operands of instructions in RC if necessary so that the copy to
// be generated from PHI can be coalesced.
DEBUG(dbgs() << "Optimize recurrence chain from " << PHI);
LLVM_DEBUG(dbgs() << "Optimize recurrence chain from " << PHI);
for (auto &RI : RC) {
DEBUG(dbgs() << "\tInst: " << *(RI.getMI()));
LLVM_DEBUG(dbgs() << "\tInst: " << *(RI.getMI()));
auto CP = RI.getCommutePair();
if (CP) {
Changed = true;
TII->commuteInstruction(*(RI.getMI()), false, (*CP).first,
(*CP).second);
DEBUG(dbgs() << "\t\tCommuted: " << *(RI.getMI()));
LLVM_DEBUG(dbgs() << "\t\tCommuted: " << *(RI.getMI()));
}
}
}
@ -1595,8 +1597,8 @@ bool PeepholeOptimizer::runOnMachineFunction(MachineFunction &MF) {
if (skipFunction(MF.getFunction()))
return false;
DEBUG(dbgs() << "********** PEEPHOLE OPTIMIZER **********\n");
DEBUG(dbgs() << "********** Function: " << MF.getName() << '\n');
LLVM_DEBUG(dbgs() << "********** PEEPHOLE OPTIMIZER **********\n");
LLVM_DEBUG(dbgs() << "********** Function: " << MF.getName() << '\n');
if (DisablePeephole)
return false;
@ -1667,7 +1669,8 @@ bool PeepholeOptimizer::runOnMachineFunction(MachineFunction &MF) {
if (Def != NAPhysToVirtMIs.end()) {
// A new definition of the non-allocatable physical register
// invalidates previous copies.
DEBUG(dbgs() << "NAPhysCopy: invalidating because of " << *MI);
LLVM_DEBUG(dbgs()
<< "NAPhysCopy: invalidating because of " << *MI);
NAPhysToVirtMIs.erase(Def);
}
}
@ -1676,7 +1679,8 @@ bool PeepholeOptimizer::runOnMachineFunction(MachineFunction &MF) {
for (auto &RegMI : NAPhysToVirtMIs) {
unsigned Def = RegMI.first;
if (MachineOperand::clobbersPhysReg(RegMask, Def)) {
DEBUG(dbgs() << "NAPhysCopy: invalidating because of " << *MI);
LLVM_DEBUG(dbgs()
<< "NAPhysCopy: invalidating because of " << *MI);
NAPhysToVirtMIs.erase(Def);
}
}
@ -1692,7 +1696,8 @@ bool PeepholeOptimizer::runOnMachineFunction(MachineFunction &MF) {
// don't know what's correct anymore.
//
// FIXME: handle explicit asm clobbers.
DEBUG(dbgs() << "NAPhysCopy: blowing away all info due to " << *MI);
LLVM_DEBUG(dbgs() << "NAPhysCopy: blowing away all info due to "
<< *MI);
NAPhysToVirtMIs.clear();
}
@ -1768,8 +1773,8 @@ bool PeepholeOptimizer::runOnMachineFunction(MachineFunction &MF) {
TII->optimizeLoadInstr(*MI, MRI, FoldAsLoadDefReg, DefMI)) {
// Update LocalMIs since we replaced MI with FoldMI and deleted
// DefMI.
DEBUG(dbgs() << "Replacing: " << *MI);
DEBUG(dbgs() << " With: " << *FoldMI);
LLVM_DEBUG(dbgs() << "Replacing: " << *MI);
LLVM_DEBUG(dbgs() << " With: " << *FoldMI);
LocalMIs.erase(MI);
LocalMIs.erase(DefMI);
LocalMIs.insert(FoldMI);
@ -1791,7 +1796,7 @@ bool PeepholeOptimizer::runOnMachineFunction(MachineFunction &MF) {
// the load candidates. Note: We might be able to fold *into* this
// instruction, so this needs to be after the folding logic.
if (MI->isLoadFoldBarrier()) {
DEBUG(dbgs() << "Encountered load fold barrier on " << *MI);
LLVM_DEBUG(dbgs() << "Encountered load fold barrier on " << *MI);
FoldAsLoadDefCandidates.clear();
}
}

44
llvm/lib/CodeGen/PostRASchedulerList.cpp
View File

@ -243,11 +243,11 @@ void SchedulePostRATDList::enterRegion(MachineBasicBlock *bb,
/// Print the schedule before exiting the region.
void SchedulePostRATDList::exitRegion() {
DEBUG({
dbgs() << "*** Final schedule ***\n";
dumpSchedule();
dbgs() << '\n';
});
LLVM_DEBUG({
dbgs() << "*** Final schedule ***\n";
dumpSchedule();
dbgs() << '\n';
});
ScheduleDAGInstrs::exitRegion();
}
@ -309,7 +309,7 @@ bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) {
: TargetSubtargetInfo::ANTIDEP_NONE);
}
DEBUG(dbgs() << "PostRAScheduler\n");
LLVM_DEBUG(dbgs() << "PostRAScheduler\n");
SchedulePostRATDList Scheduler(Fn, MLI, AA, RegClassInfo, AntiDepMode,
CriticalPathRCs);
@ -413,13 +413,12 @@ void SchedulePostRATDList::schedule() {
postprocessDAG();
DEBUG(dbgs() << "********** List Scheduling **********\n");
DEBUG(
for (const SUnit &SU : SUnits) {
SU.dumpAll(this);
dbgs() << '\n';
}
);
LLVM_DEBUG(dbgs() << "********** List Scheduling **********\n");
LLVM_DEBUG(for (const SUnit &SU
: SUnits) {
SU.dumpAll(this);
dbgs() << '\n';
});
AvailableQueue.initNodes(SUnits);
ListScheduleTopDown();
@ -502,8 +501,8 @@ void SchedulePostRATDList::ReleaseSuccessors(SUnit *SU) {
/// count of its successors. If a successor pending count is zero, add it to
/// the Available queue.
void SchedulePostRATDList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) {
DEBUG(dbgs() << "*** Scheduling [" << CurCycle << "]: ");
DEBUG(SU->dump(this));
LLVM_DEBUG(dbgs() << "*** Scheduling [" << CurCycle << "]: ");
LLVM_DEBUG(SU->dump(this));
Sequence.push_back(SU);
assert(CurCycle >= SU->getDepth() &&
@ -517,7 +516,7 @@ void SchedulePostRATDList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) {
/// emitNoop - Add a noop to the current instruction sequence.
void SchedulePostRATDList::emitNoop(unsigned CurCycle) {
DEBUG(dbgs() << "*** Emitting noop in cycle " << CurCycle << '\n');
LLVM_DEBUG(dbgs() << "*** Emitting noop in cycle " << CurCycle << '\n');
HazardRec->EmitNoop();
Sequence.push_back(nullptr); // NULL here means noop
++NumNoops;
@ -569,7 +568,8 @@ void SchedulePostRATDList::ListScheduleTopDown() {
MinDepth = PendingQueue[i]->getDepth();
}
DEBUG(dbgs() << "\n*** Examining Available\n"; AvailableQueue.dump(this));
LLVM_DEBUG(dbgs() << "\n*** Examining Available\n";
AvailableQueue.dump(this));
SUnit *FoundSUnit = nullptr, *NotPreferredSUnit = nullptr;
bool HasNoopHazards = false;
@ -605,7 +605,8 @@ void SchedulePostRATDList::ListScheduleTopDown() {
// non-preferred node.
if (NotPreferredSUnit) {
if (!FoundSUnit) {
DEBUG(dbgs() << "*** Will schedule a non-preferred instruction...\n");
LLVM_DEBUG(
dbgs() << "*** Will schedule a non-preferred instruction...\n");
FoundSUnit = NotPreferredSUnit;
} else {
AvailableQueue.push(NotPreferredSUnit);
@ -632,19 +633,20 @@ void SchedulePostRATDList::ListScheduleTopDown() {
HazardRec->EmitInstruction(FoundSUnit);
CycleHasInsts = true;
if (HazardRec->atIssueLimit()) {
DEBUG(dbgs() << "*** Max instructions per cycle " << CurCycle << '\n');
LLVM_DEBUG(dbgs() << "*** Max instructions per cycle " << CurCycle
<< '\n');
HazardRec->AdvanceCycle();
++CurCycle;
CycleHasInsts = false;
}
} else {
if (CycleHasInsts) {
DEBUG(dbgs() << "*** Finished cycle " << CurCycle << '\n');
LLVM_DEBUG(dbgs() << "*** Finished cycle " << CurCycle << '\n');
HazardRec->AdvanceCycle();
} else if (!HasNoopHazards) {
// Otherwise, we have a pipeline stall, but no other problem,
// just advance the current cycle and try again.
DEBUG(dbgs() << "*** Stall in cycle " << CurCycle << '\n');
LLVM_DEBUG(dbgs() << "*** Stall in cycle " << CurCycle << '\n');
HazardRec->AdvanceCycle();
++NumStalls;
} else {

16
llvm/lib/CodeGen/ProcessImplicitDefs.cpp
View File

@ -73,7 +73,7 @@ bool ProcessImplicitDefs::canTurnIntoImplicitDef(MachineInstr *MI) {
}
void ProcessImplicitDefs::processImplicitDef(MachineInstr *MI) {
DEBUG(dbgs() << "Processing " << *MI);
LLVM_DEBUG(dbgs() << "Processing " << *MI);
unsigned Reg = MI->getOperand(0).getReg();
if (TargetRegisterInfo::isVirtualRegister(Reg)) {
@ -84,7 +84,7 @@ void ProcessImplicitDefs::processImplicitDef(MachineInstr *MI) {
MachineInstr *UserMI = MO.getParent();
if (!canTurnIntoImplicitDef(UserMI))
continue;
DEBUG(dbgs() << "Converting to IMPLICIT_DEF: " << *UserMI);
LLVM_DEBUG(dbgs() << "Converting to IMPLICIT_DEF: " << *UserMI);
UserMI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
WorkList.insert(UserMI);
}
@ -116,7 +116,7 @@ void ProcessImplicitDefs::processImplicitDef(MachineInstr *MI) {
// If we found the using MI, we can erase the IMPLICIT_DEF.
if (Found) {
DEBUG(dbgs() << "Physreg user: " << *UserMI);
LLVM_DEBUG(dbgs() << "Physreg user: " << *UserMI);
MI->eraseFromParent();
return;
}
@ -125,15 +125,15 @@ void ProcessImplicitDefs::processImplicitDef(MachineInstr *MI) {
// Leave the physreg IMPLICIT_DEF, but trim any extra operands.
for (unsigned i = MI->getNumOperands() - 1; i; --i)
MI->RemoveOperand(i);
DEBUG(dbgs() << "Keeping physreg: " << *MI);
LLVM_DEBUG(dbgs() << "Keeping physreg: " << *MI);
}
/// processImplicitDefs - Process IMPLICIT_DEF instructions and turn them into
/// <undef> operands.
bool ProcessImplicitDefs::runOnMachineFunction(MachineFunction &MF) {
DEBUG(dbgs() << "********** PROCESS IMPLICIT DEFS **********\n"
<< "********** Function: " << MF.getName() << '\n');
LLVM_DEBUG(dbgs() << "********** PROCESS IMPLICIT DEFS **********\n"
<< "********** Function: " << MF.getName() << '\n');
bool Changed = false;
@ -154,8 +154,8 @@ bool ProcessImplicitDefs::runOnMachineFunction(MachineFunction &MF) {
if (WorkList.empty())
continue;
DEBUG(dbgs() << printMBBReference(*MFI) << " has " << WorkList.size()
<< " implicit defs.\n");
LLVM_DEBUG(dbgs() << printMBBReference(*MFI) << " has " << WorkList.size()
<< " implicit defs.\n");
Changed = true;
// Drain the WorkList to recursively process any new implicit defs.

24
llvm/lib/CodeGen/PrologEpilogInserter.cpp
View File

@ -564,10 +564,12 @@ AdjustStackOffset(MachineFrameInfo &MFI, int FrameIdx,
Offset = alignTo(Offset, Align, Skew);
if (StackGrowsDown) {
DEBUG(dbgs() << "alloc FI(" << FrameIdx << ") at SP[" << -Offset << "]\n");
LLVM_DEBUG(dbgs() << "alloc FI(" << FrameIdx << ") at SP[" << -Offset
<< "]\n");
MFI.setObjectOffset(FrameIdx, -Offset); // Set the computed offset
} else {
DEBUG(dbgs() << "alloc FI(" << FrameIdx << ") at SP[" << Offset << "]\n");
LLVM_DEBUG(dbgs() << "alloc FI(" << FrameIdx << ") at SP[" << Offset
<< "]\n");
MFI.setObjectOffset(FrameIdx, Offset);
Offset += MFI.getObjectSize(FrameIdx);
}
@ -660,12 +662,12 @@ static inline bool scavengeStackSlot(MachineFrameInfo &MFI, int FrameIdx,
if (StackGrowsDown) {
int ObjStart = -(FreeStart + ObjSize);
DEBUG(dbgs() << "alloc FI(" << FrameIdx << ") scavenged at SP[" << ObjStart
<< "]\n");
LLVM_DEBUG(dbgs() << "alloc FI(" << FrameIdx << ") scavenged at SP["
<< ObjStart << "]\n");
MFI.setObjectOffset(FrameIdx, ObjStart);
} else {
DEBUG(dbgs() << "alloc FI(" << FrameIdx << ") scavenged at SP[" << FreeStart
<< "]\n");
LLVM_DEBUG(dbgs() << "alloc FI(" << FrameIdx << ") scavenged at SP["
<< FreeStart << "]\n");
MFI.setObjectOffset(FrameIdx, FreeStart);
}
@ -745,7 +747,7 @@ void PEI::calculateFrameObjectOffsets(MachineFunction &Fn) {
// Adjust to alignment boundary
Offset = alignTo(Offset, Align, Skew);
DEBUG(dbgs() << "alloc FI(" << i << ") at SP[" << -Offset << "]\n");
LLVM_DEBUG(dbgs() << "alloc FI(" << i << ") at SP[" << -Offset << "]\n");
MFI.setObjectOffset(i, -Offset); // Set the computed offset
}
} else if (MaxCSFrameIndex >= MinCSFrameIndex) {
@ -758,7 +760,7 @@ void PEI::calculateFrameObjectOffsets(MachineFunction &Fn) {
// Adjust to alignment boundary
Offset = alignTo(Offset, Align, Skew);
DEBUG(dbgs() << "alloc FI(" << i << ") at SP[" << Offset << "]\n");
LLVM_DEBUG(dbgs() << "alloc FI(" << i << ") at SP[" << Offset << "]\n");
MFI.setObjectOffset(i, Offset);
Offset += MFI.getObjectSize(i);
}
@ -795,14 +797,14 @@ void PEI::calculateFrameObjectOffsets(MachineFunction &Fn) {
// Adjust to alignment boundary.
Offset = alignTo(Offset, Align, Skew);
DEBUG(dbgs() << "Local frame base offset: " << Offset << "\n");
LLVM_DEBUG(dbgs() << "Local frame base offset: " << Offset << "\n");
// Resolve offsets for objects in the local block.
for (unsigned i = 0, e = MFI.getLocalFrameObjectCount(); i != e; ++i) {
std::pair<int, int64_t> Entry = MFI.getLocalFrameObjectMap(i);
int64_t FIOffset = (StackGrowsDown ? -Offset : Offset) + Entry.second;
DEBUG(dbgs() << "alloc FI(" << Entry.first << ") at SP[" <<
FIOffset << "]\n");
LLVM_DEBUG(dbgs() << "alloc FI(" << Entry.first << ") at SP[" << FIOffset
<< "]\n");
MFI.setObjectOffset(Entry.first, FIOffset);
}
// Allocate the local block

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