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AMDGPU: Use isMeta flags on pseudoinstructions

This commit is contained in:
Matt Arsenault 2022-06-06 17:19:03 -04:00
parent df698a5762
commit d342d130da
3 changed files with 7 additions and 7 deletions
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6
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
View File

@ -1770,14 +1770,8 @@ unsigned SIInstrInfo::getNumWaitStates(const MachineInstr &MI) {
case AMDGPU::S_NOP:
return MI.getOperand(0).getImm() + 1;
// FIXME: Any other pseudo instruction?
// SI_RETURN_TO_EPILOG is a fallthrough to code outside of the function. The
// hazard, even if one exist, won't really be visible. Should we handle it?
case AMDGPU::SI_MASKED_UNREACHABLE:
case AMDGPU::WAVE_BARRIER:
case AMDGPU::SCHED_BARRIER:
return 0;
}
}

6
llvm/lib/Target/AMDGPU/SIInstructions.td
View File

@ -313,6 +313,7 @@ def WAVE_BARRIER : SPseudoInstSI<(outs), (ins),
let isConvergent = 1;
let FixedSize = 1;
let Size = 0;
let isMeta = 1;
}
def SCHED_BARRIER : SPseudoInstSI<(outs), (ins i32imm:$mask),
@ -325,6 +326,7 @@ def SCHED_BARRIER : SPseudoInstSI<(outs), (ins i32imm:$mask),
let isConvergent = 1;
let FixedSize = 1;
let Size = 0;
let isMeta = 1;
}
// SI pseudo instructions. These are used by the CFG structurizer pass
@ -462,6 +464,7 @@ def SI_MASKED_UNREACHABLE : SPseudoInstSI <(outs), (ins),
let Size = 0;
let hasNoSchedulingInfo = 1;
let FixedSize = 1;
let isMeta = 1;
}
// Used as an isel pseudo to directly emit initialization with an
@ -497,6 +500,9 @@ def SI_RETURN_TO_EPILOG : SPseudoInstSI <
let hasNoSchedulingInfo = 1;
let DisableWQM = 1;
let FixedSize = 1;
// TODO: Should this be true?
let isMeta = 0;
}
// Return for returning function calls.

2
llvm/test/CodeGen/AMDGPU/sched-barrier-pre-RA.mir
View File

@ -385,8 +385,8 @@ body: |
; CHECK-LABEL: name: sched_barrier_mask_256
; CHECK: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; CHECK-NEXT: [[DS_READ_U16_gfx9_:%[0-9]+]]:vgpr_32 = DS_READ_U16_gfx9 [[DEF]], 0, 0, implicit $exec :: (load (s32) from %ir.in, !alias.scope !0, addrspace 3)
; CHECK-NEXT: [[V_MUL_LO_U32_e64_:%[0-9]+]]:vgpr_32 = nsw V_MUL_LO_U32_e64 [[DS_READ_U16_gfx9_]], [[DS_READ_U16_gfx9_]], implicit $exec
; CHECK-NEXT: [[DS_READ_U16_gfx9_1:%[0-9]+]]:vgpr_32 = DS_READ_U16_gfx9 [[DEF]], 0, 0, implicit $exec :: (load (s32) from %ir.in, !alias.scope !0, addrspace 3)
; CHECK-NEXT: [[V_MUL_LO_U32_e64_:%[0-9]+]]:vgpr_32 = nsw V_MUL_LO_U32_e64 [[DS_READ_U16_gfx9_]], [[DS_READ_U16_gfx9_]], implicit $exec
; CHECK-NEXT: S_NOP 0
; CHECK-NEXT: DS_WRITE_B32 [[V_MUL_LO_U32_e64_]], [[DEF]], 0, 16, implicit $m0, implicit $exec :: (store (s32) into %ir.out, !noalias !0, addrspace 3)
; CHECK-NEXT: SCHED_BARRIER 256