forked from OSchip/llvm-project
[RISCV][NFC] Refactor RISCVDAGToDAGISel::Select
Introduce and use a switch on the opcode. llvm-svn: 343688
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@ -66,10 +66,7 @@ void RISCVDAGToDAGISel::PostprocessISelDAG() {
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}
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void RISCVDAGToDAGISel::Select(SDNode *Node) {
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unsigned Opcode = Node->getOpcode();
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MVT XLenVT = Subtarget->getXLenVT();
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// If we have a custom node, we have already selected
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// If we have a custom node, we have already selected.
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if (Node->isMachineOpcode()) {
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LLVM_DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << "\n");
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Node->setNodeId(-1);
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@ -78,27 +75,30 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
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// Instruction Selection not handled by the auto-generated tablegen selection
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// should be handled here.
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unsigned Opcode = Node->getOpcode();
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MVT XLenVT = Subtarget->getXLenVT();
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SDLoc DL(Node);
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EVT VT = Node->getValueType(0);
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if (Opcode == ISD::Constant && VT == XLenVT) {
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auto *ConstNode = cast<ConstantSDNode>(Node);
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// Materialize zero constants as copies from X0. This allows the coalescer
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// to propagate these into other instructions.
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if (ConstNode->isNullValue()) {
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switch (Opcode) {
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case ISD::Constant: {
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auto ConstNode = cast<ConstantSDNode>(Node);
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if (VT == XLenVT && ConstNode->isNullValue()) {
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SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node),
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RISCV::X0, XLenVT);
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ReplaceNode(Node, New.getNode());
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return;
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}
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break;
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}
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if (Opcode == ISD::FrameIndex) {
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SDLoc DL(Node);
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case ISD::FrameIndex: {
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SDValue Imm = CurDAG->getTargetConstant(0, DL, XLenVT);
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int FI = cast<FrameIndexSDNode>(Node)->getIndex();
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EVT VT = Node->getValueType(0);
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SDValue TFI = CurDAG->getTargetFrameIndex(FI, VT);
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ReplaceNode(Node, CurDAG->getMachineNode(RISCV::ADDI, DL, VT, TFI, Imm));
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return;
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}
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}
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// Select the default instruction.
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SelectCode(Node);
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