Fix typo in test - it should be masking bits0-15 not bit16

llvm-svn: 280816
2016-09-07 15:19:07 +00:00 · 2016-09-07 15:19:07 +00:00 · d311311beb
parent 034e727001
commit d311311beb
1 changed files with 1 additions and 1 deletions
--- a/llvm/test/CodeGen/X86/combine-or.ll
+++ b/llvm/test/CodeGen/X86/combine-or.ll
@ -462,7 +462,7 @@ define <4 x i32> @or_zext_v4i16(<4 x i16> %a0) {
 ; CHECK-NEXT:    por {{.*}}(%rip), %xmm0
 ; CHECK-NEXT:    retq
  %1 = zext <4 x i16> %a0 to <4 x i32>
-  %2 = or <4 x i32> %1, <i32 65536, i32 65536, i32 65536, i32 65536>
+  %2 = or <4 x i32> %1, <i32 65535, i32 65535, i32 65535, i32 65535>
  ret <4 x i32> %2
 }