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R600/SI: fix VOP3b encoding v2 

v2: document why we hardcode VCC for now.

This is a candidate for the mesa-stable branch.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 176099
This commit is contained in:
Christian Konig 2013-02-26 17:52:09 +00:00
parent 0f0a8fe2dd
commit d303996918
2 changed files with 32 additions and 6 deletions
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24
llvm/lib/Target/R600/SIInstrInfo.td
View File

@ -51,6 +51,7 @@ class InlineImm <ValueType vt> : ImmLeaf <vt, [{
def SIOperand { def SIOperand {
int ZERO = 0x80; int ZERO = 0x80;
int VCC = 0x6A;
} }
class GPR4Align <RegisterClass rc> : Operand <vAny> { class GPR4Align <RegisterClass rc> : Operand <vAny> {
@ -195,6 +196,29 @@ multiclass VOP2_32 <bits<6> op, string opName, list<dag> pattern>
multiclass VOP2_64 <bits<6> op, string opName, list<dag> pattern> multiclass VOP2_64 <bits<6> op, string opName, list<dag> pattern>
: VOP2_Helper <op, VReg_64, VSrc_64, opName, pattern>; : VOP2_Helper <op, VReg_64, VSrc_64, opName, pattern>;
multiclass VOP2b_32 <bits<6> op, string opName, list<dag> pattern> {
def _e32 : VOP2 <
op, (outs VReg_32:$dst), (ins VSrc_32:$src0, VReg_32:$src1),
opName#"_e32 $dst, $src0, $src1", pattern
>;
def _e64 : VOP3b <
{1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
(outs VReg_32:$dst),
(ins VSrc_32:$src0, VReg_32:$src1,
i32imm:$abs, i32imm:$clamp,
i32imm:$omod, i32imm:$neg),
opName#"_e64 $dst, $src0, $src1, $abs, $clamp, $omod, $neg", []
> {
let SRC2 = SIOperand.ZERO;
/* the VOP2 variant puts the carry out into VCC, the VOP3 variant
can write it into any SGPR. We currently don't use the carry out,
so for now hardcode it to VCC as well */
let SDST = SIOperand.VCC;
}
}
multiclass VOPC_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc, multiclass VOPC_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc,
string opName, ValueType vt, PatLeaf cond> { string opName, ValueType vt, PatLeaf cond> {

14
llvm/lib/Target/R600/SIInstructions.td
View File

@ -805,17 +805,19 @@ defm V_MADAK_F32 : VOP2_32 <0x00000021, "V_MADAK_F32", []>;
//defm V_MBCNT_LO_U32_B32 : VOP2_32 <0x00000023, "V_MBCNT_LO_U32_B32", []>; //defm V_MBCNT_LO_U32_B32 : VOP2_32 <0x00000023, "V_MBCNT_LO_U32_B32", []>;
//defm V_MBCNT_HI_U32_B32 : VOP2_32 <0x00000024, "V_MBCNT_HI_U32_B32", []>; //defm V_MBCNT_HI_U32_B32 : VOP2_32 <0x00000024, "V_MBCNT_HI_U32_B32", []>;
let Defs = [VCC] in { // Carry-out goes to VCC let Defs = [VCC] in { // Carry-out goes to VCC
defm V_ADD_I32 : VOP2_32 <0x00000025, "V_ADD_I32", defm V_ADD_I32 : VOP2b_32 <0x00000025, "V_ADD_I32",
[(set VReg_32:$dst, (add (i32 VSrc_32:$src0), (i32 VReg_32:$src1)))] [(set VReg_32:$dst, (add (i32 VSrc_32:$src0), (i32 VReg_32:$src1)))]
>; >;
defm V_SUB_I32 : VOP2_32 <0x00000026, "V_SUB_I32", defm V_SUB_I32 : VOP2b_32 <0x00000026, "V_SUB_I32",
[(set VReg_32:$dst, (sub (i32 VSrc_32:$src0), (i32 VReg_32:$src1)))] [(set VReg_32:$dst, (sub (i32 VSrc_32:$src0), (i32 VReg_32:$src1)))]
>; >;
defm V_SUBREV_I32 : VOP2b_32 <0x00000027, "V_SUBREV_I32", []>;
let Uses = [VCC] in { // Carry-out comes from VCC
defm V_ADDC_U32 : VOP2b_32 <0x00000028, "V_ADDC_U32", []>;
defm V_SUBB_U32 : VOP2b_32 <0x00000029, "V_SUBB_U32", []>;
defm V_SUBBREV_U32 : VOP2b_32 <0x0000002a, "V_SUBBREV_U32", []>;
} // End Uses = [VCC]
} // End Defs = [VCC] } // End Defs = [VCC]
defm V_SUBREV_I32 : VOP2_32 <0x00000027, "V_SUBREV_I32", []>;
defm V_ADDC_U32 : VOP2_32 <0x00000028, "V_ADDC_U32", []>;
defm V_SUBB_U32 : VOP2_32 <0x00000029, "V_SUBB_U32", []>;
defm V_SUBBREV_U32 : VOP2_32 <0x0000002a, "V_SUBBREV_U32", []>;
defm V_LDEXP_F32 : VOP2_32 <0x0000002b, "V_LDEXP_F32", []>; defm V_LDEXP_F32 : VOP2_32 <0x0000002b, "V_LDEXP_F32", []>;
////def V_CVT_PKACCUM_U8_F32 : VOP2_U8 <0x0000002c, "V_CVT_PKACCUM_U8_F32", []>; ////def V_CVT_PKACCUM_U8_F32 : VOP2_U8 <0x0000002c, "V_CVT_PKACCUM_U8_F32", []>;
////def V_CVT_PKNORM_I16_F32 : VOP2_I16 <0x0000002d, "V_CVT_PKNORM_I16_F32", []>; ////def V_CVT_PKNORM_I16_F32 : VOP2_I16 <0x0000002d, "V_CVT_PKNORM_I16_F32", []>;