forked from OSchip/llvm-project
[Hexagon] Guard the generation of lookup table
The llvm flag "-hexagon-emit-lookup-tables" guards the generation of lookup table generated from a switch statement. Differential Revision: https://reviews.llvm.org/D34819 llvm-svn: 306877
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@ -21,6 +21,10 @@ using namespace llvm;
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#define DEBUG_TYPE "hexagontti"
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static cl::opt<bool> EmitLookupTables("hexagon-emit-lookup-tables",
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cl::init(true), cl::Hidden,
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cl::desc("Control lookup table emission on Hexagon target"));
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TargetTransformInfo::PopcntSupportKind
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HexagonTTIImpl::getPopcntSupport(unsigned IntTyWidthInBit) const {
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// Return Fast Hardware support as every input < 64 bits will be promoted
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@ -70,3 +74,7 @@ int HexagonTTIImpl::getUserCost(const User *U,
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return TargetTransformInfo::TCC_Free;
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return BaseT::getUserCost(U, Operands);
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}
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bool HexagonTTIImpl::shouldBuildLookupTables() const {
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return EmitLookupTables;
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}
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@ -63,6 +63,9 @@ public:
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/// @}
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int getUserCost(const User *U, ArrayRef<const Value *> Operands);
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// Hexagon specific decision to generate a lookup table.
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bool shouldBuildLookupTables() const;
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};
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} // end namespace llvm
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@ -0,0 +1,5 @@
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config.suffixes = ['.ll']
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targets = set(config.root.targets_to_build.split())
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if not 'Hexagon' in targets:
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config.unsupported = True
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@ -0,0 +1,62 @@
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; RUN: opt -S -O2 < %s | FileCheck %s -check-prefix=ENABLE
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; RUN: opt -S -hexagon-emit-lookup-tables=true -O2 < %s | FileCheck %s -check-prefix=ENABLE
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; RUN: opt -S -hexagon-emit-lookup-tables=false -O2 < %s | FileCheck %s -check-prefix=DISABLE
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; ENABLE: @{{.*}} = private unnamed_addr constant [6 x i32] [i32 9, i32 20, i32 14, i32 22, i32 12, i32 5]
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; DISABLE-NOT: @{{.*}} = private unnamed_addr constant [6 x i32] [i32 9, i32 20, i32 14, i32 22, i32 12, i32 5]
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; DISABLE : = phi i32 [ 19, %{{.*}} ], [ 5, %{{.*}} ], [ 12, %{{.*}} ], [ 22, %{{.*}} ], [ 14, %{{.*}} ], [ 20, %{{.*}} ], [ 9, %{{.*}} ]
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target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
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target triple = "hexagon-unknown--elf"
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; Function Attrs: noinline nounwind
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define i32 @foo(i32 %x) #0 section ".tcm_text" {
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entry:
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%retval = alloca i32, align 4
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%x.addr = alloca i32, align 4
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store i32 %x, i32* %x.addr, align 4
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%0 = load i32, i32* %x.addr, align 4
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switch i32 %0, label %sw.default [
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i32 0, label %sw.bb
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i32 1, label %sw.bb1
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i32 2, label %sw.bb2
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i32 3, label %sw.bb3
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i32 4, label %sw.bb4
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i32 5, label %sw.bb5
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]
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sw.bb: ; preds = %entry
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store i32 9, i32* %retval, align 4
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br label %return
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sw.bb1: ; preds = %entry
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store i32 20, i32* %retval, align 4
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br label %return
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sw.bb2: ; preds = %entry
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store i32 14, i32* %retval, align 4
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br label %return
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sw.bb3: ; preds = %entry
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store i32 22, i32* %retval, align 4
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br label %return
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sw.bb4: ; preds = %entry
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store i32 12, i32* %retval, align 4
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br label %return
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sw.bb5: ; preds = %entry
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store i32 5, i32* %retval, align 4
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br label %return
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sw.default: ; preds = %entry
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store i32 19, i32* %retval, align 4
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br label %return
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return: ; preds = %sw.default, %sw.bb5, %sw.bb4, %sw.bb3, %sw.bb2, %sw.bb1, %sw.bb
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%1 = load i32, i32* %retval, align 4
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ret i32 %1
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}
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attributes #0 = { noinline nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv60" "target-features"="-hvx-double,-long-calls" "unsafe-fp-math"="false" "use-soft-float"="false" }
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