forked from OSchip/llvm-project
[SystemZ] Guard LEFR/LFER with FeatureVector
The LEFR/LFER pseudos are aliases for vector instructions and should therefore be guared by FeatureVector. If they aren't, the TableGen scheduler definition checking might complain that there is no data for those pseudos for pre-z13 machines. No functional change intended. llvm-svn: 285576
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@ -1079,11 +1079,13 @@ def : Pat<(v2i64 (z_replicate GR64:$scalar)),
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// Moving 32-bit values between GPRs and FPRs can be done using VLVGF
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// and VLGVF.
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def LEFR : UnaryAliasVRS<VR32, GR32>;
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def LFER : UnaryAliasVRS<GR64, VR32>;
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def : Pat<(f32 (bitconvert (i32 GR32:$src))), (LEFR GR32:$src)>;
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def : Pat<(i32 (bitconvert (f32 VR32:$src))),
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(EXTRACT_SUBREG (LFER VR32:$src), subreg_l32)>;
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let Predicates = [FeatureVector] in {
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def LEFR : UnaryAliasVRS<VR32, GR32>;
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def LFER : UnaryAliasVRS<GR64, VR32>;
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def : Pat<(f32 (bitconvert (i32 GR32:$src))), (LEFR GR32:$src)>;
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def : Pat<(i32 (bitconvert (f32 VR32:$src))),
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(EXTRACT_SUBREG (LFER VR32:$src), subreg_l32)>;
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}
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// Floating-point values are stored in element 0 of the corresponding
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// vector register. Scalar to vector conversion is just a subreg and
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