forked from OSchip/llvm-project
[AArch64] Respect reserved registers while renaming in LdSt opt.
We cannot pick reserved registers as rename registers. Fixes https://bugs.llvm.org/show_bug.cgi?id=44358
This commit is contained in:
Florian Hahn
parent
70d592d68c
commit
d269255b95
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@ -26,6 +26,7 @@
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/IR/DebugLoc.h"
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#include "llvm/MC/MCRegisterInfo.h"
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@ -1374,6 +1375,7 @@ static Optional<MCPhysReg> tryToFindRegisterToRename(
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SmallPtrSetImpl<const TargetRegisterClass *> &RequiredClasses,
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const TargetRegisterInfo *TRI) {
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auto &MF = *FirstMI.getParent()->getParent();
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MachineRegisterInfo &RegInfo = MF.getRegInfo();
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// Checks if any sub- or super-register of PR is callee saved.
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auto AnySubOrSuperRegCalleePreserved = [&MF, TRI](MCPhysReg PR) {
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@ -1397,7 +1399,8 @@ static Optional<MCPhysReg> tryToFindRegisterToRename(
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auto *RegClass = TRI->getMinimalPhysRegClass(getLdStRegOp(FirstMI).getReg());
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for (const MCPhysReg &PR : *RegClass) {
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if (DefinedInBB.available(PR) && UsedInBetween.available(PR) &&
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!AnySubOrSuperRegCalleePreserved(PR) && CanBeUsedForAllClasses(PR)) {
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!RegInfo.isReserved(PR) && !AnySubOrSuperRegCalleePreserved(PR) &&
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CanBeUsedForAllClasses(PR)) {
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DefinedInBB.addReg(PR);
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LLVM_DEBUG(dbgs() << "Found rename register " << printReg(PR, TRI)
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<< "\n");
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@ -0,0 +1,89 @@
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# RUN: llc -run-pass=aarch64-ldst-opt -mattr=+reserve-x10 -mattr=+reserve-x11 \
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# RUN: -mattr=+reserve-x15 -mtriple=arm64-apple-iphoneos -verify-machineinstrs \
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# RUN: -o - %s | FileCheck --check-prefix=CHECK --check-prefix=PRESERVED %s
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# RUN: llc -run-pass=aarch64-ldst-opt -mtriple=arm64-apple-iphoneos -verify-machineinstrs \
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# RUN: -o - %s | FileCheck --check-prefix=CHECK --check-prefix=NOPRES %s
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# Make sure we do not pick reserved registers. For test1, we would pick x10,
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# and for test2 we would pick x15, both of which are reserved.
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#
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---
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# CHECK-LABEL: name: test1
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# CHECK: bb.0:
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# CHECK-NEXT: liveins: $x0, $x1
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# PRESERVED: $x12, renamable $x8 = LDPXi renamable $x0, 0 :: (load 8)
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# NOPRES: $x10, renamable $x8 = LDPXi renamable $x0, 0 :: (load 8)
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# CHECK-NEXT: renamable $x9 = LDRXui renamable $x0, 1 :: (load 8)
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# CHECK-NEXT: STRXui renamable $x9, renamable $x0, 100 :: (store 8, align 4)
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# CHECK-NEXT: renamable $x8 = ADDXrr $x8, $x8
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# PRESERVED-NEXT: STPXi renamable $x8, killed $x12, renamable $x0, 10 :: (store 8, align 4)
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# NOPRES-NEXT: STPXi renamable $x8, killed $x10, renamable $x0, 10 :: (store 8, align 4)
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# CHECK-NEXT: RET undef $lr
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name: test1
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alignment: 4
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tracksRegLiveness: true
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liveins:
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- { reg: '$x0' }
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- { reg: '$x1' }
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- { reg: '$x8' }
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frameInfo:
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maxAlignment: 1
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maxCallFrameSize: 0
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $x0, $x1
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renamable $x9, renamable $x8 = LDPXi renamable $x0, 0 :: (load 8)
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STRXui renamable killed $x9, renamable $x0, 11 :: (store 8, align 4)
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renamable $x9 = LDRXui renamable $x0, 1 :: (load 8)
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STRXui renamable $x9, renamable $x0, 100 :: (store 8, align 4)
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renamable $x8 = ADDXrr $x8, $x8
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STRXui renamable $x8, renamable $x0, 10 :: (store 8, align 4)
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RET undef $lr
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...
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# CHECK-LABEL: name: test2
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# CHECK: bb.0:
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# CHECK-NEXT: liveins: $x0, $x1, $x10, $x11, $x12, $x13
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# CHECK: renamable $w19 = LDRWui renamable $x0, 0 :: (load 8)
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# PRESERVED-NEXT: $x18, renamable $x8 = LDPXi renamable $x0, 1 :: (load 8)
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# NOPRES-NEXT: $x15, renamable $x8 = LDPXi renamable $x0, 1 :: (load 8)
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# CHECK-NEXT: renamable $x9 = LDRXui renamable $x0, 3 :: (load 8)
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# CHECK-NEXT: renamable $x14 = LDRXui renamable $x0, 5 :: (load 8)
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# PRESERVED-NEXT: STPXi renamable $x9, killed $x18, renamable $x0, 10 :: (store 8, align 4)
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# NOPRES-NEXT: STPXi renamable $x9, killed $x15, renamable $x0, 10 :: (store 8, align 4)
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# CHECK-NEXT: STRXui killed renamable $x14, renamable $x0, 200 :: (store 8, align 4)
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# CHECK-NEXT: renamable $w8 = ADDWrr $w19, $w19
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# CHECK-NEXT: STRWui renamable $w8, renamable $x0, 100 :: (store 8, align 4)
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# CHECK-NEXT: RET undef $lr
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#
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name: test2
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alignment: 4
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tracksRegLiveness: true
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liveins:
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- { reg: '$x0' }
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- { reg: '$x1' }
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- { reg: '$x8' }
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frameInfo:
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maxAlignment: 1
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maxCallFrameSize: 0
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machineFunctionInfo: {}
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body: |
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bb.0:
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liveins: $x0, $x1, $x10, $x11, $x12, $x13
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renamable $w19 = LDRWui renamable $x0, 0 :: (load 8)
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renamable $x9, renamable $x8 = LDPXi renamable $x0, 1 :: (load 8)
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STRXui renamable killed $x9, renamable $x0, 11 :: (store 8, align 4)
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renamable $x9 = LDRXui renamable $x0, 3 :: (load 8)
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renamable $x14 = LDRXui renamable $x0, 5 :: (load 8)
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STRXui renamable $x9, renamable $x0, 10 :: (store 8, align 4)
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STRXui renamable killed $x14, renamable $x0, 200 :: (store 8, align 4)
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renamable $w8 = ADDWrr $w19, $w19
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STRWui renamable $w8, renamable $x0, 100 :: (store 8, align 4)
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RET undef $lr
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...
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---
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