forked from OSchip/llvm-project
parent
62fa743e75
commit
d215af03a3
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@ -635,6 +635,27 @@ void Interpreter::executeBrInst(BranchInst &I, ExecutionContext &SF) {
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SF.CurInst = SF.CurBB->begin(); // Update new instruction ptr...
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}
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static void executeSwitch(SwitchInst &I, ExecutionContext &SF) {
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GenericValue CondVal = getOperandValue(I.getOperand(0), SF);
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const Type *ElTy = I.getOperand(0)->getType();
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SF.PrevBB = SF.CurBB; // Update PrevBB so that PHI nodes work...
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BasicBlock *Dest = 0;
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// Check to see if any of the cases match...
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for (unsigned i = 2, e = I.getNumOperands(); i != e; i += 2) {
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if (executeSetEQInst(CondVal,
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getOperandValue(I.getOperand(i), SF),ElTy,SF).BoolVal){
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Dest = cast<BasicBlock>(I.getOperand(i+1));
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break;
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}
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}
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if (!Dest) Dest = I.getDefaultDest(); // No cases matched: use default
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SF.CurBB = Dest; // Update CurBB to branch destination
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SF.CurInst = SF.CurBB->begin(); // Update new instruction ptr...
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}
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//===----------------------------------------------------------------------===//
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// Memory Instruction Implementations
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//===----------------------------------------------------------------------===//
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@ -1106,6 +1127,7 @@ bool Interpreter::executeInstruction() {
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// Terminators
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case Instruction::Ret: executeRetInst (cast<ReturnInst>(I), SF); break;
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case Instruction::Br: executeBrInst (cast<BranchInst>(I), SF); break;
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case Instruction::Switch: executeSwitch (cast<SwitchInst>(I), SF); break;
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// Memory Instructions
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case Instruction::Alloca:
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case Instruction::Malloc: executeAllocInst((AllocationInst&)I, SF); break;
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