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[RegisterBank] Rename RegisterBank::contains into RegisterBank::covers. 

llvm-svn: 265695
This commit is contained in:
Quentin Colombet 2016-04-07 17:09:39 +00:00
parent ec63c92916
commit d21115876c
4 changed files with 13 additions and 13 deletions
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4
llvm/include/llvm/CodeGen/GlobalISel/RegisterBank.h
View File

@ -63,11 +63,11 @@ public:
/// if it has been properly constructed.
void verify(const TargetRegisterInfo &TRI) const;
/// Check whether this register bank contains \p RC.
/// Check whether this register bank covers \p RC.
/// In other words, check if this register bank fully covers
/// the registers that \p RC contains.
/// \pre isValid()
bool contains(const TargetRegisterClass &RC) const;
bool covers(const TargetRegisterClass &RC) const;
/// Check whether \p OtherRB is the same as this.
bool operator==(const RegisterBank &OtherRB) const;

10
llvm/lib/CodeGen/GlobalISel/RegisterBank.cpp
View File

@ -29,14 +29,14 @@ void RegisterBank::verify(const TargetRegisterInfo &TRI) const {
for (unsigned RCId = 0, End = TRI.getNumRegClasses(); RCId != End; ++RCId) {
const TargetRegisterClass &RC = *TRI.getRegClass(RCId);
if (!contains(RC))
if (!covers(RC))
continue;
// Verify that the register bank covers all the sub classes of the
// classes it covers.
// Use a different (slow in that case) method than
// RegisterBankInfo to find the subclasses of RC, to make sure
// both agree on the contains.
// both agree on the covers.
for (unsigned SubRCId = 0; SubRCId != End; ++SubRCId) {
const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId);
@ -47,12 +47,12 @@ void RegisterBank::verify(const TargetRegisterInfo &TRI) const {
// all the register classes it covers.
assert((getSize() >= SubRC.getSize() * 8) &&
"Size is not big enough for all the subclasses!");
assert(contains(SubRC) && "Not all subclasses are covered");
assert(covers(SubRC) && "Not all subclasses are covered");
}
}
}
bool RegisterBank::contains(const TargetRegisterClass &RC) const {
bool RegisterBank::covers(const TargetRegisterClass &RC) const {
assert(isValid() && "RB hasn't been initialized yet");
return ContainedRegClasses.test(RC.getID());
}
@ -96,7 +96,7 @@ void RegisterBank::print(raw_ostream &OS, bool IsForDebug,
for (unsigned RCId = 0, End = TRI->getNumRegClasses(); RCId != End; ++RCId) {
const TargetRegisterClass &RC = *TRI->getRegClass(RCId);
if (!contains(RC))
if (!covers(RC))
continue;
if (!IsFirst)

4
llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
View File

@ -98,8 +98,8 @@ void RegisterBankInfo::addRegBankCoverage(unsigned ID, unsigned RCId,
// Check if RB is underconstruction.
if (!RB.isValid())
RB.ContainedRegClasses.resize(NbOfRegClasses);
else if (RB.contains(*TRI.getRegClass(RCId)))
// If RB already contains this register class, there is nothing
else if (RB.covers(*TRI.getRegClass(RCId)))
// If RB already covers this register class, there is nothing
// to do.
return;

8
llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
View File

@ -33,7 +33,7 @@ AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)
addRegBankCoverage(AArch64::GPRRegBankID, AArch64::GPR64allRegClassID, TRI);
const RegisterBank &RBGPR = getRegBank(AArch64::GPRRegBankID);
(void)RBGPR;
assert(RBGPR.contains(*TRI.getRegClass(AArch64::GPR32RegClassID)) &&
assert(RBGPR.covers(*TRI.getRegClass(AArch64::GPR32RegClassID)) &&
"Subclass not added?");
assert(RBGPR.getSize() == 64 && "GPRs should hold up to 64-bit");
@ -44,9 +44,9 @@ AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)
addRegBankCoverage(AArch64::FPRRegBankID, AArch64::QQQQRegClassID, TRI);
const RegisterBank &RBFPR = getRegBank(AArch64::FPRRegBankID);
(void)RBFPR;
assert(RBFPR.contains(*TRI.getRegClass(AArch64::QQRegClassID)) &&
assert(RBFPR.covers(*TRI.getRegClass(AArch64::QQRegClassID)) &&
"Subclass not added?");
assert(RBFPR.contains(*TRI.getRegClass(AArch64::FPR64RegClassID)) &&
assert(RBFPR.covers(*TRI.getRegClass(AArch64::FPR64RegClassID)) &&
"Subclass not added?");
assert(RBFPR.getSize() == 512 &&
"FPRs should hold up to 512-bit via QQQQ sequence");
@ -56,7 +56,7 @@ AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)
addRegBankCoverage(AArch64::CCRRegBankID, AArch64::CCRRegClassID, TRI);
const RegisterBank &RBCCR = getRegBank(AArch64::CCRRegBankID);
(void)RBCCR;
assert(RBCCR.contains(*TRI.getRegClass(AArch64::CCRRegClassID)) &&
assert(RBCCR.covers(*TRI.getRegClass(AArch64::CCRRegClassID)) &&
"Class not added?");
assert(RBCCR.getSize() == 32 && "CCR should hold up to 32-bit");