[DAGCombiner] Fix a case of 1 in non-splat vector pow2 divisor

Summary:
D42479 (rL329525) enabled SDIV combine for pow2 non-splat vector
dividers. But when there is a 1 in a vector, the instruction sequence to
be generated involves shifting a value by the number of its bit widths,
which is undefined
(c64f4dbfe3/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (L6000-L6006)).

Especially, in architectures that do not support vector instructions,
each of element in a vector will be computed separately using scalar
operations, and then the resulting value will be undef for '1' values
in a vector.

(All 1's vector is fine; only vectors mixed with 1 and others will be
affected.)

Reviewers: RKSimon, jgravelle-google

Subscribers: jfb, dschuff, sbc100, jgravelle-google, llvm-commits

Differential Revision: https://reviews.llvm.org/D46161

llvm-svn: 331092

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

@@ -2887,6 +2887,13 @@ SDValue DAGCombiner::visitSDIV(SDNode *N) {
     unsigned Idx = EltIndex++;
     if (C->isNullValue() || C->isOpaque())
       return false;
+    // The instruction sequence to be generated contains shifting C by (op size
+    // in bits - # of trailing zeros in C), which results in an undef value when
+    // C == 1. (e.g. if the op size in bits is 32, it will be (sra x , 32) if C
+    // == 1)
+    if (C->getAPIntValue().isOneValue())
+      return false;
+
     if (C->getAPIntValue().isPowerOf2())
       return true;
     if ((-C->getAPIntValue()).isPowerOf2()) {

llvm/test/CodeGen/WebAssembly/vector_sdiv.ll

@@ -0,0 +1,22 @@
+; RUN: llc < %s -asm-verbose=false -fast-isel=false -disable-wasm-fallthrough-return-opt | FileCheck %s
+
+target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
+target triple = "wasm32-unknown-unknown-elf"
+
+; Because there is a 1 in the vector, sdiv should not be reduced to shifts.
+
+; CHECK-LABEL: vector_sdiv:
+; CHECK-DAG:  i32.store
+; CHECK-DAG:  i32.div_s
+; CHECK-DAG:  i32.store
+; CHECK-DAG:  i32.div_s
+; CHECK-DAG:  i32.store
+; CHECK-DAG:  i32.div_s
+; CHECK-DAG:  i32.store
+define void @vector_sdiv(<4 x i32>* %x, <4 x i32>* readonly %y) {
+entry:
+  %0 = load <4 x i32>, <4 x i32>* %y, align 16
+  %div = sdiv <4 x i32> %0, <i32 1, i32 4, i32 2, i32 8>
+  store <4 x i32> %div, <4 x i32>* %x, align 16
+  ret void
+}