forked from OSchip/llvm-project
[ARM][NFC] Fix test inlineasm-X-allocation.ll
Differential Revision: https://reviews.llvm.org/D53748 llvm-svn: 345491
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@ -1,21 +1,20 @@
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; RUN: llc -mtriple=armv7-none-eabi -mattr=-neon,-vfpv2 %s -o - | FileCheck %s -check-prefix=novfp
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; RUN: llc -mtriple=armv7-none-eabi -mattr=+neon %s -float-abi=hard -o - | FileCheck %s -check-prefix=vfp
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; RUN: llc -mtriple=armv7-none-eabi -mattr=-neon,-vfp2 %s -o - | FileCheck %s -check-prefixes=COMMON,NOVFP
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; RUN: llc -mtriple=armv7-none-eabi -mattr=+neon %s -float-abi=hard -o - | FileCheck %s -check-prefixes=COMMON,VFP
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; vfp-LABEL: f1
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; vfp-CHECK: vadd.f32 s0, s0, s0
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; The intent here is to test "X", which says that any operand whatsoever is allowed.
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; Using this mechanism, we want to test toggling allocating GPR or SPR registers
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; depending on whether the float registers are available. Thus, the mnemonic is
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; totally irrelevant here, which is why we use FOO and also comment it out using "@"
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; to avoid assembler errors.
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; In the novfp case, the compiler is forced to assign a core register.
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; Although this register class can't be used with the vadd.f32 instruction,
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; the compiler behaved as expected since it is allowed to emit anything.
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; Note that this kind of IR can be generated by a function such as:
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; void f1(float f) {asm volatile ("@FOO $0, $0" : : "X" (f));}
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; novfp-LABEL: f1
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; novfp-CHECK: vadd.f32 r0, r0, r0
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; This can be generated by a function such as:
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; void f1(float f) {asm volatile ("add.f32 $0, $0, $0" : : "X" (f));}
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define arm_aapcs_vfpcc void @f1(float %f) {
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define arm_aapcs_vfpcc void @func(float %f) {
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; COMMON-LABEL: func
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; NOVFP: FOO r0, r0
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; VFP: FOO s0, s0
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entry:
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call void asm sideeffect "vadd.f32 $0, $0, $0", "X" (float %f) nounwind
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call void asm sideeffect "@FOO $0, $0", "X" (float %f) nounwind
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ret void
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}
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