forked from OSchip/llvm-project
This patch splits apart PPCISelLowering::LowerFormalArguments_Darwin_Or_64SVR4
into separate versions for the Darwin and 64-bit SVR4 ABIs. This will facilitate doing more major surgery on the 64-bit SVR4 ABI in the near future. llvm-svn: 165336
This commit is contained in:
Bill Schmidt
parent
8b76113f05
commit
d1fa36f903
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@ -1716,12 +1716,16 @@ PPCTargetLowering::LowerFormalArguments(SDValue Chain,
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DebugLoc dl, SelectionDAG &DAG,
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals)
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SmallVectorImpl<SDValue> &InVals)
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const {
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const {
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if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) {
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if (PPCSubTarget.isSVR4ABI()) {
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return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
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if (PPCSubTarget.isPPC64())
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dl, DAG, InVals);
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return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
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dl, DAG, InVals);
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else
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return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
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dl, DAG, InVals);
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} else {
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} else {
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return LowerFormalArguments_Darwin_Or_64SVR4(Chain, CallConv, isVarArg, Ins,
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return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
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dl, DAG, InVals);
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dl, DAG, InVals);
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}
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}
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}
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}
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@ -1944,7 +1948,295 @@ PPCTargetLowering::LowerFormalArguments_32SVR4(
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}
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}
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SDValue
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SDValue
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PPCTargetLowering::LowerFormalArguments_Darwin_Or_64SVR4(
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PPCTargetLowering::LowerFormalArguments_64SVR4(
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SDValue Chain,
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CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::InputArg>
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&Ins,
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DebugLoc dl, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &InVals) const {
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// TODO: add description of PPC stack frame format, or at least some docs.
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//
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MachineFunction &MF = DAG.getMachineFunction();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
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EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
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// Potential tail calls could cause overwriting of argument stack slots.
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bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
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(CallConv == CallingConv::Fast));
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unsigned PtrByteSize = 8;
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unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true);
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// Area that is at least reserved in caller of this function.
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unsigned MinReservedArea = ArgOffset;
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static const uint16_t GPR[] = {
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PPC::X3, PPC::X4, PPC::X5, PPC::X6,
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PPC::X7, PPC::X8, PPC::X9, PPC::X10,
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};
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static const uint16_t *FPR = GetFPR();
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static const uint16_t VR[] = {
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PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
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PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
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};
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const unsigned Num_GPR_Regs = array_lengthof(GPR);
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const unsigned Num_FPR_Regs = 13;
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const unsigned Num_VR_Regs = array_lengthof(VR);
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unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
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// Add DAG nodes to load the arguments or copy them out of registers. On
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// entry to a function on PPC, the arguments start after the linkage area,
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// although the first ones are often in registers.
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SmallVector<SDValue, 8> MemOps;
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unsigned nAltivecParamsAtEnd = 0;
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Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
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for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo, ++FuncArg) {
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SDValue ArgVal;
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bool needsLoad = false;
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EVT ObjectVT = Ins[ArgNo].VT;
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unsigned ObjSize = ObjectVT.getSizeInBits()/8;
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unsigned ArgSize = ObjSize;
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ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
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unsigned CurArgOffset = ArgOffset;
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// Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
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if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
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ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
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if (isVarArg) {
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MinReservedArea = ((MinReservedArea+15)/16)*16;
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MinReservedArea += CalculateStackSlotSize(ObjectVT,
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Flags,
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PtrByteSize);
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} else
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nAltivecParamsAtEnd++;
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} else
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// Calculate min reserved area.
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MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
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Flags,
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PtrByteSize);
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// FIXME the codegen can be much improved in some cases.
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// We do not have to keep everything in memory.
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if (Flags.isByVal()) {
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// ObjSize is the true size, ArgSize rounded up to multiple of registers.
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ObjSize = Flags.getByValSize();
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ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
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// All aggregates smaller than 8 bytes must be passed right-justified.
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if (ObjSize==1 || ObjSize==2) {
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CurArgOffset = CurArgOffset + (4 - ObjSize);
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}
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// The value of the object is its address.
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int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
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SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
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InVals.push_back(FIN);
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if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
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if (GPR_idx != Num_GPR_Regs) {
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unsigned VReg;
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VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
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SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
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EVT ObjType = (ObjSize == 1 ? MVT::i8 :
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(ObjSize == 2 ? MVT::i16 : MVT::i32));
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SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
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MachinePointerInfo(FuncArg,
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CurArgOffset),
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ObjType, false, false, 0);
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MemOps.push_back(Store);
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++GPR_idx;
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}
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ArgOffset += PtrByteSize;
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continue;
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}
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for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
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// Store whatever pieces of the object are in registers
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// to memory. ArgOffset will be the address of the beginning
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// of the object.
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if (GPR_idx != Num_GPR_Regs) {
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unsigned VReg;
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VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
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int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
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SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
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SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
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SDValue Shifted = Val;
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// For 64-bit SVR4, small structs come in right-adjusted.
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// Shift them left so the following logic works as expected.
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if (ObjSize < 8) {
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SDValue ShiftAmt = DAG.getConstant(64 - 8 * ObjSize, PtrVT);
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Shifted = DAG.getNode(ISD::SHL, dl, PtrVT, Val, ShiftAmt);
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}
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SDValue Store = DAG.getStore(Val.getValue(1), dl, Shifted, FIN,
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MachinePointerInfo(FuncArg, ArgOffset),
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false, false, 0);
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MemOps.push_back(Store);
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++GPR_idx;
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ArgOffset += PtrByteSize;
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} else {
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ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
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break;
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}
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}
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continue;
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}
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switch (ObjectVT.getSimpleVT().SimpleTy) {
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default: llvm_unreachable("Unhandled argument type!");
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case MVT::i32:
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case MVT::i64:
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if (GPR_idx != Num_GPR_Regs) {
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unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
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ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
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if (ObjectVT == MVT::i32) {
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// PPC64 passes i8, i16, and i32 values in i64 registers. Promote
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// value to MVT::i64 and then truncate to the correct register size.
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if (Flags.isSExt())
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ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
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DAG.getValueType(ObjectVT));
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else if (Flags.isZExt())
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ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
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DAG.getValueType(ObjectVT));
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ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
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}
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++GPR_idx;
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} else {
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needsLoad = true;
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ArgSize = PtrByteSize;
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}
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ArgOffset += 8;
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break;
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case MVT::f32:
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case MVT::f64:
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// Every 8 bytes of argument space consumes one of the GPRs available for
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// argument passing.
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if (GPR_idx != Num_GPR_Regs) {
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++GPR_idx;
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}
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if (FPR_idx != Num_FPR_Regs) {
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unsigned VReg;
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if (ObjectVT == MVT::f32)
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VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
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else
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VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
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ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
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++FPR_idx;
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} else {
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needsLoad = true;
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}
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ArgOffset += 8;
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break;
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case MVT::v4f32:
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case MVT::v4i32:
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case MVT::v8i16:
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case MVT::v16i8:
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// Note that vector arguments in registers don't reserve stack space,
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// except in varargs functions.
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if (VR_idx != Num_VR_Regs) {
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unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
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ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
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if (isVarArg) {
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while ((ArgOffset % 16) != 0) {
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ArgOffset += PtrByteSize;
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if (GPR_idx != Num_GPR_Regs)
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GPR_idx++;
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}
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ArgOffset += 16;
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GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
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}
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++VR_idx;
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} else {
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// Vectors are aligned.
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ArgOffset = ((ArgOffset+15)/16)*16;
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CurArgOffset = ArgOffset;
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ArgOffset += 16;
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needsLoad = true;
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}
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break;
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}
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// We need to load the argument to a virtual register if we determined
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// above that we ran out of physical registers of the appropriate type.
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if (needsLoad) {
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int FI = MFI->CreateFixedObject(ObjSize,
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CurArgOffset + (ArgSize - ObjSize),
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isImmutable);
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SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
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ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
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false, false, false, 0);
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}
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InVals.push_back(ArgVal);
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}
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// Set the size that is at least reserved in caller of this function. Tail
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// call optimized function's reserved stack space needs to be aligned so that
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// taking the difference between two stack areas will result in an aligned
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// stack.
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PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
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// Add the Altivec parameters at the end, if needed.
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if (nAltivecParamsAtEnd) {
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MinReservedArea = ((MinReservedArea+15)/16)*16;
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MinReservedArea += 16*nAltivecParamsAtEnd;
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}
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MinReservedArea =
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std::max(MinReservedArea,
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PPCFrameLowering::getMinCallFrameSize(true, true));
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unsigned TargetAlign
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= DAG.getMachineFunction().getTarget().getFrameLowering()->
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getStackAlignment();
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unsigned AlignMask = TargetAlign-1;
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MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
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FI->setMinReservedArea(MinReservedArea);
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// If the function takes variable number of arguments, make a frame index for
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// the start of the first vararg value... for expansion of llvm.va_start.
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if (isVarArg) {
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int Depth = ArgOffset;
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FuncInfo->setVarArgsFrameIndex(
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MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
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Depth, true));
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SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
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// If this function is vararg, store any remaining integer argument regs
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// to their spots on the stack so that they may be loaded by deferencing the
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// result of va_next.
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for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
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unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
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SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
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SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
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MachinePointerInfo(), false, false, 0);
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MemOps.push_back(Store);
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// Increment the address by four for the next argument to store
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SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
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FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
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}
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}
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if (!MemOps.empty())
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Chain = DAG.getNode(ISD::TokenFactor, dl,
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MVT::Other, &MemOps[0], MemOps.size());
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return Chain;
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}
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SDValue
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PPCTargetLowering::LowerFormalArguments_Darwin(
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SDValue Chain,
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SDValue Chain,
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CallingConv::ID CallConv, bool isVarArg,
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CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::InputArg>
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const SmallVectorImpl<ISD::InputArg>
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@ -1959,7 +2251,6 @@ PPCTargetLowering::LowerFormalArguments_Darwin_Or_64SVR4(
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EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
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EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
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bool isPPC64 = PtrVT == MVT::i64;
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bool isPPC64 = PtrVT == MVT::i64;
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bool isSVR4ABI = PPCSubTarget.isSVR4ABI();
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// Potential tail calls could cause overwriting of argument stack slots.
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// Potential tail calls could cause overwriting of argument stack slots.
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bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
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bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
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(CallConv == CallingConv::Fast));
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(CallConv == CallingConv::Fast));
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@ -2080,11 +2371,8 @@ PPCTargetLowering::LowerFormalArguments_Darwin_Or_64SVR4(
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// ObjSize is the true size, ArgSize rounded up to multiple of registers.
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// ObjSize is the true size, ArgSize rounded up to multiple of registers.
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ObjSize = Flags.getByValSize();
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ObjSize = Flags.getByValSize();
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ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
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ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
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// FOR DARWIN: Objects of size 1 and 2 are right justified, everything
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// Objects of size 1 and 2 are right justified, everything else is
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// else is left justified. This means the memory address is adjusted
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// left justified. This means the memory address is adjusted forwards.
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// forwards.
|
|
||||||
// FOR 64-BIT SVR4: All aggregates smaller than 8 bytes must be passed
|
|
||||||
// right-justified.
|
|
||||||
if (ObjSize==1 || ObjSize==2) {
|
if (ObjSize==1 || ObjSize==2) {
|
||||||
CurArgOffset = CurArgOffset + (4 - ObjSize);
|
CurArgOffset = CurArgOffset + (4 - ObjSize);
|
||||||
}
|
}
|
||||||
|
|
@ -2092,8 +2380,7 @@ PPCTargetLowering::LowerFormalArguments_Darwin_Or_64SVR4(
|
||||||
int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
|
int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
|
||||||
SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
|
SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
|
||||||
InVals.push_back(FIN);
|
InVals.push_back(FIN);
|
||||||
if (ObjSize==1 || ObjSize==2 ||
|
if (ObjSize==1 || ObjSize==2) {
|
||||||
(ObjSize==4 && isSVR4ABI)) {
|
|
||||||
if (GPR_idx != Num_GPR_Regs) {
|
if (GPR_idx != Num_GPR_Regs) {
|
||||||
unsigned VReg;
|
unsigned VReg;
|
||||||
if (isPPC64)
|
if (isPPC64)
|
||||||
|
|
@ -2128,16 +2415,7 @@ PPCTargetLowering::LowerFormalArguments_Darwin_Or_64SVR4(
|
||||||
int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
|
int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
|
||||||
SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
|
SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
|
||||||
SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
|
SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
|
||||||
SDValue Shifted = Val;
|
SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
|
||||||
|
|
||||||
// For 64-bit SVR4, small structs come in right-adjusted.
|
|
||||||
// Shift them left so the following logic works as expected.
|
|
||||||
if (ObjSize < 8 && isSVR4ABI) {
|
|
||||||
SDValue ShiftAmt = DAG.getConstant(64 - 8 * ObjSize, PtrVT);
|
|
||||||
Shifted = DAG.getNode(ISD::SHL, dl, PtrVT, Val, ShiftAmt);
|
|
||||||
}
|
|
||||||
|
|
||||||
SDValue Store = DAG.getStore(Val.getValue(1), dl, Shifted, FIN,
|
|
||||||
MachinePointerInfo(FuncArg, ArgOffset),
|
MachinePointerInfo(FuncArg, ArgOffset),
|
||||||
false, false, 0);
|
false, false, 0);
|
||||||
MemOps.push_back(Store);
|
MemOps.push_back(Store);
|
||||||
|
|
|
||||||
|
|
@ -467,7 +467,13 @@ namespace llvm {
|
||||||
DebugLoc dl, SelectionDAG &DAG) const;
|
DebugLoc dl, SelectionDAG &DAG) const;
|
||||||
|
|
||||||
SDValue
|
SDValue
|
||||||
LowerFormalArguments_Darwin_Or_64SVR4(SDValue Chain,
|
LowerFormalArguments_Darwin(SDValue Chain,
|
||||||
|
CallingConv::ID CallConv, bool isVarArg,
|
||||||
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||||
|
DebugLoc dl, SelectionDAG &DAG,
|
||||||
|
SmallVectorImpl<SDValue> &InVals) const;
|
||||||
|
SDValue
|
||||||
|
LowerFormalArguments_64SVR4(SDValue Chain,
|
||||||
CallingConv::ID CallConv, bool isVarArg,
|
CallingConv::ID CallConv, bool isVarArg,
|
||||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||||
DebugLoc dl, SelectionDAG &DAG,
|
DebugLoc dl, SelectionDAG &DAG,
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue