forked from OSchip/llvm-project
[AMDGPU][NFC] Fix typos
Differential Revision: https://reviews.llvm.org/D113672
This commit is contained in:
Neubauer, Sebastian
parent
5dfe60d171
commit
d1f45ed58f
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@ -415,7 +415,7 @@ def FeatureDPP : SubtargetFeature<"dpp",
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"Support DPP (Data Parallel Primitives) extension"
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>;
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// DPP8 allows arbitrary cross-lane swizzling withing groups of 8 lanes.
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// DPP8 allows arbitrary cross-lane swizzling within groups of 8 lanes.
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def FeatureDPP8 : SubtargetFeature<"dpp8",
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"HasDPP8",
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"true",
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@ -76,8 +76,8 @@ struct ImageDimIntrinsicInfo {
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};
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const ImageDimIntrinsicInfo *getImageDimIntrinsicInfo(unsigned Intr);
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const ImageDimIntrinsicInfo *getImageDimInstrinsicByBaseOpcode(unsigned BaseOpcode,
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unsigned Dim);
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const ImageDimIntrinsicInfo *
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getImageDimIntrinsicByBaseOpcode(unsigned BaseOpcode, unsigned Dim);
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} // end AMDGPU namespace
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} // End llvm namespace
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@ -4408,8 +4408,8 @@ bool AMDGPULegalizerInfo::legalizeImageIntrinsic(
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if (ConstantLod->isZero() || ConstantLod->isNegative()) {
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// Set new opcode to _lz variant of _l, and change the intrinsic ID.
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const AMDGPU::ImageDimIntrinsicInfo *NewImageDimIntr =
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AMDGPU::getImageDimInstrinsicByBaseOpcode(LZMappingInfo->LZ,
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Intr->Dim);
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AMDGPU::getImageDimIntrinsicByBaseOpcode(LZMappingInfo->LZ,
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Intr->Dim);
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// The starting indexes should remain in the same place.
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--CorrectedNumVAddrs;
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@ -109,8 +109,8 @@ public:
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Register Den) const;
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void legalizeUnsignedDIV_REM64Impl(MachineIRBuilder &B, Register DstDivReg,
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Register DstRemReg, Register Numer,
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Register Denom) const;
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Register DstRemReg, Register Num,
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Register Den) const;
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bool legalizeSignedDIV_REM(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &B) const;
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@ -125,7 +125,7 @@ private:
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BasicBlock::iterator getEntryIns(CallInst * UI);
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// Insert an Alloc instruction.
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AllocaInst* insertAlloca(CallInst * UI, IRBuilder<> &B, const char *prefix);
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// Get a scalar native builtin signle argument FP function
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// Get a scalar native builtin single argument FP function
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FunctionCallee getNativeFunction(Module *M, const FuncInfo &FInfo);
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protected:
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@ -455,7 +455,8 @@ AMDGPULibFunc::Param ParamIterator::getNextParam() {
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break;
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}
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default: llvm_unreachable("Unhandeled param rule");
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default:
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llvm_unreachable("Unhandled param rule");
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}
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}
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++Index;
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@ -747,7 +748,8 @@ static const char *getItaniumTypeName(AMDGPULibFunc::EType T) {
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case AMDGPULibFunc::IMG3D: return "11ocl_image3d";
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case AMDGPULibFunc::SAMPLER: return "11ocl_sampler";
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case AMDGPULibFunc::EVENT: return "9ocl_event";
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default: llvm_unreachable("Unhandeled param type");
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default:
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llvm_unreachable("Unhandled param type");
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}
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return nullptr;
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}
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@ -761,7 +763,7 @@ namespace {
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// substitution candidates from the grammar, but are explicitly excluded:
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// 1. <builtin-type> other than vendor extended types ..."
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// For the purpose of functions the following productions make sence for the
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// For the purpose of functions the following productions make sense for the
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// substitution:
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// <type> ::= <builtin-type>
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// ::= <class-enum-type>
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@ -774,8 +776,8 @@ namespace {
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// using <class-enum-type> production rule they're not used for substitution
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// because clang consider them as builtin types.
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//
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// DvNN_ type is GCC extension for vectors and is a subject for the substitution.
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// DvNN_ type is GCC extension for vectors and is a subject for the
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// substitution.
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class ItaniumMangler {
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SmallVector<AMDGPULibFunc::Param, 10> Str; // list of accumulated substitutions
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@ -902,7 +904,7 @@ static Type* getIntrinsicParamType(
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case AMDGPULibFunc::EVENT:
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T = StructType::create(C,"ocl_event")->getPointerTo(); break;
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default:
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llvm_unreachable("Unhandeled param type");
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llvm_unreachable("Unhandled param type");
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return nullptr;
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}
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if (P.VectorSize > 1)
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@ -13,7 +13,7 @@
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//
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// In LLVM CodeGen the runtime-handle metadata will be translated to
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// RuntimeHandle metadata in code object. Runtime allocates a global buffer
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// for each kernel with RuntimeHandel metadata and saves the kernel address
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// for each kernel with RuntimeHandle metadata and saves the kernel address
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// required for the AQL packet into the buffer. __enqueue_kernel function
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// in device library knows that the invoke function pointer in the block
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// literal is actually runtime handle and loads the kernel address from it
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@ -274,7 +274,7 @@ AMDGPUPromoteAllocaImpl::getLocalSizeYZ(IRBuilder<> &Builder) {
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// We could do a single 64-bit load here, but it's likely that the basic
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// 32-bit and extract sequence is already present, and it is probably easier
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// to CSE this. The loads should be mergable later anyway.
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// to CSE this. The loads should be mergeable later anyway.
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Value *GEPXY = Builder.CreateConstInBoundsGEP1_64(I32Ty, CastDispatchPtr, 1);
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LoadInst *LoadXY = Builder.CreateAlignedLoad(I32Ty, GEPXY, Align(4));
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@ -251,7 +251,7 @@ public:
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uint64_t getExplicitKernArgSize(const Function &F, Align &MaxAlign) const;
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unsigned getKernArgSegmentSize(const Function &F, Align &MaxAlign) const;
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/// \returns Corresponsing DWARF register number mapping flavour for the
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/// \returns Corresponding DWARF register number mapping flavour for the
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/// \p WavefrontSize.
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AMDGPUDwarfFlavour getAMDGPUDwarfFlavour() const;
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@ -1545,7 +1545,7 @@ int GCNHazardRecognizer::checkMAIHazards90A(MachineInstr *MI) {
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}
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int GCNHazardRecognizer::checkMAILdStHazards(MachineInstr *MI) {
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// On gfx90a+ releveant hazards are checked in checkMAIVALUHazards()
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// On gfx90a+ relevant hazards are checked in checkMAIVALUHazards()
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if (!ST.hasMAIInsts() || ST.hasGFX90AInsts())
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return 0;
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@ -188,7 +188,7 @@ public:
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printRegion(dbgs(), Rgn.Begin, Rgn.End, Sch.LIS, 2));
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Sch.BaseClass::schedule();
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// Unfortunatelly placeDebugValues incorrectly modifies RegionEnd, restore
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// Unfortunately placeDebugValues incorrectly modifies RegionEnd, restore
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Sch.RegionEnd = Rgn.End;
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//assert(Rgn.End == Sch.RegionEnd);
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Rgn.Begin = Sch.RegionBegin;
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@ -280,7 +280,7 @@ GCNIterativeScheduler::getSchedulePressure(const Region &R,
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return RPTracker.moveMaxPressure();
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}
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void GCNIterativeScheduler::enterRegion(MachineBasicBlock *BB, // overriden
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void GCNIterativeScheduler::enterRegion(MachineBasicBlock *BB, // overridden
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MachineBasicBlock::iterator Begin,
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MachineBasicBlock::iterator End,
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unsigned NumRegionInstrs) {
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@ -293,7 +293,7 @@ void GCNIterativeScheduler::enterRegion(MachineBasicBlock *BB, // overriden
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}
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}
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void GCNIterativeScheduler::schedule() { // overriden
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void GCNIterativeScheduler::schedule() { // overridden
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// do nothing
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LLVM_DEBUG(printLivenessInfo(dbgs(), RegionBegin, RegionEnd, LIS);
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if (!Regions.empty() && Regions.back()->Begin == RegionBegin) {
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@ -304,7 +304,7 @@ void GCNIterativeScheduler::schedule() { // overriden
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<< '\n';);
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}
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void GCNIterativeScheduler::finalizeSchedule() { // overriden
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void GCNIterativeScheduler::finalizeSchedule() { // overridden
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if (Regions.empty())
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return;
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switch (Strategy) {
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@ -391,8 +391,8 @@ void GCNIterativeScheduler::scheduleRegion(Region &R, Range &&Schedule,
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// and already interleaved with debug values
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if (!std::is_same<decltype(*Schedule.begin()), MachineInstr*>::value) {
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placeDebugValues();
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// Unfortunatelly placeDebugValues incorrectly modifies RegionEnd, restore
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//assert(R.End == RegionEnd);
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// Unfortunately placeDebugValues incorrectly modifies RegionEnd, restore
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// assert(R.End == RegionEnd);
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RegionEnd = R.End;
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}
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@ -7,7 +7,7 @@
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file defines and imlements the class GCNMinRegScheduler, which
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/// This file defines and implements the class GCNMinRegScheduler, which
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/// implements an experimental, simple scheduler whose main goal is to learn
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/// ways about consuming less possible registers for a region.
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///
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@ -7,7 +7,7 @@
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// This pass combines split register tuple initialization into a single psuedo:
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/// This pass combines split register tuple initialization into a single pseudo:
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///
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/// undef %0.sub1:sreg_64 = S_MOV_B32 1
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/// %0.sub0:sreg_64 = S_MOV_B32 2
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@ -121,7 +121,7 @@ void GCNMaxOccupancySchedStrategy::initCandidate(SchedCandidate &Cand, SUnit *SU
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// Register pressure is considered 'CRITICAL' if it is approaching a value
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// that would reduce the wave occupancy for the execution unit. When
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// register pressure is 'CRITICAL', increading SGPR and VGPR pressure both
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// register pressure is 'CRITICAL', increasing SGPR and VGPR pressure both
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// has the same cost, so we don't need to prefer one over the other.
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int SGPRDelta = NewSGPRPressure - SGPRCriticalLimit;
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@ -60,7 +60,7 @@ class AMDGPUCustomBehaviour : public CustomBehaviour {
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/// where we setup the InstrWaitCntInfo vector.
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/// The core logic for determining which CNTs an instruction
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/// interacts with is taken from SIInsertWaitcnts::updateEventWaitcntAfter().
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/// Unfortunately, some of the logic from that function is not avalable to us
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/// Unfortunately, some of the logic from that function is not available to us
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/// in this scope so we conservatively end up assuming that some
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/// instructions interact with more CNTs than they do in reality.
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void generateWaitCntInfo();
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@ -1108,7 +1108,7 @@ def ImageDimIntrinsicTable : GenericTable {
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let PrimaryKeyEarlyOut = 1;
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}
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def getImageDimInstrinsicByBaseOpcode : SearchIndex {
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def getImageDimIntrinsicByBaseOpcode : SearchIndex {
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let Table = ImageDimIntrinsicTable;
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let Key = ["BaseOpcode", "Dim"];
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}
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@ -926,7 +926,7 @@ SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
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std::swap(LHS, RHS);
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CC = DAG.getCondCode(CCSwapped);
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} else {
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// Try inverting the conditon and then swapping the operands
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// Try inverting the condition and then swapping the operands
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ISD::CondCode CCInv = ISD::getSetCCInverse(CCOpcode, CompareVT);
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CCSwapped = ISD::getSetCCSwappedOperands(CCInv);
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if (isCondCodeLegal(CCSwapped, CompareVT.getSimpleVT())) {
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@ -175,7 +175,7 @@ public:
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int *BytesAdded = nullptr) const override;
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unsigned removeBranch(MachineBasicBlock &MBB,
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int *BytesRemvoed = nullptr) const override;
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int *BytesRemoved = nullptr) const override;
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bool isPredicated(const MachineInstr &MI) const override;
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@ -1346,7 +1346,7 @@ let Predicates = [isR600] in {
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//===----------------------------------------------------------------------===//
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// Regist loads and stores - for indirect addressing
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// Register loads and stores - for indirect addressing
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//===----------------------------------------------------------------------===//
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let Namespace = "R600" in {
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@ -29,7 +29,7 @@ void R600SchedStrategy::initialize(ScheduleDAGMI *dag) {
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MRI = &DAG->MRI;
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CurInstKind = IDOther;
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CurEmitted = 0;
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OccupedSlotsMask = 31;
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OccupiedSlotsMask = 31;
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InstKindLimit[IDAlu] = TII->getMaxAlusPerClause();
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InstKindLimit[IDOther] = 32;
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InstKindLimit[IDFetch] = ST.getTexVTXClauseSize();
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@ -138,7 +138,7 @@ void R600SchedStrategy::schedNode(SUnit *SU, bool IsTopNode) {
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if (NextInstKind != CurInstKind) {
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LLVM_DEBUG(dbgs() << "Instruction Type Switch\n");
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if (NextInstKind != IDAlu)
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OccupedSlotsMask |= 31;
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OccupiedSlotsMask |= 31;
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CurEmitted = 0;
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CurInstKind = NextInstKind;
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}
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@ -339,10 +339,10 @@ void R600SchedStrategy::LoadAlu() {
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void R600SchedStrategy::PrepareNextSlot() {
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LLVM_DEBUG(dbgs() << "New Slot\n");
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assert (OccupedSlotsMask && "Slot wasn't filled");
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OccupedSlotsMask = 0;
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// if (HwGen == AMDGPUSubtarget::NORTHERN_ISLANDS)
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// OccupedSlotsMask |= 16;
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assert(OccupiedSlotsMask && "Slot wasn't filled");
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OccupiedSlotsMask = 0;
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// if (HwGen == AMDGPUSubtarget::NORTHERN_ISLANDS)
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// OccupiedSlotsMask |= 16;
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InstructionsGroupCandidate.clear();
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LoadAlu();
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}
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@ -400,41 +400,41 @@ unsigned R600SchedStrategy::AvailablesAluCount() const {
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SUnit* R600SchedStrategy::pickAlu() {
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while (AvailablesAluCount() || !Pending[IDAlu].empty()) {
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if (!OccupedSlotsMask) {
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if (!OccupiedSlotsMask) {
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// Bottom up scheduling : predX must comes first
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if (!AvailableAlus[AluPredX].empty()) {
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OccupedSlotsMask |= 31;
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OccupiedSlotsMask |= 31;
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return PopInst(AvailableAlus[AluPredX], false);
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}
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// Flush physical reg copies (RA will discard them)
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if (!AvailableAlus[AluDiscarded].empty()) {
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OccupedSlotsMask |= 31;
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OccupiedSlotsMask |= 31;
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return PopInst(AvailableAlus[AluDiscarded], false);
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}
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// If there is a T_XYZW alu available, use it
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if (!AvailableAlus[AluT_XYZW].empty()) {
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OccupedSlotsMask |= 15;
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OccupiedSlotsMask |= 15;
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return PopInst(AvailableAlus[AluT_XYZW], false);
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}
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}
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bool TransSlotOccuped = OccupedSlotsMask & 16;
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if (!TransSlotOccuped && VLIW5) {
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bool TransSlotOccupied = OccupiedSlotsMask & 16;
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if (!TransSlotOccupied && VLIW5) {
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if (!AvailableAlus[AluTrans].empty()) {
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OccupedSlotsMask |= 16;
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OccupiedSlotsMask |= 16;
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return PopInst(AvailableAlus[AluTrans], false);
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}
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SUnit *SU = AttemptFillSlot(3, true);
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if (SU) {
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OccupedSlotsMask |= 16;
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OccupiedSlotsMask |= 16;
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return SU;
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}
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}
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for (int Chan = 3; Chan > -1; --Chan) {
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bool isOccupied = OccupedSlotsMask & (1 << Chan);
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bool isOccupied = OccupiedSlotsMask & (1 << Chan);
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if (!isOccupied) {
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SUnit *SU = AttemptFillSlot(Chan, false);
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if (SU) {
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OccupedSlotsMask |= (1 << Chan);
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OccupiedSlotsMask |= (1 << Chan);
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InstructionsGroupCandidate.push_back(SU->getInstr());
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return SU;
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}
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@ -63,7 +63,7 @@ class R600SchedStrategy final : public MachineSchedStrategy {
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int InstKindLimit[IDLast];
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int OccupedSlotsMask;
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int OccupiedSlotsMask;
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public:
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R600SchedStrategy() = default;
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@ -228,7 +228,7 @@ static bool updateOperand(FoldCandidate &Fold,
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MachineOperand &Mod = MI->getOperand(ModIdx);
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unsigned Val = Mod.getImm();
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if (!(Val & SISrcMods::OP_SEL_0) && (Val & SISrcMods::OP_SEL_1)) {
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// Only apply the following transformation if that operand requries
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// Only apply the following transformation if that operand requires
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// a packed immediate.
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switch (TII.get(Opcode).OpInfo[OpNo].OperandType) {
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case AMDGPU::OPERAND_REG_IMM_V2FP16:
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@ -688,7 +688,7 @@ void SIFoldOperands::foldOperand(
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// Don't fold into a copy to a physical register with the same class. Doing
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// so would interfere with the register coalescer's logic which would avoid
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// redundant initalizations.
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// redundant initializations.
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if (DestReg.isPhysical() && SrcRC->contains(DestReg))
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return;
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@ -902,7 +902,7 @@ void SIFoldOperands::foldOperand(
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tryAddToFoldList(FoldList, UseMI, UseOpIdx, &OpToFold, TII);
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// FIXME: We could try to change the instruction from 64-bit to 32-bit
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// to enable more folding opportunites. The shrink operands pass
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// to enable more folding opportunities. The shrink operands pass
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// already does this.
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return;
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}
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@ -73,7 +73,7 @@ public:
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// Class of object that encapsulates latest instruction counter score
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// associated with the operand. Used for determining whether
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// s_waitcnt instruction needs to be emited.
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// s_waitcnt instruction needs to be emitted.
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#define CNT_MASK(t) (1u << (t))
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@ -146,7 +146,7 @@ class SILoadStoreOptimizer : public MachineFunctionPass {
|
|||
if (!AddrOp->isReg())
|
||||
return false;
|
||||
|
||||
// TODO: We should be able to merge physical reg addreses.
|
||||
// TODO: We should be able to merge physical reg addresses.
|
||||
if (AddrOp->getReg().isPhysical())
|
||||
return false;
|
||||
|
||||
|
|
@ -652,7 +652,7 @@ static bool canMoveInstsAcrossMemOp(MachineInstr &MemOp,
|
|||
}
|
||||
|
||||
// This function assumes that \p A and \p B have are identical except for
|
||||
// size and offset, and they referecne adjacent memory.
|
||||
// size and offset, and they reference adjacent memory.
|
||||
static MachineMemOperand *combineKnownAdjacentMMOs(MachineFunction &MF,
|
||||
const MachineMemOperand *A,
|
||||
const MachineMemOperand *B) {
|
||||
|
|
|
|||
|
|
@ -13,7 +13,7 @@
|
|||
/// All control flow is handled using predicated instructions and
|
||||
/// a predicate stack. Each Scalar ALU controls the operations of 64 Vector
|
||||
/// ALUs. The Scalar ALU can update the predicate for any of the Vector ALUs
|
||||
/// by writting to the 64-bit EXEC register (each bit corresponds to a
|
||||
/// by writing to the 64-bit EXEC register (each bit corresponds to a
|
||||
/// single vector ALU). Typically, for predicates, a vector ALU will write
|
||||
/// to its bit of the VCC register (like EXEC VCC is 64-bits, one for each
|
||||
/// Vector ALU) and then the ScalarALU will AND the VCC register with the
|
||||
|
|
@ -38,7 +38,8 @@
|
|||
/// %vgpr0 = V_ADD_F32 %vgpr0, %vgpr0 // Do the IF block of the branch
|
||||
///
|
||||
/// label0:
|
||||
/// %sgpr0 = S_OR_SAVEEXEC_B64 %sgpr0 // Restore the exec mask for the Then block
|
||||
/// %sgpr0 = S_OR_SAVEEXEC_B64 %sgpr0 // Restore the exec mask for the Then
|
||||
/// // block
|
||||
/// %exec = S_XOR_B64 %sgpr0, %exec // Update the exec mask
|
||||
/// S_BRANCH_EXECZ label1 // Use our branch optimization
|
||||
/// // instruction again.
|
||||
|
|
|
|||
|
|
@ -368,7 +368,7 @@ bool SILowerSGPRSpills::runOnMachineFunction(MachineFunction &MF) {
|
|||
}
|
||||
|
||||
// All those frame indices which are dead by now should be removed from the
|
||||
// function frame. Othewise, there is a side effect such as re-mapping of
|
||||
// function frame. Otherwise, there is a side effect such as re-mapping of
|
||||
// free frame index ids by the later pass(es) like "stack slot coloring"
|
||||
// which in turn could mess-up with the book keeping of "frame index to VGPR
|
||||
// lane".
|
||||
|
|
|
|||
|
|
@ -403,7 +403,7 @@ void SIScheduleBlock::schedule(MachineBasicBlock::iterator BeginBlock,
|
|||
}
|
||||
|
||||
// TODO: compute InternalAdditionnalPressure.
|
||||
InternalAdditionnalPressure.resize(TopPressure.MaxSetPressure.size());
|
||||
InternalAdditionalPressure.resize(TopPressure.MaxSetPressure.size());
|
||||
|
||||
// Check everything is right.
|
||||
#ifndef NDEBUG
|
||||
|
|
|
|||
|
|
@ -72,7 +72,7 @@ class SIScheduleBlock {
|
|||
// store the live virtual and real registers.
|
||||
// We do care only of SGPR32 and VGPR32 and do track only virtual registers.
|
||||
// Pressure of additional registers required inside the block.
|
||||
std::vector<unsigned> InternalAdditionnalPressure;
|
||||
std::vector<unsigned> InternalAdditionalPressure;
|
||||
// Pressure of input and output registers
|
||||
std::vector<unsigned> LiveInPressure;
|
||||
std::vector<unsigned> LiveOutPressure;
|
||||
|
|
@ -153,8 +153,8 @@ public:
|
|||
|
||||
// Needs the block to be scheduled inside
|
||||
// TODO: find a way to compute it.
|
||||
std::vector<unsigned> &getInternalAdditionnalRegUsage() {
|
||||
return InternalAdditionnalPressure;
|
||||
std::vector<unsigned> &getInternalAdditionalRegUsage() {
|
||||
return InternalAdditionalPressure;
|
||||
}
|
||||
|
||||
std::set<unsigned> &getInRegs() { return LiveInRegs; }
|
||||
|
|
|
|||
|
|
@ -225,7 +225,7 @@ void SIModeRegister::processBlockPhase1(MachineBasicBlock &MBB,
|
|||
// RequirePending is used to indicate whether we are collecting the initial
|
||||
// requirements for the block, and need to defer the first InsertionPoint to
|
||||
// Phase 3. It is set to false once we have set FirstInsertionPoint, or when
|
||||
// we discover an explict setreg that means this block doesn't have any
|
||||
// we discover an explicit setreg that means this block doesn't have any
|
||||
// initial requirements.
|
||||
bool RequirePending = true;
|
||||
Status IPChange;
|
||||
|
|
|
|||
|
|
@ -11,7 +11,7 @@
|
|||
/// structures and waterfall loops.
|
||||
///
|
||||
/// When we do structurization, we usually transform an if-else into two
|
||||
/// sucessive if-then (with a flow block to do predicate inversion). Consider a
|
||||
/// successive if-then (with a flow block to do predicate inversion). Consider a
|
||||
/// simple case after structurization: A divergent value %a was defined before
|
||||
/// if-else and used in both THEN (use in THEN is optional) and ELSE part:
|
||||
/// bb.if:
|
||||
|
|
|
|||
|
|
@ -365,7 +365,7 @@ bool SDWASrcOperand::convertToSDWA(MachineInstr &MI, const SIInstrInfo *TII) {
|
|||
|
||||
if (Dst &&
|
||||
DstUnused->getImm() == AMDGPU::SDWA::DstUnused::UNUSED_PRESERVE) {
|
||||
// This will work if the tied src is acessing WORD_0, and the dst is
|
||||
// This will work if the tied src is accessing WORD_0, and the dst is
|
||||
// writing WORD_1. Modifiers don't matter because all the bits that
|
||||
// would be impacted are being overwritten by the dst.
|
||||
// Any other case will not work.
|
||||
|
|
|
|||
|
|
@ -8,7 +8,7 @@
|
|||
//
|
||||
/// \file
|
||||
/// This pass creates bundles of memory instructions to protect adjacent loads
|
||||
/// and stores from beeing rescheduled apart from each other post-RA.
|
||||
/// and stores from being rescheduled apart from each other post-RA.
|
||||
///
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
|
|
|
|||
|
|
@ -174,7 +174,7 @@ bool SIPreEmitPeephole::optimizeVccBranch(MachineInstr &MI) const {
|
|||
MI.setDesc(TII->get(AMDGPU::S_BRANCH));
|
||||
} else if (IsVCCZ && MaskValue == 0) {
|
||||
// Will always branch
|
||||
// Remove all succesors shadowed by new unconditional branch
|
||||
// Remove all successors shadowed by new unconditional branch
|
||||
MachineBasicBlock *Parent = MI.getParent();
|
||||
SmallVector<MachineInstr *, 4> ToRemove;
|
||||
bool Found = false;
|
||||
|
|
|
|||
|
|
@ -834,7 +834,7 @@ defm AReg_1024 : ARegClass<32, [v32i32, v32f32, v16i64, v16f64], (add AGPR_1024)
|
|||
|
||||
// This is not a real register. This is just to have a register to add
|
||||
// to VReg_1 that does not alias any real register that would
|
||||
// introduce inferred register classess.
|
||||
// introduce inferred register classes.
|
||||
def ARTIFICIAL_VGPR : SIReg <"invalid vgpr", 0> {
|
||||
let isArtificial = 1;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -188,7 +188,7 @@ static void shrinkScalarCompare(const SIInstrInfo *TII, MachineInstr &MI) {
|
|||
return;
|
||||
|
||||
// eq/ne is special because the imm16 can be treated as signed or unsigned,
|
||||
// and initially selectd to the unsigned versions.
|
||||
// and initially selected to the unsigned versions.
|
||||
if (SOPKOpc == AMDGPU::S_CMPK_EQ_U32 || SOPKOpc == AMDGPU::S_CMPK_LG_U32) {
|
||||
bool HasUImm;
|
||||
if (isKImmOrKUImmOperand(TII, Src1, HasUImm)) {
|
||||
|
|
|
|||
|
|
@ -771,7 +771,7 @@ bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo);
|
|||
/// Is this floating-point operand?
|
||||
bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);
|
||||
|
||||
/// Does this opearnd support only inlinable literals?
|
||||
/// Does this operand support only inlinable literals?
|
||||
bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
|
||||
|
||||
/// Get the size in bits of a register from the register class \p RC.
|
||||
|
|
|
|||
|
|
@ -48,7 +48,7 @@ Align getAlign(DataLayout const &DL, const GlobalVariable *GV);
|
|||
/// as an use within some instruction (either from kernel or from non-kernel).
|
||||
bool hasUserInstruction(const GlobalValue *GV);
|
||||
|
||||
/// \returns true if an LDS global requres lowering to a module LDS structure
|
||||
/// \returns true if an LDS global requires lowering to a module LDS structure
|
||||
/// if \p F is not given. If \p F is given it must be a kernel and function
|
||||
/// \returns true if an LDS global is directly used from that kernel and it
|
||||
/// is safe to replace its uses with a kernel LDS structure member.
|
||||
|
|
|
|||
Loading…
Reference in New Issue