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[X86] Canonicalize (x > 1) ? x : 1 -> (x >= 1) ? x : 1 for sign and unsigned to enable the use of test instructions for the compare. 

This will be further canonicalized to a compare involving 0
which will enable the use of test instructions. Either using
cmovg for signed for cmovne for unsigned.

Fixes more case for PR47049
This commit is contained in:
Craig Topper 2020-09-30 12:36:28 -07:00
parent ce5379f0f0
commit d1d7fc9832
2 changed files with 37 additions and 3 deletions
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16
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -40939,8 +40939,7 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
// (x > 0) ? x : 0 -> (x >= 0) ? x : 0
// (x < -1) ? x : -1 -> (x <= -1) ? x : -1
// This allows use of COND_S / COND_NS (see TranslateX86CC) which eliminates
// the need for an extra compare
// against zero. e.g.
// the need for an extra compare against zero. e.g.
// (a - b) > 0 : (a - b) ? 0 -> (a - b) >= 0 : (a - b) ? 0
// subl %esi, %edi
// testl %edi, %edi
@ -40950,17 +40949,28 @@ static SDValue combineSelect(SDNode *N, SelectionDAG &DAG,
// xorl %eax, %eax
// subl %esi, $edi
// cmovsl %eax, %edi
//
// We can also canonicalize
// (x s> 1) ? x : 1 -> (x s>= 1) ? x : 1 -> (x s> 0) ? x : 1
// (x u> 1) ? x : 1 -> (x u>= 1) ? x : 1 -> (x != 0) ? x : 1
// This allows the use of a test instruction for the compare.
if (N->getOpcode() == ISD::SELECT && Cond.getOpcode() == ISD::SETCC &&
Cond.hasOneUse() &&
LHS == Cond.getOperand(0) && RHS == Cond.getOperand(1)) {
ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
if ((CC == ISD::SETGT && isNullConstant(RHS)) ||
if ((CC == ISD::SETGT && (isNullConstant(RHS) || isOneConstant(RHS))) ||
(CC == ISD::SETLT && isAllOnesConstant(RHS))) {
ISD::CondCode NewCC = CC == ISD::SETGT ? ISD::SETGE : ISD::SETLE;
Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
Cond.getOperand(0), Cond.getOperand(1), NewCC);
return DAG.getSelect(DL, VT, Cond, LHS, RHS);
}
if (CC == ISD::SETUGT && isOneConstant(RHS)) {
ISD::CondCode NewCC = ISD::SETUGE;
Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(),
Cond.getOperand(0), Cond.getOperand(1), NewCC);
return DAG.getSelect(DL, VT, Cond, LHS, RHS);
}
}
// Match VSELECTs into subs with unsigned saturation.

24
llvm/test/CodeGen/X86/cmov.ll
View File

@ -235,3 +235,27 @@ define i32 @pr47049_2(i32 %0) {
%3 = select i1 %2, i32 %0, i32 -1
ret i32 %3
}
define i32 @pr47049_3(i32 %0) {
; CHECK-LABEL: pr47049_3:
; CHECK: # %bb.0:
; CHECK-NEXT: testl %edi, %edi
; CHECK-NEXT: movl $1, %eax
; CHECK-NEXT: cmovgl %edi, %eax
; CHECK-NEXT: retq
%2 = icmp sgt i32 %0, 1
%3 = select i1 %2, i32 %0, i32 1
ret i32 %3
}
define i32 @pr47049_4(i32 %0) {
; CHECK-LABEL: pr47049_4:
; CHECK: # %bb.0:
; CHECK-NEXT: testl %edi, %edi
; CHECK-NEXT: movl $1, %eax
; CHECK-NEXT: cmovnel %edi, %eax
; CHECK-NEXT: retq
%2 = icmp ugt i32 %0, 1
%3 = select i1 %2, i32 %0, i32 1
ret i32 %3
}