forked from OSchip/llvm-project
Finally, the entire instruction asmprinter is now generated from tblgen, woo!
llvm-svn: 15658
This commit is contained in:
Chris Lattner
parent
a0bafce127
commit
d1bee6ee12
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@ -438,8 +438,8 @@ static bool isMem(const MachineInstr *MI, unsigned Op) {
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if (MI->getOperand(Op).isFrameIndex()) return true;
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if (MI->getOperand(Op).isFrameIndex()) return true;
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if (MI->getOperand(Op).isConstantPoolIndex()) return true;
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if (MI->getOperand(Op).isConstantPoolIndex()) return true;
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return Op+4 <= MI->getNumOperands() &&
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return Op+4 <= MI->getNumOperands() &&
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MI->getOperand(Op ).isRegister() &&isScale(MI->getOperand(Op+1)) &&
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MI->getOperand(Op ).isRegister() && isScale(MI->getOperand(Op+1)) &&
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MI->getOperand(Op+2).isRegister() &&MI->getOperand(Op+3).isImmediate();
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MI->getOperand(Op+2).isRegister() && MI->getOperand(Op+3).isImmediate();
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}
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}
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@ -490,17 +490,6 @@ void X86AsmPrinter::printOp(const MachineOperand &MO,
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}
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}
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}
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}
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static const char* const sizePtr(const TargetInstrDescriptor &Desc) {
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switch (Desc.TSFlags & X86II::MemMask) {
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default: assert(0 && "Unknown arg size!");
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case X86II::Mem8: return "BYTE PTR";
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case X86II::Mem16: return "WORD PTR";
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case X86II::Mem32: return "DWORD PTR";
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case X86II::Mem64: return "QWORD PTR";
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case X86II::Mem80: return "XWORD PTR";
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}
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}
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void X86AsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op) {
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void X86AsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op) {
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assert(isMem(MI, Op) && "Invalid memory reference!");
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assert(isMem(MI, Op) && "Invalid memory reference!");
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@ -619,289 +608,12 @@ void X86AsmPrinter::printMachineInstruction(const MachineInstr *MI) {
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O << "\t# ";
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O << "\t# ";
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}
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}
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if (printInstruction(MI))
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// Call the autogenerated instruction printer routines.
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return; // Printer was automatically generated
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bool Handled = printInstruction(MI);
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if (!Handled) {
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MI->dump();
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MI->dump();
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abort();
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assert(0 && "Do not know how to print this instruction!");
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abort();
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unsigned Opcode = MI->getOpcode();
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const TargetInstrInfo &TII = *TM.getInstrInfo();
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const TargetInstrDescriptor &Desc = TII.get(Opcode);
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switch (Desc.TSFlags & X86II::FormMask) {
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case X86II::Pseudo:
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// Print pseudo-instructions as comments; either they should have been
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// turned into real instructions by now, or they don't need to be
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// seen by the assembler (e.g., IMPLICIT_USEs.)
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O << "# ";
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if (Opcode == X86::PHI) {
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printOp(MI->getOperand(0));
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O << " = phi ";
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for (unsigned i = 1, e = MI->getNumOperands(); i != e; i+=2) {
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if (i != 1) O << ", ";
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O << "[";
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printOp(MI->getOperand(i));
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O << ", ";
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printOp(MI->getOperand(i+1));
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O << "]";
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}
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} else {
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unsigned i = 0;
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if (MI->getNumOperands() && MI->getOperand(0).isDef()) {
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printOp(MI->getOperand(0));
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O << " = ";
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++i;
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}
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O << TII.getName(MI->getOpcode());
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for (unsigned e = MI->getNumOperands(); i != e; ++i) {
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O << " ";
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if (MI->getOperand(i).isDef()) O << "*";
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printOp(MI->getOperand(i));
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if (MI->getOperand(i).isDef()) O << "*";
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}
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}
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O << "\n";
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return;
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case X86II::RawFrm:
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{
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// The accepted forms of Raw instructions are:
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// 1. jmp foo - MachineBasicBlock operand
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// 2. call bar - GlobalAddress Operand or External Symbol Operand
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// 3. in AL, imm - Immediate operand
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//
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assert(MI->getNumOperands() == 1 &&
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(MI->getOperand(0).isMachineBasicBlock() ||
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MI->getOperand(0).isGlobalAddress() ||
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MI->getOperand(0).isExternalSymbol() ||
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MI->getOperand(0).isImmediate()) &&
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"Illegal raw instruction!");
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O << TII.getName(MI->getOpcode()) << " ";
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bool LeadingComma = false;
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if (MI->getNumOperands() == 1) {
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printOp(MI->getOperand(0), true); // Don't print "OFFSET"...
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LeadingComma = true;
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}
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printImplUsesAfter(Desc, LeadingComma);
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O << "\n";
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return;
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}
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case X86II::AddRegFrm: {
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// There are currently two forms of acceptable AddRegFrm instructions.
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// Either the instruction JUST takes a single register (like inc, dec, etc),
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// or it takes a register and an immediate of the same size as the register
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// (move immediate f.e.). Note that this immediate value might be stored as
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// an LLVM value, to represent, for example, loading the address of a global
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// into a register. The initial register might be duplicated if this is a
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// M_2_ADDR_REG instruction
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//
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assert(MI->getOperand(0).isRegister() &&
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(MI->getNumOperands() == 1 ||
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(MI->getNumOperands() == 2 &&
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(MI->getOperand(1).getVRegValueOrNull() ||
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MI->getOperand(1).isImmediate() ||
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MI->getOperand(1).isRegister() ||
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MI->getOperand(1).isGlobalAddress() ||
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MI->getOperand(1).isExternalSymbol()))) &&
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"Illegal form for AddRegFrm instruction!");
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unsigned Reg = MI->getOperand(0).getReg();
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O << TII.getName(MI->getOpcode()) << " ";
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printOp(MI->getOperand(0));
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if (MI->getNumOperands() == 2 &&
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(!MI->getOperand(1).isRegister() ||
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MI->getOperand(1).getVRegValueOrNull() ||
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MI->getOperand(1).isGlobalAddress() ||
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MI->getOperand(1).isExternalSymbol())) {
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O << ", ";
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printOp(MI->getOperand(1));
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}
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printImplUsesAfter(Desc);
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O << "\n";
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return;
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}
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case X86II::MRMDestReg: {
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// There are three forms of MRMDestReg instructions, those with 2
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// or 3 operands:
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//
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// 2 Operands: this is for things like mov that do not read a
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// second input.
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//
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// 2 Operands: two address instructions which def&use the first
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// argument and use the second as input.
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//
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// 3 Operands: in this form, two address instructions are the same
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// as in 2 but have a constant argument as well.
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//
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bool isTwoAddr = TII.isTwoAddrInstr(Opcode);
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assert(MI->getOperand(0).isRegister() &&
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(MI->getNumOperands() == 2 ||
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(MI->getNumOperands() == 3 && MI->getOperand(2).isImmediate()))
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&& "Bad format for MRMDestReg!");
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O << TII.getName(MI->getOpcode()) << " ";
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printOp(MI->getOperand(0));
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O << ", ";
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printOp(MI->getOperand(1));
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if (MI->getNumOperands() == 3) {
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O << ", ";
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printOp(MI->getOperand(2));
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}
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printImplUsesAfter(Desc);
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O << "\n";
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return;
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}
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case X86II::MRMDestMem: {
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// These instructions are the same as MRMDestReg, but instead of having a
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// register reference for the mod/rm field, it's a memory reference.
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//
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assert(isMem(MI, 0) &&
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(MI->getNumOperands() == 4+1 ||
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(MI->getNumOperands() == 4+2 && MI->getOperand(5).isImmediate()))
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&& "Bad format for MRMDestMem!");
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O << TII.getName(MI->getOpcode()) << " " << sizePtr(Desc) << " ";
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printMemReference(MI, 0);
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O << ", ";
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printOp(MI->getOperand(4));
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if (MI->getNumOperands() == 4+2) {
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O << ", ";
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printOp(MI->getOperand(5));
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}
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printImplUsesAfter(Desc);
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O << "\n";
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return;
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}
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case X86II::MRMSrcReg: {
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// There are three forms that are acceptable for MRMSrcReg
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// instructions, those with 2 or 3 operands:
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//
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// 2 Operands: this is for things like mov that do not read a
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// second input.
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//
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// 2 Operands: in this form, the last register is the ModR/M
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// input. The first operand is a def&use. This is for things
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// like: add r32, r/m32
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//
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// 3 Operands: in this form, we can have 'INST R1, R2, imm', which is used
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// for instructions like the IMULrri instructions.
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//
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//
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assert(MI->getOperand(0).isRegister() &&
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MI->getOperand(1).isRegister() &&
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(MI->getNumOperands() == 2 ||
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(MI->getNumOperands() == 3 &&
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(MI->getOperand(2).isImmediate())))
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&& "Bad format for MRMSrcReg!");
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O << TII.getName(MI->getOpcode()) << " ";
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printOp(MI->getOperand(0));
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O << ", ";
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printOp(MI->getOperand(1));
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if (MI->getNumOperands() == 3) {
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O << ", ";
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printOp(MI->getOperand(2));
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}
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O << "\n";
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return;
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}
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case X86II::MRMSrcMem: {
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// These instructions are the same as MRMSrcReg, but instead of having a
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// register reference for the mod/rm field, it's a memory reference.
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//
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assert(MI->getOperand(0).isRegister() &&
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((MI->getNumOperands() == 1+4 && isMem(MI, 1)) ||
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(MI->getNumOperands() == 2+4 && MI->getOperand(5).isImmediate() &&
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isMem(MI, 1)))
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&& "Bad format for MRMSrcMem!");
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O << TII.getName(MI->getOpcode()) << " ";
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printOp(MI->getOperand(0));
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O << ", " << sizePtr(Desc) << " ";
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printMemReference(MI, 1);
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if (MI->getNumOperands() == 2+4) {
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O << ", ";
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printOp(MI->getOperand(5));
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}
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O << "\n";
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return;
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}
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case X86II::MRM0r: case X86II::MRM1r:
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case X86II::MRM2r: case X86II::MRM3r:
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case X86II::MRM4r: case X86II::MRM5r:
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case X86II::MRM6r: case X86II::MRM7r: {
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// In this form, the following are valid formats:
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// 1. sete r
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// 2. cmp reg, immediate
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// 2. shl rdest, rinput <implicit CL or 1>
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// 3. sbb rdest, rinput, immediate [rdest = rinput]
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//
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assert(MI->getNumOperands() > 0 && MI->getNumOperands() < 4 &&
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MI->getOperand(0).isRegister() && "Bad MRMSxR format!");
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assert((MI->getNumOperands() != 2 ||
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MI->getOperand(1).isRegister() || MI->getOperand(1).isImmediate())&&
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"Bad MRMSxR format!");
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assert((MI->getNumOperands() < 3 ||
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(MI->getOperand(1).isRegister() && MI->getOperand(2).isImmediate())) &&
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"Bad MRMSxR format!");
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if (MI->getNumOperands() > 1 && MI->getOperand(1).isRegister() &&
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MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
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O << "**";
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O << TII.getName(MI->getOpcode()) << " ";
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printOp(MI->getOperand(0));
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if (MI->getOperand(MI->getNumOperands()-1).isImmediate()) {
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O << ", ";
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printOp(MI->getOperand(MI->getNumOperands()-1));
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}
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printImplUsesAfter(Desc);
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O << "\n";
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return;
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}
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case X86II::MRM0m: case X86II::MRM1m:
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case X86II::MRM2m: case X86II::MRM3m:
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case X86II::MRM4m: case X86II::MRM5m:
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case X86II::MRM6m: case X86II::MRM7m: {
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// In this form, the following are valid formats:
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// 1. sete [m]
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// 2. cmp [m], immediate
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// 2. shl [m], rinput <implicit CL or 1>
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// 3. sbb [m], immediate
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//
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assert(MI->getNumOperands() >= 4 && MI->getNumOperands() <= 5 &&
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isMem(MI, 0) && "Bad MRMSxM format!");
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assert((MI->getNumOperands() != 5 ||
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(MI->getOperand(4).isImmediate() ||
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MI->getOperand(4).isGlobalAddress())) &&
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"Bad MRMSxM format!");
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const MachineOperand &Op3 = MI->getOperand(3);
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O << TII.getName(MI->getOpcode()) << " ";
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O << sizePtr(Desc) << " ";
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printMemReference(MI, 0);
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if (MI->getNumOperands() == 5) {
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O << ", ";
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printOp(MI->getOperand(4));
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}
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printImplUsesAfter(Desc);
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O << "\n";
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return;
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}
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default:
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O << "\tUNKNOWN FORM:\t\t-"; MI->print(O, &TM); break;
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}
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}
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}
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}
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