forked from OSchip/llvm-project
[NFC][AArch64] Add some ubfx tests with immediates
Shows the regression in D62100 llvm-svn: 361102
This commit is contained in:
Roman Lebedev
parent
98092f37d0
commit
d1be3c446e
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@ -421,6 +421,39 @@ entry:
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store i32 %shr2, i32* %y, align 8
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ret void
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}
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define void @fct12_mask(i32* nocapture %y, i32 %x) nounwind optsize inlinehint ssp {
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; LLC-LABEL: fct12_mask:
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; LLC: // %bb.0: // %entry
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; LLC-NEXT: ldr w8, [x0]
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; LLC-NEXT: and w8, w8, #0x3ffffff8
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; LLC-NEXT: bfxil w8, w1, #16, #3
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; LLC-NEXT: lsr w8, w8, #2
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; LLC-NEXT: str w8, [x0]
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; LLC-NEXT: ret
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; OPT-LABEL: @fct12_mask(
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; OPT-NEXT: entry:
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; OPT-NEXT: [[TMP0:%.*]] = load i32, i32* [[Y:%.*]], align 8
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; OPT-NEXT: [[AND:%.*]] = and i32 [[TMP0]], -8
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; OPT-NEXT: [[SHR:%.*]] = lshr i32 [[X:%.*]], 16
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; OPT-NEXT: [[AND1:%.*]] = and i32 [[SHR]], 7
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; OPT-NEXT: [[OR:%.*]] = or i32 [[AND]], [[AND1]]
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; OPT-NEXT: [[LSHR:%.*]] = lshr i32 [[OR]], 2
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; OPT-NEXT: [[MASK:%.*]] = and i32 [[LSHR]], 268435455
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; OPT-NEXT: store i32 [[MASK]], i32* [[Y]], align 8
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; OPT-NEXT: ret void
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;
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entry:
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; lsr is an alias of ubfm
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%0 = load i32, i32* %y, align 8
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%and = and i32 %0, -8
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%shr = lshr i32 %x, 16
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%and1 = and i32 %shr, 7
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%or = or i32 %and, %and1
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%lshr = lshr i32 %or, 2
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%mask = and i32 %lshr, 268435455
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store i32 %mask, i32* %y, align 8
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ret void
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}
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; Check if we can still catch bfm instruction when we drop some high bits
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; and some low bits
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@ -457,6 +490,39 @@ entry:
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store i64 %shr2, i64* %y, align 8
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ret void
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}
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define void @fct13_mask(i64* nocapture %y, i64 %x) nounwind optsize inlinehint ssp {
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; LLC-LABEL: fct13_mask:
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; LLC: // %bb.0: // %entry
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; LLC-NEXT: ldr x8, [x0]
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; LLC-NEXT: and x8, x8, #0x3ffffffffffffff8
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; LLC-NEXT: bfxil x8, x1, #16, #3
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; LLC-NEXT: lsr x8, x8, #2
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; LLC-NEXT: str x8, [x0]
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; LLC-NEXT: ret
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; OPT-LABEL: @fct13_mask(
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; OPT-NEXT: entry:
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; OPT-NEXT: [[TMP0:%.*]] = load i64, i64* [[Y:%.*]], align 8
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; OPT-NEXT: [[AND:%.*]] = and i64 [[TMP0]], -8
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; OPT-NEXT: [[SHR:%.*]] = lshr i64 [[X:%.*]], 16
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; OPT-NEXT: [[AND1:%.*]] = and i64 [[SHR]], 7
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; OPT-NEXT: [[OR:%.*]] = or i64 [[AND]], [[AND1]]
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; OPT-NEXT: [[LSHR:%.*]] = lshr i64 [[OR]], 2
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; OPT-NEXT: [[MASK:%.*]] = and i64 [[LSHR]], 1152921504606846975
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; OPT-NEXT: store i64 [[MASK]], i64* [[Y]], align 8
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; OPT-NEXT: ret void
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;
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entry:
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; lsr is an alias of ubfm
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%0 = load i64, i64* %y, align 8
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%and = and i64 %0, -8
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%shr = lshr i64 %x, 16
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%and1 = and i64 %shr, 7
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%or = or i64 %and, %and1
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%lshr = lshr i64 %or, 2
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%mask = and i64 %lshr, 1152921504606846975
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store i64 %mask, i64* %y, align 8
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ret void
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}
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; Check if we can still catch bfm instruction when we drop some high bits
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@ -591,6 +657,43 @@ entry:
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store i32 %shr2, i32* %y, align 8
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ret void
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}
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define void @fct16_mask(i32* nocapture %y, i32 %x) nounwind optsize inlinehint ssp {
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; LLC-LABEL: fct16_mask:
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; LLC: // %bb.0: // %entry
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; LLC-NEXT: ldr w8, [x0]
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; LLC-NEXT: mov w9, #33120
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; LLC-NEXT: movk w9, #26, lsl #16
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; LLC-NEXT: and w8, w8, w9
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; LLC-NEXT: bfxil w8, w1, #16, #3
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; LLC-NEXT: lsr w8, w8, #2
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; LLC-NEXT: str w8, [x0]
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; LLC-NEXT: ret
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; OPT-LABEL: @fct16_mask(
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; OPT-NEXT: entry:
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; OPT-NEXT: [[TMP0:%.*]] = load i32, i32* [[Y:%.*]], align 8
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; OPT-NEXT: [[AND:%.*]] = and i32 [[TMP0]], 1737056
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; OPT-NEXT: [[SHR:%.*]] = lshr i32 [[X:%.*]], 16
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; OPT-NEXT: [[AND1:%.*]] = and i32 [[SHR]], 7
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; OPT-NEXT: [[OR:%.*]] = or i32 [[AND]], [[AND1]]
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; OPT-NEXT: [[LSHR:%.*]] = lshr i32 [[OR]], 2
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; OPT-NEXT: [[MASK:%.*]] = and i32 [[LSHR]], 268435455
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; OPT-NEXT: store i32 [[MASK]], i32* [[Y]], align 8
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; OPT-NEXT: ret void
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;
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entry:
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; Create the constant
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; Do the masking
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; lsr is an alias of ubfm
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%0 = load i32, i32* %y, align 8
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%and = and i32 %0, 1737056
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%shr = lshr i32 %x, 16
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%and1 = and i32 %shr, 7
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%or = or i32 %and, %and1
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%lshr = lshr i32 %or, 2
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%mask = and i32 %lshr, 268435455
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store i32 %mask, i32* %y, align 8
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ret void
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}
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; Check if we can still catch bfm instruction when we drop some high bits
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@ -633,6 +736,43 @@ entry:
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store i64 %shr2, i64* %y, align 8
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ret void
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}
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define void @fct17_mask(i64* nocapture %y, i64 %x) nounwind optsize inlinehint ssp {
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; LLC-LABEL: fct17_mask:
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; LLC: // %bb.0: // %entry
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; LLC-NEXT: ldr x8, [x0]
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; LLC-NEXT: mov w9, #33120
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; LLC-NEXT: movk w9, #26, lsl #16
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; LLC-NEXT: and x8, x8, x9
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; LLC-NEXT: bfxil x8, x1, #16, #3
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; LLC-NEXT: lsr x8, x8, #2
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; LLC-NEXT: str x8, [x0]
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; LLC-NEXT: ret
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; OPT-LABEL: @fct17_mask(
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; OPT-NEXT: entry:
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; OPT-NEXT: [[TMP0:%.*]] = load i64, i64* [[Y:%.*]], align 8
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; OPT-NEXT: [[AND:%.*]] = and i64 [[TMP0]], 1737056
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; OPT-NEXT: [[SHR:%.*]] = lshr i64 [[X:%.*]], 16
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; OPT-NEXT: [[AND1:%.*]] = and i64 [[SHR]], 7
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; OPT-NEXT: [[OR:%.*]] = or i64 [[AND]], [[AND1]]
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; OPT-NEXT: [[LSHR:%.*]] = lshr i64 [[OR]], 2
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; OPT-NEXT: [[MASK:%.*]] = and i64 [[LSHR]], 1152921504606846975
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; OPT-NEXT: store i64 [[MASK]], i64* [[Y]], align 8
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; OPT-NEXT: ret void
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;
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entry:
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; Create the constant
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; Do the masking
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; lsr is an alias of ubfm
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%0 = load i64, i64* %y, align 8
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%and = and i64 %0, 1737056
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%shr = lshr i64 %x, 16
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%and1 = and i64 %shr, 7
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%or = or i64 %and, %and1
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%lshr = lshr i64 %or, 2
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%mask = and i64 %lshr, 1152921504606846975
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store i64 %mask, i64* %y, align 8
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ret void
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}
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define i64 @fct18(i32 %xor72) nounwind ssp {
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; LLC-LABEL: fct18:
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@ -660,31 +800,31 @@ define i32 @fct19(i64 %arg1) nounwind readonly ssp {
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; LLC-LABEL: fct19:
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; LLC: // %bb.0: // %entry
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; LLC-NEXT: lsr x8, x0, #48
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; LLC-NEXT: cbz x8, .LBB22_2
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; LLC-NEXT: cbz x8, .LBB26_2
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; LLC-NEXT: // %bb.1: // %if.then
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; LLC-NEXT: adrp x9, first_ones
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; LLC-NEXT: add x9, x9, :lo12:first_ones
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; LLC-NEXT: ldrb w0, [x9, x8]
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; LLC-NEXT: ret
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; LLC-NEXT: .LBB22_2: // %if.end
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; LLC-NEXT: .LBB26_2: // %if.end
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; LLC-NEXT: ubfx x8, x0, #32, #16
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; LLC-NEXT: cbz w8, .LBB22_4
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; LLC-NEXT: cbz w8, .LBB26_4
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; LLC-NEXT: // %bb.3: // %if.then7
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; LLC-NEXT: adrp x9, first_ones
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; LLC-NEXT: add x9, x9, :lo12:first_ones
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; LLC-NEXT: ldrb w8, [x9, x8]
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; LLC-NEXT: add w0, w8, #16 // =16
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; LLC-NEXT: ret
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; LLC-NEXT: .LBB22_4: // %if.end13
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; LLC-NEXT: .LBB26_4: // %if.end13
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; LLC-NEXT: ubfx x8, x0, #16, #16
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; LLC-NEXT: cbz w8, .LBB22_6
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; LLC-NEXT: cbz w8, .LBB26_6
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; LLC-NEXT: // %bb.5: // %if.then17
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; LLC-NEXT: adrp x9, first_ones
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; LLC-NEXT: add x9, x9, :lo12:first_ones
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; LLC-NEXT: ldrb w8, [x9, x8]
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; LLC-NEXT: add w0, w8, #32 // =32
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; LLC-NEXT: ret
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; LLC-NEXT: .LBB22_6:
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; LLC-NEXT: .LBB26_6:
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; LLC-NEXT: mov w0, #64
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; LLC-NEXT: ret
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; OPT-LABEL: @fct19(
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@ -885,14 +1025,14 @@ define i16 @test_ignored_rightbits(i32 %dst, i32 %in) {
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define void @sameOperandBFI(i64 %src, i64 %src2, i16 *%ptr) {
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; LLC-LABEL: sameOperandBFI:
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; LLC: // %bb.0: // %entry
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; LLC-NEXT: cbnz wzr, .LBB26_2
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; LLC-NEXT: cbnz wzr, .LBB30_2
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; LLC-NEXT: // %bb.1: // %if.else
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; LLC-NEXT: lsr x8, x0, #47
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; LLC-NEXT: and w9, w1, #0x3
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; LLC-NEXT: bfi w9, w8, #2, #2
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; LLC-NEXT: bfi w9, w9, #4, #4
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; LLC-NEXT: strh w9, [x2]
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; LLC-NEXT: .LBB26_2: // %end
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; LLC-NEXT: .LBB30_2: // %end
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; LLC-NEXT: ret
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; OPT-LABEL: @sameOperandBFI(
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; OPT-NEXT: entry:
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