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[PowerPC] Skip IEEE 128-bit FP type in FastISel 

Vector types, quadword integers and f128 currently cannot be handled in
FastISel. We did not skip f128 type in lowering arguments, which causes
a crash. This patch will fix it.

Reviewed By: steven.zhang

Differential Revision: https://reviews.llvm.org/D90206
This commit is contained in:
Qiu Chaofan 2020-11-03 11:17:11 +08:00
parent 3204ffeade
commit d14e51806b
2 changed files with 33 additions and 1 deletions
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5
llvm/lib/Target/PowerPC/PPCFastISel.cpp
View File

@ -1626,7 +1626,10 @@ bool PPCFastISel::fastLowerCall(CallLoweringInfo &CLI) {
if (!isTypeLegal(ArgTy, ArgVT) && ArgVT != MVT::i16 && ArgVT != MVT::i8)
return false;
if (ArgVT.isVector())
// FIXME: FastISel cannot handle non-simple types yet, including 128-bit FP
// types, which is passed through vector register. Skip these types and
// fallback to default SelectionDAG based selection.
if (ArgVT.isVector() || ArgVT == MVT::f128)
return false;
unsigned Arg = getRegForValue(ArgValue);

29
llvm/test/CodeGen/PowerPC/f128-passByValue.ll
View File

@ -266,3 +266,32 @@ entry:
store double %conv1, double* %d1, align 8
ret void
}
; Function Attrs: noinline optnone
define signext i32 @noopt_call_crash() #0 {
; CHECK-LABEL: noopt_call_crash:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr r0
; CHECK-NEXT: std r0, 16(r1)
; CHECK-NEXT: stdu r1, -96(r1)
; CHECK-NEXT: .cfi_def_cfa_offset 96
; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: bl in
; CHECK-NEXT: nop
; CHECK-NEXT: bl out
; CHECK-NEXT: nop
; CHECK-NEXT: li r3, 0
; CHECK-NEXT: addi r1, r1, 96
; CHECK-NEXT: ld r0, 16(r1)
; CHECK-NEXT: mtlr r0
; CHECK-NEXT: blr
entry:
%call = call fp128 @in()
call void @out(fp128 %call)
ret i32 0
}
declare void @out(fp128)
declare fp128 @in()
attributes #0 = { noinline optnone }