forked from OSchip/llvm-project
Jim Grosbach
parent
247fd3bf59
commit
d14b70d00b
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@ -41,8 +41,9 @@ typedef llvm::MCDisassembler::DecodeStatus DecodeStatus;
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// Definitions are further down.
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static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst,
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unsigned RegNo, uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
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@ -55,8 +56,10 @@ static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst,
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unsigned RegNo,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
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uint64_t Address, const void *Decoder);
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@ -79,11 +82,13 @@ static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
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static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst,unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeSORegImmOperand(llvm::MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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@ -104,7 +109,7 @@ static DecodeStatus DecodeAddrMode5Operand(llvm::MCInst &Inst, unsigned Val,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
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static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst,unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeVCVTImmOperand(llvm::MCInst &Inst, unsigned Val,
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uint64_t Address, const void *Decoder);
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@ -122,7 +127,7 @@ static DecodeStatus DecodeVLD3DupInstruction(llvm::MCInst &Inst, unsigned Val,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Val,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Val,
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static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst,unsigned Val,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeVSHLMaxInstruction(llvm::MCInst &Inst, unsigned Val,
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uint64_t Address, const void *Decoder);
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@ -214,7 +219,7 @@ static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Val,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
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static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst,unsigned Val,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeThumbBLTargetOperand(llvm::MCInst &Inst, unsigned Val,
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uint64_t Address, const void *Decoder);
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@ -243,7 +248,8 @@ EDInstInfo *ThumbDisassembler::getEDInfo() const {
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DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
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const MemoryObject &Region,
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uint64_t Address,raw_ostream &os) const {
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uint64_t Address,
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raw_ostream &os) const {
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uint8_t bytes[4];
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// We want to read exactly 4 bytes of data.
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@ -419,7 +425,8 @@ void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
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DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
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const MemoryObject &Region,
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uint64_t Address,raw_ostream &os) const {
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uint64_t Address,
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raw_ostream &os) const {
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uint8_t bytes[4];
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// We want to read exactly 2 bytes of data.
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@ -577,8 +584,9 @@ static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
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return Success;
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}
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static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
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uint64_t Address, const void *Decoder) {
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static DecodeStatus
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DecodeGPRnopcRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
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uint64_t Address, const void *Decoder) {
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if (RegNo == 15) return Fail;
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return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
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}
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@ -626,7 +634,7 @@ static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
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return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
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}
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static const unsigned SPRDecoderTable[] = {
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static const unsigned SPRDecoderTable[] = {
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ARM::S0, ARM::S1, ARM::S2, ARM::S3,
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ARM::S4, ARM::S5, ARM::S6, ARM::S7,
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ARM::S8, ARM::S9, ARM::S10, ARM::S11,
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@ -647,7 +655,7 @@ static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
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return Success;
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}
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static const unsigned DPRDecoderTable[] = {
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static const unsigned DPRDecoderTable[] = {
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ARM::D0, ARM::D1, ARM::D2, ARM::D3,
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ARM::D4, ARM::D5, ARM::D6, ARM::D7,
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ARM::D8, ARM::D9, ARM::D10, ARM::D11,
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@ -675,14 +683,15 @@ static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
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return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
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}
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static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
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uint64_t Address, const void *Decoder) {
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static DecodeStatus
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DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
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uint64_t Address, const void *Decoder) {
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if (RegNo > 15)
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return Fail;
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return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
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}
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static const unsigned QPRDecoderTable[] = {
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static const unsigned QPRDecoderTable[] = {
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ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
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ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
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ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
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@ -859,7 +868,7 @@ static DecodeStatus DecodeBitfieldMaskOperand(llvm::MCInst &Inst, unsigned Val,
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// This operand encodes a mask of contiguous zeros between a specified MSB
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// and LSB. To decode it, we create the mask of all bits MSB-and-lower,
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// the mask of all bits LSB-and-lower, and then xor them to create
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// the mask of that's all ones on [msb, lsb]. Finally we not it to
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// the mask of that's all ones on [msb, lsb]. Finally we not it to
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// create the final mask.
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unsigned msb = fieldFromInstruction32(Val, 5, 5);
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unsigned lsb = fieldFromInstruction32(Val, 0, 5);
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@ -984,8 +993,9 @@ static DecodeStatus DecodeCopMemInstruction(llvm::MCInst &Inst, unsigned Insn,
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return S;
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}
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static DecodeStatus DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder) {
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static DecodeStatus
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DecodeAddrMode2IdxInstruction(llvm::MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder) {
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DecodeStatus S = Success;
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unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
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@ -1120,8 +1130,9 @@ static DecodeStatus DecodeSORegMemOperand(llvm::MCInst &Inst, unsigned Val,
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return S;
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}
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static DecodeStatus DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder) {
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static DecodeStatus
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DecodeAddrMode3Instruction(llvm::MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder) {
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DecodeStatus S = Success;
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unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
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@ -1392,8 +1403,9 @@ static DecodeStatus DecodeAddrMode7Operand(llvm::MCInst &Inst, unsigned Val,
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return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
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}
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static DecodeStatus DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder) {
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static DecodeStatus
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DecodeBranchImmInstruction(llvm::MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder) {
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DecodeStatus S = Success;
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unsigned pred = fieldFromInstruction32(Insn, 28, 4);
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@ -2053,8 +2065,9 @@ static DecodeStatus DecodeVLD4DupInstruction(llvm::MCInst &Inst, unsigned Insn,
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return S;
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}
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static DecodeStatus DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder) {
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static DecodeStatus
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DecodeNEONModImmInstruction(llvm::MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder) {
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DecodeStatus S = Success;
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unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
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@ -2472,8 +2485,9 @@ static DecodeStatus DecodeCoprocessor(llvm::MCInst &Inst, unsigned Val,
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return Success;
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}
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static DecodeStatus DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder) {
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static DecodeStatus
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DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder) {
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DecodeStatus S = Success;
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unsigned pred = fieldFromInstruction32(Insn, 22, 4);
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@ -2543,8 +2557,9 @@ static DecodeStatus DecodeT2SOImm(llvm::MCInst &Inst, unsigned Val,
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return Success;
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}
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static DecodeStatus DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
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uint64_t Address, const void *Decoder){
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static DecodeStatus
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DecodeThumbBCCTargetOperand(llvm::MCInst &Inst, unsigned Val,
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uint64_t Address, const void *Decoder){
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Inst.addOperand(MCOperand::CreateImm(Val << 1));
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return Success;
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}
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@ -2583,7 +2598,7 @@ static DecodeStatus DecodeMSRMask(llvm::MCInst &Inst, unsigned Val,
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}
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static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder) {
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uint64_t Address, const void *Decoder) {
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DecodeStatus S = Success;
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unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
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@ -2602,7 +2617,7 @@ static DecodeStatus DecodeDoubleRegLoad(llvm::MCInst &Inst, unsigned Insn,
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static DecodeStatus DecodeDoubleRegStore(llvm::MCInst &Inst, unsigned Insn,
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uint64_t Address, const void *Decoder) {
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uint64_t Address, const void *Decoder){
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DecodeStatus S = Success;
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unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
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