forked from OSchip/llvm-project
Make sure the register pressure reduction schedulers work for non-uniform
latency targets, e.g. PPC32. llvm-svn: 28561
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@ -63,8 +63,8 @@ public:
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private:
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void ReleasePred(SUnit *PredSU, bool isChain, unsigned CurCycle);
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void ReleaseSucc(SUnit *SuccSU, bool isChain, unsigned CurCycle);
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void ScheduleNodeBottomUp(SUnit *SU, unsigned& CurCycle);
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void ScheduleNodeTopDown(SUnit *SU, unsigned& CurCycle);
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void ScheduleNodeBottomUp(SUnit *SU, unsigned CurCycle);
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void ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle);
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void ListScheduleTopDown();
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void ListScheduleBottomUp();
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void CommuteNodesToReducePressure();
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@ -78,8 +78,6 @@ void ScheduleDAGRRList::Schedule() {
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// Build scheduling units.
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BuildSchedUnits();
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DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su)
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SUnits[su].dumpAll(&DAG));
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CalculateDepths();
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CalculateHeights();
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@ -217,7 +215,7 @@ void ScheduleDAGRRList::ReleasePred(SUnit *PredSU, bool isChain,
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/// ScheduleNodeBottomUp - Add the node to the schedule. Decrement the pending
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/// count of its predecessors. If a predecessor pending count is zero, add it to
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/// the Available queue.
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void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU, unsigned& CurCycle) {
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void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU, unsigned CurCycle) {
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DEBUG(std::cerr << "*** Scheduling [" << CurCycle << "]: ");
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DEBUG(SU->dump(&DAG));
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SU->Cycle = CurCycle;
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@ -230,7 +228,6 @@ void ScheduleDAGRRList::ScheduleNodeBottomUp(SUnit *SU, unsigned& CurCycle) {
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E = SU->Preds.end(); I != E; ++I)
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ReleasePred(I->first, I->second, CurCycle);
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SU->isScheduled = true;
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CurCycle++;
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}
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/// isReady - True if node's lower cycle bound is less or equal to the current
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@ -252,7 +249,7 @@ void ScheduleDAGRRList::ListScheduleBottomUp() {
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SUnit *CurNode = NULL;
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while (!AvailableQueue->empty()) {
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SUnit *CurNode = AvailableQueue->pop();
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while (!isReady(CurNode, CurCycle)) {
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while (CurNode && !isReady(CurNode, CurCycle)) {
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NotReady.push_back(CurNode);
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CurNode = AvailableQueue->pop();
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}
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@ -261,7 +258,9 @@ void ScheduleDAGRRList::ListScheduleBottomUp() {
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AvailableQueue->push_all(NotReady);
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NotReady.clear();
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ScheduleNodeBottomUp(CurNode, CurCycle);
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if (CurNode != NULL)
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ScheduleNodeBottomUp(CurNode, CurCycle);
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CurCycle++;
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}
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// Add entry node last
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@ -328,7 +327,7 @@ void ScheduleDAGRRList::ReleaseSucc(SUnit *SuccSU, bool isChain,
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/// ScheduleNodeTopDown - Add the node to the schedule. Decrement the pending
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/// count of its successors. If a successor pending count is zero, add it to
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/// the Available queue.
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void ScheduleDAGRRList::ScheduleNodeTopDown(SUnit *SU, unsigned& CurCycle) {
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void ScheduleDAGRRList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) {
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DEBUG(std::cerr << "*** Scheduling [" << CurCycle << "]: ");
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DEBUG(SU->dump(&DAG));
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SU->Cycle = CurCycle;
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@ -341,7 +340,6 @@ void ScheduleDAGRRList::ScheduleNodeTopDown(SUnit *SU, unsigned& CurCycle) {
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E = SU->Succs.end(); I != E; ++I)
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ReleaseSucc(I->first, I->second, CurCycle);
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SU->isScheduled = true;
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CurCycle++;
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}
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void ScheduleDAGRRList::ListScheduleTopDown() {
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@ -359,6 +357,7 @@ void ScheduleDAGRRList::ListScheduleTopDown() {
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// Emit the entry node first.
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ScheduleNodeTopDown(Entry, CurCycle);
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CurCycle++;
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// While Available queue is not empty, grab the node with the highest
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// priority. If it is not ready put it back. Schedule the node.
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@ -366,7 +365,7 @@ void ScheduleDAGRRList::ListScheduleTopDown() {
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SUnit *CurNode = NULL;
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while (!AvailableQueue->empty()) {
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SUnit *CurNode = AvailableQueue->pop();
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while (!isReady(CurNode, CurCycle)) {
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while (CurNode && !isReady(CurNode, CurCycle)) {
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NotReady.push_back(CurNode);
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CurNode = AvailableQueue->pop();
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}
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@ -375,7 +374,9 @@ void ScheduleDAGRRList::ListScheduleTopDown() {
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AvailableQueue->push_all(NotReady);
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NotReady.clear();
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ScheduleNodeTopDown(CurNode, CurCycle);
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if (CurNode != NULL)
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ScheduleNodeTopDown(CurNode, CurCycle);
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CurCycle++;
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}
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@ -453,6 +454,7 @@ namespace {
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}
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SUnit *pop() {
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if (empty()) return NULL;
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SUnit *V = Queue.top();
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Queue.pop();
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return V;
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