Revert r331466: [OPENMP] Fix test typos: CHECK-DAG-N -> CHECK-N-DAG"

Sorry, forgot to add commit log attributes.

llvm-svn: 331468
This commit is contained in:
Joel E. Denny 2018-05-03 17:22:01 +00:00
parent a0f095ebd7
commit d110fe4a7e
8 changed files with 72 additions and 72 deletions

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@ -216,8 +216,8 @@ int main() {
// CHECK: store i{{[0-9]+}} {{.+}}, i{{[0-9]+}}* [[SIVAR_ADDR]],
// T_VAR and SIVAR
// CHECK-64-DAG: [[CONV_TVAR:%.+]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK-64-DAG: [[CONV_SIVAR:%.+]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK-DAG-64: [[CONV_TVAR:%.+]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK-DAG-64: [[CONV_SIVAR:%.+]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// preparation vars
// CHECK-DAG: [[VEC_ADDR_VAL:%.+]] = load [2 x i{{[0-9]+}}]*, [2 x i{{[0-9]+}}]** [[VEC_ADDR]],
@ -247,13 +247,13 @@ int main() {
// CHECK-DAG: call void @{{.+}}({{.+}} [[AGG_TMP2]])
// CHECK: call void @__kmpc_for_static_init_4(
// CHECK-32-DAG: {{.+}} = {{.+}} [[T_VAR_ADDR]]
// CHECK-64-DAG: {{.+}} = {{.+}} [[CONV_TVAR]]
// CHECK-DAG-32: {{.+}} = {{.+}} [[T_VAR_ADDR]]
// CHECK-DAG-64: {{.+}} = {{.+}} [[CONV_TVAR]]
// CHECK-DAG: {{.+}} = {{.+}} [[VEC_PRIV]]
// CHECK-DAG: {{.+}} = {{.+}} [[S_ARR_PRIV]]
// CHECK-DAG: {{.+}} = {{.+}} [[VAR_PRIV]]
// CHECK-32-DAG: {{.+}} = {{.+}} [[SIVAR_ADDR]]
// CHECK-64-DAG: {{.+}} = {{.+}} [[CONV_SIVAR]]
// CHECK-DAG-32: {{.+}} = {{.+}} [[SIVAR_ADDR]]
// CHECK-DAG-64: {{.+}} = {{.+}} [[CONV_SIVAR]]
// CHECK: call void @__kmpc_for_static_fini(
// CHECK: ret void
@ -335,8 +335,8 @@ int main() {
// CHECK-DAG: store [[S_INT_TY]]* [[VAR_PRIV]], [[S_INT_TY]]** [[TMP]],
// CHECK: call void @__kmpc_for_static_init_4(
// CHECK-32-DAG: {{.+}} = {{.+}} [[T_VAR_ADDR]]
// CHECK-64-DAG: {{.+}} = {{.+}} [[CONV_TVAR]]
// CHECK-DAG-32: {{.+}} = {{.+}} [[T_VAR_ADDR]]
// CHECK-DAG-64: {{.+}} = {{.+}} [[CONV_TVAR]]
// CHECK-DAG: {{.+}} = {{.+}} [[VEC_PRIV]]
// CHECK-DAG: {{.+}} = {{.+}} [[TMP]]
// CHECK-DAG: {{.+}} = {{.+}} [[S_ARR_PRIV]]

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@ -266,8 +266,8 @@ int main() {
// CHECK: store i{{[0-9]+}} {{.+}}, i{{[0-9]+}}* [[SIVAR_ADDR]],
// T_VAR and SIVAR
// CHECK-64-DAG: [[CONV_TVAR:%.+]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK-64-DAG: [[CONV_SIVAR:%.+]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK-DAG-64: [[CONV_TVAR:%.+]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK-DAG-64: [[CONV_SIVAR:%.+]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// preparation vars
// CHECK-DAG: [[VEC_ADDR_VAL:%.+]] = load [2 x i{{[0-9]+}}]*, [2 x i{{[0-9]+}}]** [[VEC_ADDR]],
@ -332,8 +332,8 @@ int main() {
// CHECK: store i{{[0-9]+}} {{.+}}, i{{[0-9]+}}* [[SIVAR_ADDR]],
// T_VAR and SIVAR
// CHECK-64-DAG: [[CONV_TVAR:%.+]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK-64-DAG: [[CONV_SIVAR:%.+]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK-DAG-64: [[CONV_TVAR:%.+]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK-DAG-64: [[CONV_SIVAR:%.+]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// preparation vars
// CHECK-DAG: [[VEC_ADDR_VAL:%.+]] = load [2 x i{{[0-9]+}}]*, [2 x i{{[0-9]+}}]** [[VEC_ADDR]],
@ -363,13 +363,13 @@ int main() {
// CHECK-DAG: call void @{{.+}}({{.+}} [[AGG_TMP2]])
// CHECK: call void @__kmpc_for_static_init_4(
// CHECK-32-DAG: {{.+}} = {{.+}} [[T_VAR_ADDR]]
// CHECK-64-DAG: {{.+}} = {{.+}} [[CONV_TVAR]]
// CHECK-DAG-32: {{.+}} = {{.+}} [[T_VAR_ADDR]]
// CHECK-DAG-64: {{.+}} = {{.+}} [[CONV_TVAR]]
// CHECK-DAG: {{.+}} = {{.+}} [[VEC_PRIV]]
// CHECK-DAG: {{.+}} = {{.+}} [[S_ARR_PRIV]]
// CHECK-DAG: {{.+}} = {{.+}} [[VAR_PRIV]]
// CHECK-32-DAG: {{.+}} = {{.+}} [[SIVAR_ADDR]]
// CHECK-64-DAG: {{.+}} = {{.+}} [[CONV_SIVAR]]
// CHECK-DAG-32: {{.+}} = {{.+}} [[SIVAR_ADDR]]
// CHECK-DAG-64: {{.+}} = {{.+}} [[CONV_SIVAR]]
// CHECK: call void @__kmpc_for_static_fini(
// CHECK: ret void
@ -512,8 +512,8 @@ int main() {
// CHECK-DAG: store [[S_INT_TY]]* [[VAR_PRIV]], [[S_INT_TY]]** [[TMP]],
// CHECK: call void @__kmpc_for_static_init_4(
// CHECK-32-DAG: {{.+}} = {{.+}} [[T_VAR_ADDR]]
// CHECK-64-DAG: {{.+}} = {{.+}} [[CONV_TVAR]]
// CHECK-DAG-32: {{.+}} = {{.+}} [[T_VAR_ADDR]]
// CHECK-DAG-64: {{.+}} = {{.+}} [[CONV_TVAR]]
// CHECK-DAG: {{.+}} = {{.+}} [[VEC_PRIV]]
// CHECK-DAG: {{.+}} = {{.+}} [[TMP]]
// CHECK-DAG: {{.+}} = {{.+}} [[S_ARR_PRIV]]

View File

@ -266,8 +266,8 @@ int main() {
// CHECK: store i{{[0-9]+}} {{.+}}, i{{[0-9]+}}* [[SIVAR_ADDR]],
// T_VAR and SIVAR
// CHECK-64-DAG: [[CONV_TVAR:%.+]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK-64-DAG: [[CONV_SIVAR:%.+]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK-DAG-64: [[CONV_TVAR:%.+]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK-DAG-64: [[CONV_SIVAR:%.+]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// preparation vars
// CHECK-DAG: [[VEC_ADDR_VAL:%.+]] = load [2 x i{{[0-9]+}}]*, [2 x i{{[0-9]+}}]** [[VEC_ADDR]],
@ -332,8 +332,8 @@ int main() {
// CHECK: store i{{[0-9]+}} {{.+}}, i{{[0-9]+}}* [[SIVAR_ADDR]],
// T_VAR and SIVAR
// CHECK-64-DAG: [[CONV_TVAR:%.+]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK-64-DAG: [[CONV_SIVAR:%.+]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK-DAG-64: [[CONV_TVAR:%.+]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK-DAG-64: [[CONV_SIVAR:%.+]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// preparation vars
// CHECK-DAG: [[VEC_ADDR_VAL:%.+]] = load [2 x i{{[0-9]+}}]*, [2 x i{{[0-9]+}}]** [[VEC_ADDR]],
@ -363,13 +363,13 @@ int main() {
// CHECK-DAG: call void @{{.+}}({{.+}} [[AGG_TMP2]])
// CHECK: call void @__kmpc_for_static_init_4(
// CHECK-32-DAG: {{.+}} = {{.+}} [[T_VAR_ADDR]]
// CHECK-64-DAG: {{.+}} = {{.+}} [[CONV_TVAR]]
// CHECK-DAG-32: {{.+}} = {{.+}} [[T_VAR_ADDR]]
// CHECK-DAG-64: {{.+}} = {{.+}} [[CONV_TVAR]]
// CHECK-DAG: {{.+}} = {{.+}} [[VEC_PRIV]]
// CHECK-DAG: {{.+}} = {{.+}} [[S_ARR_PRIV]]
// CHECK-DAG: {{.+}} = {{.+}} [[VAR_PRIV]]
// CHECK-32-DAG: {{.+}} = {{.+}} [[SIVAR_ADDR]]
// CHECK-64-DAG: {{.+}} = {{.+}} [[CONV_SIVAR]]
// CHECK-DAG-32: {{.+}} = {{.+}} [[SIVAR_ADDR]]
// CHECK-DAG-64: {{.+}} = {{.+}} [[CONV_SIVAR]]
// CHECK: call void @__kmpc_for_static_fini(
// CHECK: ret void
@ -512,8 +512,8 @@ int main() {
// CHECK-DAG: store [[S_INT_TY]]* [[VAR_PRIV]], [[S_INT_TY]]** [[TMP]],
// CHECK: call void @__kmpc_for_static_init_4(
// CHECK-32-DAG: {{.+}} = {{.+}} [[T_VAR_ADDR]]
// CHECK-64-DAG: {{.+}} = {{.+}} [[CONV_TVAR]]
// CHECK-DAG-32: {{.+}} = {{.+}} [[T_VAR_ADDR]]
// CHECK-DAG-64: {{.+}} = {{.+}} [[CONV_TVAR]]
// CHECK-DAG: {{.+}} = {{.+}} [[VEC_PRIV]]
// CHECK-DAG: {{.+}} = {{.+}} [[TMP]]
// CHECK-DAG: {{.+}} = {{.+}} [[S_ARR_PRIV]]

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@ -216,8 +216,8 @@ int main() {
// CHECK: store i{{[0-9]+}} {{.+}}, i{{[0-9]+}}* [[SIVAR_ADDR]],
// T_VAR and SIVAR
// CHECK-64-DAG: [[CONV_TVAR:%.+]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK-64-DAG: [[CONV_SIVAR:%.+]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK-DAG-64: [[CONV_TVAR:%.+]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK-DAG-64: [[CONV_SIVAR:%.+]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// preparation vars
// CHECK-DAG: [[VEC_ADDR_VAL:%.+]] = load [2 x i{{[0-9]+}}]*, [2 x i{{[0-9]+}}]** [[VEC_ADDR]],
@ -247,13 +247,13 @@ int main() {
// CHECK-DAG: call void @{{.+}}({{.+}} [[AGG_TMP2]])
// CHECK: call void @__kmpc_for_static_init_4(
// CHECK-32-DAG: {{.+}} = {{.+}} [[T_VAR_ADDR]]
// CHECK-64-DAG: {{.+}} = {{.+}} [[CONV_TVAR]]
// CHECK-DAG-32: {{.+}} = {{.+}} [[T_VAR_ADDR]]
// CHECK-DAG-64: {{.+}} = {{.+}} [[CONV_TVAR]]
// CHECK-DAG: {{.+}} = {{.+}} [[VEC_PRIV]]
// CHECK-DAG: {{.+}} = {{.+}} [[S_ARR_PRIV]]
// CHECK-DAG: {{.+}} = {{.+}} [[VAR_PRIV]]
// CHECK-32-DAG: {{.+}} = {{.+}} [[SIVAR_ADDR]]
// CHECK-64-DAG: {{.+}} = {{.+}} [[CONV_SIVAR]]
// CHECK-DAG-32: {{.+}} = {{.+}} [[SIVAR_ADDR]]
// CHECK-DAG-64: {{.+}} = {{.+}} [[CONV_SIVAR]]
// CHECK: call void @__kmpc_for_static_fini(
// CHECK: ret void
@ -335,8 +335,8 @@ int main() {
// CHECK-DAG: store [[S_INT_TY]]* [[VAR_PRIV]], [[S_INT_TY]]** [[TMP]],
// CHECK: call void @__kmpc_for_static_init_4(
// CHECK-32-DAG: {{.+}} = {{.+}} [[T_VAR_ADDR]]
// CHECK-64-DAG: {{.+}} = {{.+}} [[CONV_TVAR]]
// CHECK-DAG-32: {{.+}} = {{.+}} [[T_VAR_ADDR]]
// CHECK-DAG-64: {{.+}} = {{.+}} [[CONV_TVAR]]
// CHECK-DAG: {{.+}} = {{.+}} [[VEC_PRIV]]
// CHECK-DAG: {{.+}} = {{.+}} [[TMP]]
// CHECK-DAG: {{.+}} = {{.+}} [[S_ARR_PRIV]]

View File

@ -219,8 +219,8 @@ int main() {
// CHECK: store i{{[0-9]+}} {{.+}}, i{{[0-9]+}}* [[SIVAR_ADDR]],
// T_VAR and SIVAR
// CHECK-64-DAG: [[CONV_TVAR:%.+]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK-64-DAG: [[CONV_SIVAR:%.+]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK-DAG-64: [[CONV_TVAR:%.+]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK-DAG-64: [[CONV_SIVAR:%.+]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// preparation vars
// CHECK-DAG: [[VEC_ADDR_VAL:%.+]] = load [2 x i{{[0-9]+}}]*, [2 x i{{[0-9]+}}]** [[VEC_ADDR]],
@ -250,13 +250,13 @@ int main() {
// CHECK-DAG: call void @{{.+}}({{.+}} [[AGG_TMP2]])
// CHECK: call void @__kmpc_for_static_init_4(
// CHECK-32-DAG: {{.+}} = {{.+}} [[T_VAR_ADDR]]
// CHECK-64-DAG: {{.+}} = {{.+}} [[CONV_TVAR]]
// CHECK-DAG-32: {{.+}} = {{.+}} [[T_VAR_ADDR]]
// CHECK-DAG-64: {{.+}} = {{.+}} [[CONV_TVAR]]
// CHECK-DAG: {{.+}} = {{.+}} [[VEC_PRIV]]
// CHECK-DAG: {{.+}} = {{.+}} [[S_ARR_PRIV]]
// CHECK-DAG: {{.+}} = {{.+}} [[VAR_PRIV]]
// CHECK-32-DAG: {{.+}} = {{.+}} [[SIVAR_ADDR]]
// CHECK-64-DAG: {{.+}} = {{.+}} [[CONV_SIVAR]]
// CHECK-DAG-32: {{.+}} = {{.+}} [[SIVAR_ADDR]]
// CHECK-DAG-64: {{.+}} = {{.+}} [[CONV_SIVAR]]
// CHECK: call void @__kmpc_for_static_fini(
// CHECK: ret void
@ -338,8 +338,8 @@ int main() {
// CHECK-DAG: store [[S_INT_TY]]* [[VAR_PRIV]], [[S_INT_TY]]** [[TMP]],
// CHECK: call void @__kmpc_for_static_init_4(
// CHECK-32-DAG: {{.+}} = {{.+}} [[T_VAR_ADDR]]
// CHECK-64-DAG: {{.+}} = {{.+}} [[CONV_TVAR]]
// CHECK-DAG-32: {{.+}} = {{.+}} [[T_VAR_ADDR]]
// CHECK-DAG-64: {{.+}} = {{.+}} [[CONV_TVAR]]
// CHECK-DAG: {{.+}} = {{.+}} [[VEC_PRIV]]
// CHECK-DAG: {{.+}} = {{.+}} [[TMP]]
// CHECK-DAG: {{.+}} = {{.+}} [[S_ARR_PRIV]]

View File

@ -243,8 +243,8 @@ int main() {
// CHECK: store i{{[0-9]+}} {{.+}}, i{{[0-9]+}}* [[SIVAR_ADDR]],
// T_VAR and SIVAR
// CHECK-64-DAG: [[CONV_TVAR:%.+]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK-64-DAG: [[CONV_SIVAR:%.+]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK-DAG-64: [[CONV_TVAR:%.+]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK-DAG-64: [[CONV_SIVAR:%.+]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// preparation vars
// CHECK-DAG: [[VEC_ADDR_VAL:%.+]] = load [2 x i{{[0-9]+}}]*, [2 x i{{[0-9]+}}]** [[VEC_ADDR]],
@ -309,8 +309,8 @@ int main() {
// CHECK: store i{{[0-9]+}} {{.+}}, i{{[0-9]+}}* [[SIVAR_ADDR]],
// T_VAR and SIVAR
// CHECK-64-DAG: [[CONV_TVAR:%.+]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK-64-DAG: [[CONV_SIVAR:%.+]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK-DAG-64: [[CONV_TVAR:%.+]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK-DAG-64: [[CONV_SIVAR:%.+]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// preparation vars
// CHECK-DAG: [[VEC_ADDR_VAL:%.+]] = load [2 x i{{[0-9]+}}]*, [2 x i{{[0-9]+}}]** [[VEC_ADDR]],
@ -340,13 +340,13 @@ int main() {
// CHECK-DAG: call void @{{.+}}({{.+}} [[AGG_TMP2]])
// CHECK: call void @__kmpc_for_static_init_4(
// CHECK-32-DAG: {{.+}} = {{.+}} [[T_VAR_ADDR]]
// CHECK-64-DAG: {{.+}} = {{.+}} [[CONV_TVAR]]
// CHECK-DAG-32: {{.+}} = {{.+}} [[T_VAR_ADDR]]
// CHECK-DAG-64: {{.+}} = {{.+}} [[CONV_TVAR]]
// CHECK-DAG: {{.+}} = {{.+}} [[VEC_PRIV]]
// CHECK-DAG: {{.+}} = {{.+}} [[S_ARR_PRIV]]
// CHECK-DAG: {{.+}} = {{.+}} [[VAR_PRIV]]
// CHECK-32-DAG: {{.+}} = {{.+}} [[SIVAR_ADDR]]
// CHECK-64-DAG: {{.+}} = {{.+}} [[CONV_SIVAR]]
// CHECK-DAG-32: {{.+}} = {{.+}} [[SIVAR_ADDR]]
// CHECK-DAG-64: {{.+}} = {{.+}} [[CONV_SIVAR]]
// CHECK: call void @__kmpc_for_static_fini(
// CHECK: ret void
@ -488,8 +488,8 @@ int main() {
// CHECK-DAG: store [[S_INT_TY]]* [[VAR_PRIV]], [[S_INT_TY]]** [[TMP]],
// CHECK: call void @__kmpc_for_static_init_4(
// CHECK-32-DAG: {{.+}} = {{.+}} [[T_VAR_ADDR]]
// CHECK-64-DAG: {{.+}} = {{.+}} [[CONV_TVAR]]
// CHECK-DAG-32: {{.+}} = {{.+}} [[T_VAR_ADDR]]
// CHECK-DAG-64: {{.+}} = {{.+}} [[CONV_TVAR]]
// CHECK-DAG: {{.+}} = {{.+}} [[VEC_PRIV]]
// CHECK-DAG: {{.+}} = {{.+}} [[TMP]]
// CHECK-DAG: {{.+}} = {{.+}} [[S_ARR_PRIV]]

View File

@ -246,8 +246,8 @@ int main() {
// CHECK: store i{{[0-9]+}} {{.+}}, i{{[0-9]+}}* [[SIVAR_ADDR]],
// T_VAR and SIVAR
// CHECK-64-DAG: [[CONV_TVAR:%.+]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK-64-DAG: [[CONV_SIVAR:%.+]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK-DAG-64: [[CONV_TVAR:%.+]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK-DAG-64: [[CONV_SIVAR:%.+]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// preparation vars
// CHECK-DAG: [[VEC_ADDR_VAL:%.+]] = load [2 x i{{[0-9]+}}]*, [2 x i{{[0-9]+}}]** [[VEC_ADDR]],
@ -312,8 +312,8 @@ int main() {
// CHECK: store i{{[0-9]+}} {{.+}}, i{{[0-9]+}}* [[SIVAR_ADDR]],
// T_VAR and SIVAR
// CHECK-64-DAG: [[CONV_TVAR:%.+]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK-64-DAG: [[CONV_SIVAR:%.+]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK-DAG-64: [[CONV_TVAR:%.+]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK-DAG-64: [[CONV_SIVAR:%.+]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// preparation vars
// CHECK-DAG: [[VEC_ADDR_VAL:%.+]] = load [2 x i{{[0-9]+}}]*, [2 x i{{[0-9]+}}]** [[VEC_ADDR]],
@ -343,13 +343,13 @@ int main() {
// CHECK-DAG: call void @{{.+}}({{.+}} [[AGG_TMP2]])
// CHECK: call void @__kmpc_for_static_init_4(
// CHECK-32-DAG: {{.+}} = {{.+}} [[T_VAR_ADDR]]
// CHECK-64-DAG: {{.+}} = {{.+}} [[CONV_TVAR]]
// CHECK-DAG-32: {{.+}} = {{.+}} [[T_VAR_ADDR]]
// CHECK-DAG-64: {{.+}} = {{.+}} [[CONV_TVAR]]
// CHECK-DAG: {{.+}} = {{.+}} [[VEC_PRIV]]
// CHECK-DAG: {{.+}} = {{.+}} [[S_ARR_PRIV]]
// CHECK-DAG: {{.+}} = {{.+}} [[VAR_PRIV]]
// CHECK-32-DAG: {{.+}} = {{.+}} [[SIVAR_ADDR]]
// CHECK-64-DAG: {{.+}} = {{.+}} [[CONV_SIVAR]]
// CHECK-DAG-32: {{.+}} = {{.+}} [[SIVAR_ADDR]]
// CHECK-DAG-64: {{.+}} = {{.+}} [[CONV_SIVAR]]
// CHECK: call void @__kmpc_for_static_fini(
// CHECK: ret void
@ -491,8 +491,8 @@ int main() {
// CHECK-DAG: store [[S_INT_TY]]* [[VAR_PRIV]], [[S_INT_TY]]** [[TMP]],
// CHECK: call void @__kmpc_for_static_init_4(
// CHECK-32-DAG: {{.+}} = {{.+}} [[T_VAR_ADDR]]
// CHECK-64-DAG: {{.+}} = {{.+}} [[CONV_TVAR]]
// CHECK-DAG-32: {{.+}} = {{.+}} [[T_VAR_ADDR]]
// CHECK-DAG-64: {{.+}} = {{.+}} [[CONV_TVAR]]
// CHECK-DAG: {{.+}} = {{.+}} [[VEC_PRIV]]
// CHECK-DAG: {{.+}} = {{.+}} [[TMP]]
// CHECK-DAG: {{.+}} = {{.+}} [[S_ARR_PRIV]]

View File

@ -219,8 +219,8 @@ int main() {
// CHECK: store i{{[0-9]+}} {{.+}}, i{{[0-9]+}}* [[SIVAR_ADDR]],
// T_VAR and SIVAR
// CHECK-64-DAG: [[CONV_TVAR:%.+]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK-64-DAG: [[CONV_SIVAR:%.+]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// CHECK-DAG-64: [[CONV_TVAR:%.+]] = bitcast i64* [[T_VAR_ADDR]] to i32*
// CHECK-DAG-64: [[CONV_SIVAR:%.+]] = bitcast i64* [[SIVAR_ADDR]] to i32*
// preparation vars
// CHECK-DAG: [[VEC_ADDR_VAL:%.+]] = load [2 x i{{[0-9]+}}]*, [2 x i{{[0-9]+}}]** [[VEC_ADDR]],
@ -250,13 +250,13 @@ int main() {
// CHECK-DAG: call void @{{.+}}({{.+}} [[AGG_TMP2]])
// CHECK: call void @__kmpc_for_static_init_4(
// CHECK-32-DAG: {{.+}} = {{.+}} [[T_VAR_ADDR]]
// CHECK-64-DAG: {{.+}} = {{.+}} [[CONV_TVAR]]
// CHECK-DAG-32: {{.+}} = {{.+}} [[T_VAR_ADDR]]
// CHECK-DAG-64: {{.+}} = {{.+}} [[CONV_TVAR]]
// CHECK-DAG: {{.+}} = {{.+}} [[VEC_PRIV]]
// CHECK-DAG: {{.+}} = {{.+}} [[S_ARR_PRIV]]
// CHECK-DAG: {{.+}} = {{.+}} [[VAR_PRIV]]
// CHECK-32-DAG: {{.+}} = {{.+}} [[SIVAR_ADDR]]
// CHECK-64-DAG: {{.+}} = {{.+}} [[CONV_SIVAR]]
// CHECK-DAG-32: {{.+}} = {{.+}} [[SIVAR_ADDR]]
// CHECK-DAG-64: {{.+}} = {{.+}} [[CONV_SIVAR]]
// CHECK: call void @__kmpc_for_static_fini(
// CHECK: ret void
@ -338,8 +338,8 @@ int main() {
// CHECK-DAG: store [[S_INT_TY]]* [[VAR_PRIV]], [[S_INT_TY]]** [[TMP]],
// CHECK: call void @__kmpc_for_static_init_4(
// CHECK-32-DAG: {{.+}} = {{.+}} [[T_VAR_ADDR]]
// CHECK-64-DAG: {{.+}} = {{.+}} [[CONV_TVAR]]
// CHECK-DAG-32: {{.+}} = {{.+}} [[T_VAR_ADDR]]
// CHECK-DAG-64: {{.+}} = {{.+}} [[CONV_TVAR]]
// CHECK-DAG: {{.+}} = {{.+}} [[VEC_PRIV]]
// CHECK-DAG: {{.+}} = {{.+}} [[TMP]]
// CHECK-DAG: {{.+}} = {{.+}} [[S_ARR_PRIV]]