forked from OSchip/llvm-project
[X86][MMX] Add PR35982 test cases
FEMMS has the same problem as EMMS llvm-svn: 322770
This commit is contained in:
Simon Pilgrim
parent
f4b1c002d1
commit
d109b5e027
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+mmx,+3dnowa -post-RA-scheduler=false | FileCheck %s --check-prefixes=CHECK,NOPOST
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; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+mmx,+3dnowa -post-RA-scheduler=true | FileCheck %s --check-prefixes=CHECK,POST
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define float @PR35982_emms(<1 x i64>) nounwind {
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; NOPOST-LABEL: PR35982_emms:
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; NOPOST: # %bb.0:
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; NOPOST-NEXT: pushl %ebp
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; NOPOST-NEXT: movl %esp, %ebp
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; NOPOST-NEXT: andl $-8, %esp
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; NOPOST-NEXT: subl $16, %esp
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; NOPOST-NEXT: movl 8(%ebp), %eax
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; NOPOST-NEXT: movl 12(%ebp), %ecx
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; NOPOST-NEXT: movl %ecx, {{[0-9]+}}(%esp)
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; NOPOST-NEXT: movl %eax, {{[0-9]+}}(%esp)
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; NOPOST-NEXT: movq {{[0-9]+}}(%esp), %mm0
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; NOPOST-NEXT: punpckhdq %mm0, %mm0 # mm0 = mm0[1,1]
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; NOPOST-NEXT: movd %mm0, %ecx
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; NOPOST-NEXT: emms
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; NOPOST-NEXT: movl %eax, (%esp)
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; NOPOST-NEXT: fildl (%esp)
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; NOPOST-NEXT: movl %ecx, {{[0-9]+}}(%esp)
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; NOPOST-NEXT: fiaddl {{[0-9]+}}(%esp)
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; NOPOST-NEXT: movl %ebp, %esp
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; NOPOST-NEXT: popl %ebp
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; NOPOST-NEXT: retl
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;
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; POST-LABEL: PR35982_emms:
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; POST: # %bb.0:
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; POST-NEXT: pushl %ebp
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; POST-NEXT: movl %esp, %ebp
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; POST-NEXT: andl $-8, %esp
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; POST-NEXT: subl $16, %esp
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; POST-NEXT: movl 8(%ebp), %eax
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; POST-NEXT: movl 12(%ebp), %ecx
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; POST-NEXT: movl %ecx, {{[0-9]+}}(%esp)
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; POST-NEXT: movl %eax, {{[0-9]+}}(%esp)
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; POST-NEXT: movq {{[0-9]+}}(%esp), %mm0
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; POST-NEXT: emms
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; POST-NEXT: movl %eax, (%esp)
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; POST-NEXT: fildl (%esp)
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; POST-NEXT: punpckhdq %mm0, %mm0 # mm0 = mm0[1,1]
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; POST-NEXT: movd %mm0, %ecx
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; POST-NEXT: movl %ecx, {{[0-9]+}}(%esp)
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; POST-NEXT: fiaddl {{[0-9]+}}(%esp)
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; POST-NEXT: movl %ebp, %esp
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; POST-NEXT: popl %ebp
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; POST-NEXT: retl
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%2 = bitcast <1 x i64> %0 to <2 x i32>
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%3 = extractelement <2 x i32> %2, i32 0
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%4 = extractelement <1 x i64> %0, i32 0
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%5 = bitcast i64 %4 to x86_mmx
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%6 = tail call x86_mmx @llvm.x86.mmx.punpckhdq(x86_mmx %5, x86_mmx %5)
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%7 = bitcast x86_mmx %6 to <2 x i32>
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%8 = extractelement <2 x i32> %7, i32 0
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tail call void @llvm.x86.mmx.emms()
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%9 = sitofp i32 %3 to float
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%10 = sitofp i32 %8 to float
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%11 = fadd float %9, %10
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ret float %11
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}
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define float @PR35982_femms(<1 x i64>) nounwind {
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; NOPOST-LABEL: PR35982_femms:
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; NOPOST: # %bb.0:
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; NOPOST-NEXT: pushl %ebp
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; NOPOST-NEXT: movl %esp, %ebp
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; NOPOST-NEXT: andl $-8, %esp
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; NOPOST-NEXT: subl $16, %esp
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; NOPOST-NEXT: movl 8(%ebp), %eax
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; NOPOST-NEXT: movl 12(%ebp), %ecx
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; NOPOST-NEXT: movl %ecx, {{[0-9]+}}(%esp)
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; NOPOST-NEXT: movl %eax, {{[0-9]+}}(%esp)
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; NOPOST-NEXT: movq {{[0-9]+}}(%esp), %mm0
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; NOPOST-NEXT: punpckhdq %mm0, %mm0 # mm0 = mm0[1,1]
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; NOPOST-NEXT: movd %mm0, %ecx
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; NOPOST-NEXT: femms
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; NOPOST-NEXT: movl %eax, (%esp)
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; NOPOST-NEXT: fildl (%esp)
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; NOPOST-NEXT: movl %ecx, {{[0-9]+}}(%esp)
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; NOPOST-NEXT: fiaddl {{[0-9]+}}(%esp)
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; NOPOST-NEXT: movl %ebp, %esp
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; NOPOST-NEXT: popl %ebp
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; NOPOST-NEXT: retl
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;
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; POST-LABEL: PR35982_femms:
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; POST: # %bb.0:
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; POST-NEXT: pushl %ebp
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; POST-NEXT: movl %esp, %ebp
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; POST-NEXT: andl $-8, %esp
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; POST-NEXT: subl $16, %esp
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; POST-NEXT: movl 8(%ebp), %eax
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; POST-NEXT: movl 12(%ebp), %ecx
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; POST-NEXT: movl %ecx, {{[0-9]+}}(%esp)
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; POST-NEXT: movl %eax, {{[0-9]+}}(%esp)
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; POST-NEXT: movq {{[0-9]+}}(%esp), %mm0
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; POST-NEXT: femms
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; POST-NEXT: movl %eax, (%esp)
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; POST-NEXT: fildl (%esp)
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; POST-NEXT: punpckhdq %mm0, %mm0 # mm0 = mm0[1,1]
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; POST-NEXT: movd %mm0, %ecx
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; POST-NEXT: movl %ecx, {{[0-9]+}}(%esp)
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; POST-NEXT: fiaddl {{[0-9]+}}(%esp)
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; POST-NEXT: movl %ebp, %esp
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; POST-NEXT: popl %ebp
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; POST-NEXT: retl
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%2 = bitcast <1 x i64> %0 to <2 x i32>
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%3 = extractelement <2 x i32> %2, i32 0
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%4 = extractelement <1 x i64> %0, i32 0
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%5 = bitcast i64 %4 to x86_mmx
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%6 = tail call x86_mmx @llvm.x86.mmx.punpckhdq(x86_mmx %5, x86_mmx %5)
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%7 = bitcast x86_mmx %6 to <2 x i32>
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%8 = extractelement <2 x i32> %7, i32 0
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tail call void @llvm.x86.mmx.femms()
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%9 = sitofp i32 %3 to float
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%10 = sitofp i32 %8 to float
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%11 = fadd float %9, %10
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ret float %11
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}
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declare x86_mmx @llvm.x86.mmx.punpckhdq(x86_mmx, x86_mmx)
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declare void @llvm.x86.mmx.femms()
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declare void @llvm.x86.mmx.emms()
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