maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity

[X86] Change a SmallVector& argument to SmallVectorImpl&. NFC 

Avoids repeating the size.

llvm-svn: 372302
This commit is contained in:
Craig Topper 2019-09-19 06:27:12 +00:00
parent eff4fd6999
commit d103bb654f
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
llvm/lib/Target/X86/X86ISelLowering.cpp
View File

@ -2493,7 +2493,7 @@ static SDValue lowerMasksToReg(const SDValue &ValArg, const EVT &ValLoc,
/// Breaks v64i1 value into two registers and adds the new node to the DAG /// Breaks v64i1 value into two registers and adds the new node to the DAG
static void Passv64i1ArgInRegs( static void Passv64i1ArgInRegs(
const SDLoc &Dl, SelectionDAG &DAG, SDValue &Arg, const SDLoc &Dl, SelectionDAG &DAG, SDValue &Arg,
SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, CCValAssign &VA, SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass, CCValAssign &VA,
CCValAssign &NextVA, const X86Subtarget &Subtarget) { CCValAssign &NextVA, const X86Subtarget &Subtarget) {
assert(Subtarget.hasBWI() && "Expected AVX512BW target!"); assert(Subtarget.hasBWI() && "Expected AVX512BW target!");
assert(Subtarget.is32Bit() && "Expecting 32 bit target"); assert(Subtarget.is32Bit() && "Expecting 32 bit target");