forked from OSchip/llvm-project
[X86] Change a SmallVector& argument to SmallVectorImpl&. NFC
Avoids repeating the size. llvm-svn: 372302
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@ -2493,7 +2493,7 @@ static SDValue lowerMasksToReg(const SDValue &ValArg, const EVT &ValLoc,
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/// Breaks v64i1 value into two registers and adds the new node to the DAG
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static void Passv64i1ArgInRegs(
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const SDLoc &Dl, SelectionDAG &DAG, SDValue &Arg,
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SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass, CCValAssign &VA,
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SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass, CCValAssign &VA,
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CCValAssign &NextVA, const X86Subtarget &Subtarget) {
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assert(Subtarget.hasBWI() && "Expected AVX512BW target!");
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assert(Subtarget.is32Bit() && "Expecting 32 bit target");
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