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[PowerPC] Enable fast-isel on AIX 64 subtarget 

This patch basically enables fast-isel for AIX 64-bit subtarget
(previously enabled only for ELF 64). The initial motivation is to
introduce branch folding to AIX generated code for correct debug
behavior. I also saw some compiling time improvement in a few LLVM
test-suite benchmarks. (toast, dbms, cjpeg, burg, etc.)

Reviewed By: jsji

Differential Revision: https://reviews.llvm.org/D98844
This commit is contained in:
Qiu Chaofan 2021-09-03 11:33:45 +08:00
parent 34badc409c
commit d0f9553ef5
11 changed files with 239 additions and 125 deletions
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4
llvm/lib/Target/PowerPC/PPCFastISel.cpp
View File

@ -2467,9 +2467,9 @@ namespace llvm {
// Create the fast instruction selector for PowerPC64 ELF.
FastISel *PPC::createFastISel(FunctionLoweringInfo &FuncInfo,
const TargetLibraryInfo *LibInfo) {
// Only available on 64-bit ELF for now.
// Only available on 64-bit for now.
const PPCSubtarget &Subtarget = FuncInfo.MF->getSubtarget<PPCSubtarget>();
if (Subtarget.is64BitELFABI())
if (Subtarget.isPPC64())
return new PPCFastISel(FuncInfo, LibInfo);
return nullptr;
}

19
llvm/test/CodeGen/PowerPC/fast-isel-GEP-coalesce.ll
View File

@ -1,4 +1,5 @@
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=PPC64
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr7 | FileCheck %s --check-prefix=PPC64
%struct.A = type { i32, [2 x [2 x i32]], i8, [3 x [3 x [3 x i32]]] }
%struct.B = type { i32, [2 x [2 x [2 x %struct.A]]] }
@ -9,40 +10,40 @@
define i32* @t1() nounwind {
entry:
; ELF64: t1
; PPC64: t1
%addr = alloca i32*, align 4
store i32* getelementptr inbounds ([2 x [2 x [2 x [2 x [2 x i32]]]]], [2 x [2 x [2 x [2 x [2 x i32]]]]]* @arr, i32 0, i32 1, i32 1, i32 1, i32 1, i32 1), i32** %addr, align 4
; ELF64: addi {{[0-9]+}}, {{[0-9]+}}, 124
; PPC64: addi {{[0-9]+}}, {{[0-9]+}}, 124
%0 = load i32*, i32** %addr, align 4
ret i32* %0
}
define i32* @t2() nounwind {
entry:
; ELF64: t2
; PPC64: t2
%addr = alloca i32*, align 4
store i32* getelementptr inbounds ([3 x [3 x %struct.A]], [3 x [3 x %struct.A]]* @A, i32 0, i32 2, i32 2, i32 3, i32 1, i32 2, i32 2), i32** %addr, align 4
; ELF64: addi {{[0-9]+}}, {{[0-9]+}}, 1148
; PPC64: addi {{[0-9]+}}, {{[0-9]+}}, 1148
%0 = load i32*, i32** %addr, align 4
ret i32* %0
}
define i32* @t3() nounwind {
entry:
; ELF64: t3
; PPC64: t3
%addr = alloca i32*, align 4
store i32* getelementptr inbounds ([3 x [3 x %struct.A]], [3 x [3 x %struct.A]]* @A, i32 0, i32 0, i32 1, i32 1, i32 0, i32 1), i32** %addr, align 4
; ELF64: addi {{[0-9]+}}, {{[0-9]+}}, 140
; PPC64: addi {{[0-9]+}}, {{[0-9]+}}, 140
%0 = load i32*, i32** %addr, align 4
ret i32* %0
}
define i32* @t4() nounwind {
entry:
; ELF64: t4
; PPC64: t4
%addr = alloca i32*, align 4
store i32* getelementptr inbounds ([2 x [2 x [2 x %struct.B]]], [2 x [2 x [2 x %struct.B]]]* @B, i32 0, i32 0, i32 0, i32 1, i32 1, i32 0, i32 0, i32 1, i32 3, i32 1, i32 2, i32 1), i32** %addr, align 4
; ELF64: addi {{[0-9]+}}, {{[0-9]+}}, 1284
; PPC64: addi {{[0-9]+}}, {{[0-9]+}}, 1284
%0 = load i32*, i32** %addr, align 4
ret i32* %0
}

55
llvm/test/CodeGen/PowerPC/fast-isel-binary.ll
View File

@ -1,43 +1,44 @@
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=PPC64
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr7 | FileCheck %s --check-prefix=PPC64
; Test add with non-legal types
define void @add_i8(i8 %a, i8 %b) nounwind {
entry:
; ELF64: add_i8
; PPC64: add_i8
%a.addr = alloca i8, align 4
%0 = add i8 %a, %b
; ELF64: add
; PPC64: add
store i8 %0, i8* %a.addr, align 4
ret void
}
define void @add_i8_imm(i8 %a) nounwind {
entry:
; ELF64: add_i8_imm
; PPC64: add_i8_imm
%a.addr = alloca i8, align 4
%0 = add i8 %a, 22;
; ELF64: addi
; PPC64: addi
store i8 %0, i8* %a.addr, align 4
ret void
}
define void @add_i16(i16 %a, i16 %b) nounwind {
entry:
; ELF64: add_i16
; PPC64: add_i16
%a.addr = alloca i16, align 4
%0 = add i16 %a, %b
; ELF64: add
; PPC64: add
store i16 %0, i16* %a.addr, align 4
ret void
}
define void @add_i16_imm(i16 %a, i16 %b) nounwind {
entry:
; ELF64: add_i16_imm
; PPC64: add_i16_imm
%a.addr = alloca i16, align 4
%0 = add i16 %a, 243;
; ELF64: addi
; PPC64: addi
store i16 %0, i16* %a.addr, align 4
ret void
}
@ -46,40 +47,40 @@ entry:
define void @or_i8(i8 %a, i8 %b) nounwind {
entry:
; ELF64: or_i8
; PPC64: or_i8
%a.addr = alloca i8, align 4
%0 = or i8 %a, %b
; ELF64: or
; PPC64: or
store i8 %0, i8* %a.addr, align 4
ret void
}
define void @or_i8_imm(i8 %a) nounwind {
entry:
; ELF64: or_i8_imm
; PPC64: or_i8_imm
%a.addr = alloca i8, align 4
%0 = or i8 %a, -13;
; ELF64: ori
; PPC64: ori
store i8 %0, i8* %a.addr, align 4
ret void
}
define void @or_i16(i16 %a, i16 %b) nounwind {
entry:
; ELF64: or_i16
; PPC64: or_i16
%a.addr = alloca i16, align 4
%0 = or i16 %a, %b
; ELF64: or
; PPC64: or
store i16 %0, i16* %a.addr, align 4
ret void
}
define void @or_i16_imm(i16 %a) nounwind {
entry:
; ELF64: or_i16_imm
; PPC64: or_i16_imm
%a.addr = alloca i16, align 4
%0 = or i16 %a, 273;
; ELF64: ori
; PPC64: ori
store i16 %0, i16* %a.addr, align 4
ret void
}
@ -88,50 +89,50 @@ entry:
define void @sub_i8(i8 %a, i8 %b) nounwind {
entry:
; ELF64: sub_i8
; PPC64: sub_i8
%a.addr = alloca i8, align 4
%0 = sub i8 %a, %b
; ELF64: sub
; PPC64: sub
store i8 %0, i8* %a.addr, align 4
ret void
}
define void @sub_i8_imm(i8 %a) nounwind {
entry:
; ELF64: sub_i8_imm
; PPC64: sub_i8_imm
%a.addr = alloca i8, align 4
%0 = sub i8 %a, 22;
; ELF64: addi
; PPC64: addi
store i8 %0, i8* %a.addr, align 4
ret void
}
define void @sub_i16(i16 %a, i16 %b) nounwind {
entry:
; ELF64: sub_i16
; PPC64: sub_i16
%a.addr = alloca i16, align 4
%0 = sub i16 %a, %b
; ELF64: sub
; PPC64: sub
store i16 %0, i16* %a.addr, align 4
ret void
}
define void @sub_i16_imm(i16 %a) nounwind {
entry:
; ELF64: sub_i16_imm
; PPC64: sub_i16_imm
%a.addr = alloca i16, align 4
%0 = sub i16 %a, 247;
; ELF64: addi
; PPC64: addi
store i16 %0, i16* %a.addr, align 4
ret void
}
define void @sub_i16_badimm(i16 %a) nounwind {
entry:
; ELF64: sub_i16_imm
; PPC64: sub_i16_imm
%a.addr = alloca i16, align 4
%0 = sub i16 %a, -32768;
; ELF64: sub
; PPC64: sub
store i16 %0, i16* %a.addr, align 4
ret void
}

105
llvm/test/CodeGen/PowerPC/fast-isel-branch.ll Normal file
View File

@ -0,0 +1,105 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu < %s | FileCheck %s -check-prefix=ELF64
; RUN: llc -mtriple=powerpc64-ibm-aix-xcoff < %s | FileCheck %s -check-prefix=AIX64
@x = global i32 1000, align 4
define signext i32 @bar() #0 {
; ELF64-LABEL: bar:
; ELF64: # %bb.0: # %entry
; ELF64-NEXT: mflr 0
; ELF64-NEXT: std 0, 16(1)
; ELF64-NEXT: stdu 1, -48(1)
; ELF64-NEXT: .cfi_def_cfa_offset 48
; ELF64-NEXT: .cfi_offset lr, 16
; ELF64-NEXT: li 3, 0
; ELF64-NEXT: stw 3, 44(1)
; ELF64-NEXT: li 3, 0
; ELF64-NEXT: stw 3, 40(1)
; ELF64-NEXT: .LBB0_1: # %for.cond
; ELF64-NEXT: #
; ELF64-NEXT: lwz 3, 40(1)
; ELF64-NEXT: addis 4, 2, .LC0@toc@ha
; ELF64-NEXT: ld 4, .LC0@toc@l(4)
; ELF64-NEXT: lwz 4, 0(4)
; ELF64-NEXT: cmpw 3, 4
; ELF64-NEXT: bge 0, .LBB0_4
; ELF64-NEXT: # %bb.2: # %for.body
; ELF64-NEXT: #
; ELF64-NEXT: bl foo
; ELF64-NEXT: nop
; ELF64-NEXT: # %bb.3: # %for.inc
; ELF64-NEXT: #
; ELF64-NEXT: lwz 3, 40(1)
; ELF64-NEXT: addi 3, 3, 1
; ELF64-NEXT: stw 3, 40(1)
; ELF64-NEXT: b .LBB0_1
; ELF64-NEXT: .LBB0_4: # %for.end
; ELF64-NEXT: li 3, 0
; ELF64-NEXT: addi 1, 1, 48
; ELF64-NEXT: ld 0, 16(1)
; ELF64-NEXT: mtlr 0
; ELF64-NEXT: blr
;
; AIX64-LABEL: bar:
; AIX64: # %bb.0: # %entry
; AIX64-NEXT: mflr 0
; AIX64-NEXT: std 0, 16(1)
; AIX64-NEXT: stdu 1, -128(1)
; AIX64-NEXT: li 3, 0
; AIX64-NEXT: stw 3, 124(1)
; AIX64-NEXT: li 3, 0
; AIX64-NEXT: stw 3, 120(1)
; AIX64-NEXT: L..BB0_1: # %for.cond
; AIX64-NEXT: #
; AIX64-NEXT: lwz 3, 120(1)
; AIX64-NEXT: ld 4, L..C0(2)
; AIX64-NEXT: lwz 4, 0(4)
; AIX64-NEXT: cmpw 3, 4
; AIX64-NEXT: bge 0, L..BB0_4
; AIX64-NEXT: # %bb.2: # %for.body
; AIX64-NEXT: #
; AIX64-NEXT: bl .foo[PR]
; AIX64-NEXT: nop
; AIX64-NEXT: # %bb.3: # %for.inc
; AIX64-NEXT: #
; AIX64-NEXT: lwz 3, 120(1)
; AIX64-NEXT: addi 3, 3, 1
; AIX64-NEXT: stw 3, 120(1)
; AIX64-NEXT: b L..BB0_1
; AIX64-NEXT: L..BB0_4: # %for.end
; AIX64-NEXT: li 3, 0
; AIX64-NEXT: addi 1, 1, 128
; AIX64-NEXT: ld 0, 16(1)
; AIX64-NEXT: mtlr 0
; AIX64-NEXT: blr
entry:
%retval = alloca i32, align 4
%i = alloca i32, align 4
store i32 0, i32* %retval, align 4
store i32 0, i32* %i, align 4
br label %for.cond
for.cond:
%0 = load i32, i32* %i, align 4
%1 = load i32, i32* @x, align 4
%cmp = icmp slt i32 %0, %1
br i1 %cmp, label %for.body, label %for.end
for.body:
call void bitcast (void (...)* @foo to void ()*)()
br label %for.inc
for.inc:
%2 = load i32, i32* %i, align 4
%inc = add nsw i32 %2, 1
store i32 %inc, i32* %i, align 4
br label %for.cond
for.end:
ret i32 0
}
declare void @foo(...)
attributes #0 = { optnone noinline }

13
llvm/test/CodeGen/PowerPC/fast-isel-const.ll
View File

@ -1,27 +1,28 @@
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=PPC64
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr7 | FileCheck %s --check-prefix=PPC64
define zeroext i1 @testi1(i8 %in) nounwind {
entry:
%c = icmp eq i8 %in, 5
br i1 %c, label %true, label %false
; ELF64-LABEL: @testi1
; PPC64-LABEL: @testi1
true:
br label %end
; ELF64-NOT: li {{[0-9]+}}, -1
; ELF64: li {{[0-9]+}}, 1
; PPC64-NOT: li {{[0-9]+}}, -1
; PPC64: li {{[0-9]+}}, 1
false:
br label %end
; ELF64: li {{[0-9]+}}, 0
; PPC64: li {{[0-9]+}}, 0
end:
%r = phi i1 [ 0, %false], [ 1, %true ]
ret i1 %r
; ELF64: blr
; PPC64: blr
}

1
llvm/test/CodeGen/PowerPC/fast-isel-crash.ll
View File

@ -1,4 +1,5 @@
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr7
; Ensure this doesn't crash.

43
llvm/test/CodeGen/PowerPC/fast-isel-ext.ll
View File

@ -1,75 +1,76 @@
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=PPC64
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr7 | FileCheck %s --check-prefix=PPC64
; zext
define i32 @zext_8_32(i8 %a) nounwind {
; ELF64: zext_8_32
; PPC64: zext_8_32
%r = zext i8 %a to i32
; ELF64: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24
; PPC64: clrlwi {{[0-9]+}}, {{[0-9]+}}, 24
ret i32 %r
}
define i32 @zext_16_32(i16 %a) nounwind {
; ELF64: zext_16_32
; PPC64: zext_16_32
%r = zext i16 %a to i32
; ELF64: clrlwi {{[0-9]+}}, {{[0-9]+}}, 16
; PPC64: clrlwi {{[0-9]+}}, {{[0-9]+}}, 16
ret i32 %r
}
define i64 @zext_8_64(i8 %a) nounwind {
; ELF64: zext_8_64
; PPC64: zext_8_64
%r = zext i8 %a to i64
; ELF64: clrldi {{[0-9]+}}, {{[0-9]+}}, 56
; PPC64: clrldi {{[0-9]+}}, {{[0-9]+}}, 56
ret i64 %r
}
define i64 @zext_16_64(i16 %a) nounwind {
; ELF64: zext_16_64
; PPC64: zext_16_64
%r = zext i16 %a to i64
; ELF64: clrldi {{[0-9]+}}, {{[0-9]+}}, 48
; PPC64: clrldi {{[0-9]+}}, {{[0-9]+}}, 48
ret i64 %r
}
define i64 @zext_32_64(i32 %a) nounwind {
; ELF64: zext_32_64
; PPC64: zext_32_64
%r = zext i32 %a to i64
; ELF64: clrldi {{[0-9]+}}, {{[0-9]+}}, 32
; PPC64: clrldi {{[0-9]+}}, {{[0-9]+}}, 32
ret i64 %r
}
; sext
define i32 @sext_8_32(i8 %a) nounwind {
; ELF64: sext_8_32
; PPC64: sext_8_32
%r = sext i8 %a to i32
; ELF64: extsb
; PPC64: extsb
ret i32 %r
}
define i32 @sext_16_32(i16 %a) nounwind {
; ELF64: sext_16_32
; PPC64: sext_16_32
%r = sext i16 %a to i32
; ELF64: extsh
; PPC64: extsh
ret i32 %r
}
define i64 @sext_8_64(i8 %a) nounwind {
; ELF64: sext_8_64
; PPC64: sext_8_64
%r = sext i8 %a to i64
; ELF64: extsb
; PPC64: extsb
ret i64 %r
}
define i64 @sext_16_64(i16 %a) nounwind {
; ELF64: sext_16_64
; PPC64: sext_16_64
%r = sext i16 %a to i64
; ELF64: extsh
; PPC64: extsh
ret i64 %r
}
define i64 @sext_32_64(i32 %a) nounwind {
; ELF64: sext_32_64
; PPC64: sext_32_64
%r = sext i32 %a to i64
; ELF64: extsw
; PPC64: extsw
ret i64 %r
}

87
llvm/test/CodeGen/PowerPC/fast-isel-fold.ll
View File

@ -1,36 +1,37 @@
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=PPC64
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr7 | FileCheck %s --check-prefix=PPC64
@a = global i8 1, align 1
@b = global i16 2, align 2
@c = global i32 4, align 4
define void @t1() nounwind {
; ELF64: t1
; PPC64: t1
%1 = load i8, i8* @a, align 1
call void @foo1(i8 zeroext %1)
; ELF64: lbz
; ELF64-NOT: rldicl
; ELF64-NOT: rlwinm
; PPC64: lbz
; PPC64-NOT: rldicl
; PPC64-NOT: rlwinm
ret void
}
define void @t2() nounwind {
; ELF64: t2
; PPC64: t2
%1 = load i16, i16* @b, align 2
call void @foo2(i16 zeroext %1)
; ELF64: lhz
; ELF64-NOT: rldicl
; ELF64-NOT: rlwinm
; PPC64: lhz
; PPC64-NOT: rldicl
; PPC64-NOT: rlwinm
ret void
}
define void @t2a() nounwind {
; ELF64: t2a
; PPC64: t2a
%1 = load i32, i32* @c, align 4
call void @foo3(i32 zeroext %1)
; ELF64: lwz
; ELF64-NOT: rldicl
; ELF64-NOT: rlwinm
; PPC64: lwz
; PPC64-NOT: rldicl
; PPC64-NOT: rlwinm
ret void
}
@ -39,91 +40,91 @@ declare void @foo2(i16 zeroext)
declare void @foo3(i32 zeroext)
define i32 @t3() nounwind {
; ELF64: t3
; PPC64: t3
%1 = load i8, i8* @a, align 1
%2 = zext i8 %1 to i32
; ELF64: lbz
; ELF64-NOT: rlwinm
; PPC64: lbz
; PPC64-NOT: rlwinm
ret i32 %2
}
define i32 @t4() nounwind {
; ELF64: t4
; PPC64: t4
%1 = load i16, i16* @b, align 2
%2 = zext i16 %1 to i32
; ELF64: lhz
; ELF64-NOT: rlwinm
; PPC64: lhz
; PPC64-NOT: rlwinm
ret i32 %2
}
define i32 @t5() nounwind {
; ELF64: t5
; PPC64: t5
%1 = load i16, i16* @b, align 2
%2 = sext i16 %1 to i32
; ELF64: lha
; ELF64-NOT: rlwinm
; PPC64: lha
; PPC64-NOT: rlwinm
ret i32 %2
}
define i32 @t6() nounwind {
; ELF64: t6
; PPC64: t6
%1 = load i8, i8* @a, align 2
%2 = sext i8 %1 to i32
; ELF64: lbz
; ELF64-NOT: rlwinm
; PPC64: lbz
; PPC64-NOT: rlwinm
ret i32 %2
}
define i64 @t7() nounwind {
; ELF64: t7
; PPC64: t7
%1 = load i8, i8* @a, align 1
%2 = zext i8 %1 to i64
; ELF64: lbz
; ELF64-NOT: rldicl
; PPC64: lbz
; PPC64-NOT: rldicl
ret i64 %2
}
define i64 @t8() nounwind {
; ELF64: t8
; PPC64: t8
%1 = load i16, i16* @b, align 2
%2 = zext i16 %1 to i64
; ELF64: lhz
; ELF64-NOT: rldicl
; PPC64: lhz
; PPC64-NOT: rldicl
ret i64 %2
}
define i64 @t9() nounwind {
; ELF64: t9
; PPC64: t9
%1 = load i16, i16* @b, align 2
%2 = sext i16 %1 to i64
; ELF64: lha
; ELF64-NOT: extsh
; PPC64: lha
; PPC64-NOT: extsh
ret i64 %2
}
define i64 @t10() nounwind {
; ELF64: t10
; PPC64: t10
%1 = load i8, i8* @a, align 2
%2 = sext i8 %1 to i64
; ELF64: lbz
; ELF64: extsb
; PPC64: lbz
; PPC64: extsb
ret i64 %2
}
define i64 @t11() nounwind {
; ELF64: t11
; PPC64: t11
%1 = load i32, i32* @c, align 4
%2 = zext i32 %1 to i64
; ELF64: lwz
; ELF64-NOT: rldicl
; PPC64: lwz
; PPC64-NOT: rldicl
ret i64 %2
}
define i64 @t12() nounwind {
; ELF64: t12
; PPC64: t12
%1 = load i32, i32* @c, align 4
%2 = sext i32 %1 to i64
; ELF64: lwa
; ELF64-NOT: extsw
; PPC64: lwa
; PPC64-NOT: extsw
ret i64 %2
}

1
llvm/test/CodeGen/PowerPC/fast-isel-i64offset.ll
View File

@ -1,4 +1,5 @@
; RUN: llc -verify-machineinstrs -mtriple powerpc64-unknown-linux-gnu -fast-isel -O0 < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -fast-isel -O0 < %s | FileCheck %s
; Verify that pointer offsets larger than 32 bits work correctly.

9
llvm/test/CodeGen/PowerPC/fast-isel-indirectbr.ll
View File

@ -1,8 +1,9 @@
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=PPC64
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr7 | FileCheck %s --check-prefix=PPC64
define void @t1(i8* %x) nounwind {
entry:
; ELF64: t1
; PPC64: t1
br label %L0
L0:
@ -10,6 +11,6 @@ L0:
L1:
indirectbr i8* %x, [ label %L0, label %L1 ]
; ELF64: mtctr 3
; ELF64: bctr
; PPC64: mtctr 3
; PPC64: bctr
}

27
llvm/test/CodeGen/PowerPC/fast-isel-shifter.ll
View File

@ -1,49 +1,50 @@
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=PPC64
; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort=1 -mtriple=powerpc64-ibm-aix-xcoff -mcpu=pwr7 | FileCheck %s --check-prefix=PPC64
define i32 @shl() nounwind {
entry:
; ELF64: shl
; ELF64: slw
; PPC64: shl
; PPC64: slw
%shl = shl i32 -1, 2
ret i32 %shl
}
define i32 @shl_reg(i32 %src1, i32 %src2) nounwind {
entry:
; ELF64: shl_reg
; ELF64: slw
; PPC64: shl_reg
; PPC64: slw
%shl = shl i32 %src1, %src2
ret i32 %shl
}
define i32 @lshr() nounwind {
entry:
; ELF64: lshr
; ELF64: srw
; PPC64: lshr
; PPC64: srw
%lshr = lshr i32 -1, 2
ret i32 %lshr
}
define i32 @lshr_reg(i32 %src1, i32 %src2) nounwind {
entry:
; ELF64: lshr_reg
; ELF64: srw
; PPC64: lshr_reg
; PPC64: srw
%lshr = lshr i32 %src1, %src2
ret i32 %lshr
}
define i32 @ashr() nounwind {
entry:
; ELF64: ashr
; ELF64: srawi
; PPC64: ashr
; PPC64: srawi
%ashr = ashr i32 -1, 2
ret i32 %ashr
}
define i32 @ashr_reg(i32 %src1, i32 %src2) nounwind {
entry:
; ELF64: ashr_reg
; ELF64: sraw
; PPC64: ashr_reg
; PPC64: sraw
%ashr = ashr i32 %src1, %src2
ret i32 %ashr
}