forked from OSchip/llvm-project
parent
66d130a584
commit
d0e360e16e
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@ -317,7 +317,9 @@ static inline unsigned getLSMultipleTransferSize(MachineInstr *MI) {
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/// =>
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/// ldmdb rn!, <ra, rb, rc>
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static bool mergeBaseUpdateLSMultiple(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI) {
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MachineBasicBlock::iterator MBBI,
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bool &Advance,
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MachineBasicBlock::iterator &I) {
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MachineInstr *MI = MBBI;
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unsigned Base = MI->getOperand(0).getReg();
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unsigned Bytes = getLSMultipleTransferSize(MI);
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@ -358,11 +360,19 @@ static bool mergeBaseUpdateLSMultiple(MachineBasicBlock &MBB,
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if ((Mode == ARM_AM::ia || Mode == ARM_AM::ib) &&
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isMatchingIncrement(NextMBBI, Base, Bytes, Pred, PredReg)) {
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MI->getOperand(1).setImm(ARM_AM::getAM4ModeImm(Mode, true));
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if (NextMBBI == I) {
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Advance = true;
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++I;
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}
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MBB.erase(NextMBBI);
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return true;
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} else if ((Mode == ARM_AM::da || Mode == ARM_AM::db) &&
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isMatchingDecrement(NextMBBI, Base, Bytes, Pred, PredReg)) {
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MI->getOperand(1).setImm(ARM_AM::getAM4ModeImm(Mode, true));
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if (NextMBBI == I) {
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Advance = true;
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++I;
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}
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MBB.erase(NextMBBI);
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return true;
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}
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@ -389,6 +399,10 @@ static bool mergeBaseUpdateLSMultiple(MachineBasicBlock &MBB,
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if (Mode == ARM_AM::ia &&
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isMatchingIncrement(NextMBBI, Base, Bytes, Pred, PredReg)) {
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MI->getOperand(1).setImm(ARM_AM::getAM5Opc(ARM_AM::ia, true, Offset));
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if (NextMBBI == I) {
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Advance = true;
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++I;
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}
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MBB.erase(NextMBBI);
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}
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return true;
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@ -428,7 +442,9 @@ static unsigned getPostIndexedLoadStoreOpcode(unsigned Opc) {
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/// register into the LDR/STR/FLD{D|S}/FST{D|S} op when possible:
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static bool mergeBaseUpdateLoadStore(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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const TargetInstrInfo *TII) {
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const TargetInstrInfo *TII,
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bool &Advance,
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MachineBasicBlock::iterator &I) {
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MachineInstr *MI = MBBI;
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unsigned Base = MI->getOperand(1).getReg();
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bool BaseKill = MI->getOperand(1).isKill();
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@ -475,8 +491,13 @@ static bool mergeBaseUpdateLoadStore(MachineBasicBlock &MBB,
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DoMerge = true;
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NewOpc = getPostIndexedLoadStoreOpcode(Opcode);
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}
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if (DoMerge)
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if (DoMerge) {
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if (NextMBBI == I) {
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Advance = true;
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++I;
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}
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MBB.erase(NextMBBI);
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}
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}
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if (!DoMerge)
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@ -668,7 +689,7 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
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// Try folding preceeding/trailing base inc/dec into the generated
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// LDM/STM ops.
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for (unsigned i = 0, e = MBBII.size(); i < e; ++i)
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if (mergeBaseUpdateLSMultiple(MBB, MBBII[i]))
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if (mergeBaseUpdateLSMultiple(MBB, MBBII[i], Advance, MBBI))
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NumMerges++;
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NumMerges += MBBII.size();
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@ -676,7 +697,7 @@ bool ARMLoadStoreOpt::LoadStoreMultipleOpti(MachineBasicBlock &MBB) {
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// that were not merged to form LDM/STM ops.
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for (unsigned i = 0; i != NumMemOps; ++i)
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if (!MemOps[i].Merged)
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if (mergeBaseUpdateLoadStore(MBB, MemOps[i].MBBI, TII))
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if (mergeBaseUpdateLoadStore(MBB, MemOps[i].MBBI, TII,Advance,MBBI))
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NumMerges++;
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// RS may be pointing to an instruction that's deleted.
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