forked from OSchip/llvm-project
Committing a good chunk of the pre-register allocation live interval splitting pass. It's handling simple cases and appear to do good things. Next: avoid splitting an interval multiple times; renumber registers when possible; record stack slot live intervals for coloring; rematerialize defs when possible.
llvm-svn: 58044
This commit is contained in:
Evan Cheng
parent
e395d78657
commit
d0d0317b9a
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@ -219,6 +219,39 @@ namespace llvm {
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return i2miMap_[index];
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}
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/// hasGapBeforeInstr - Return true if the previous instruction slot,
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/// i.e. Index - InstrSlots::NUM, is not occupied.
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bool hasGapBeforeInstr(unsigned Index) {
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Index = getBaseIndex(Index - InstrSlots::NUM);
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return getInstructionFromIndex(Index) == 0;
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}
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/// findGapBeforeInstr - Find an empty instruction slot before the
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/// specified index. If "Furthest" is true, find one that's furthest
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/// away from the index (but before any index that's occupied).
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unsigned findGapBeforeInstr(unsigned Index, bool Furthest = false) {
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Index = getBaseIndex(Index - InstrSlots::NUM);
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if (getInstructionFromIndex(Index))
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return 0; // No gap!
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if (!Furthest)
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return Index;
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unsigned PrevIndex = getBaseIndex(Index - InstrSlots::NUM);
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while (getInstructionFromIndex(Index)) {
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Index = PrevIndex;
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PrevIndex = getBaseIndex(Index - InstrSlots::NUM);
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}
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return Index;
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}
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/// InsertMachineInstrInMaps - Insert the specified machine instruction
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/// into the instruction index map at the given index.
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void InsertMachineInstrInMaps(MachineInstr *MI, unsigned Index) {
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i2miMap_[Index / InstrSlots::NUM] = MI;
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Mi2IndexMap::iterator it = mi2iMap_.find(MI);
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assert(it == mi2iMap_.end() && "Already in map!");
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mi2iMap_[MI] = Index;
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}
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/// conflictsWithPhysRegDef - Returns true if the specified register
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/// is defined during the duration of the specified interval.
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bool conflictsWithPhysRegDef(const LiveInterval &li, VirtRegMap &vrm,
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@ -16,29 +16,51 @@
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#define DEBUG_TYPE "pre-alloc-split"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineLoopInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/RegisterCoalescer.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/ADT/PostOrderIterator.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/Statistic.h"
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#include <map>
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using namespace llvm;
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STATISTIC(NumSplit , "Number of intervals split");
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namespace {
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class VISIBILITY_HIDDEN PreAllocSplitting : public MachineFunctionPass {
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// ProcessedBarriers - Register live interval barriers that have already
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// been processed.
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SmallPtrSet<MachineInstr*, 16> ProcessedBarriers;
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MachineFunction *CurMF;
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const TargetMachine *TM;
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const TargetInstrInfo *TII;
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MachineFrameInfo *MFI;
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MachineRegisterInfo *MRI;
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LiveIntervals *LIs;
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// Barrier - Current barrier being processed.
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MachineInstr *Barrier;
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// BarrierMBB - Basic block where the barrier resides in.
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MachineBasicBlock *BarrierMBB;
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// Barrier - Current barrier index.
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unsigned BarrierIdx;
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// CurrLI - Current live interval being split.
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LiveInterval *CurrLI;
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// LIValNoSSMap - A map from live interval and val# pairs to spill slots.
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// This records what live interval's val# has been split and what spill
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// slot was used.
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std::map<std::pair<unsigned, unsigned>, int> LIValNoSSMap;
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// ActiveBarriers - Register live interval barriers that are currently
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// being processed.
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SmallSet<unsigned, 16> ActiveBarriers;
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public:
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static char ID;
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PreAllocSplitting() : MachineFunctionPass(&ID) {}
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@ -48,24 +70,60 @@ namespace {
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<LiveIntervals>();
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AU.addPreserved<LiveIntervals>();
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AU.addPreserved<MachineLoopInfo>();
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AU.addPreserved<RegisterCoalescer>();
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if (StrongPHIElim)
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AU.addPreservedID(StrongPHIEliminationID);
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else
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AU.addPreservedID(PHIEliminationID);
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AU.addPreservedID(TwoAddressInstructionPassID);
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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virtual void releaseMemory() {
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ProcessedBarriers.clear();
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ActiveBarriers.clear();
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LIValNoSSMap.clear();
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}
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virtual const char *getPassName() const {
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return "Pre-Register Allocaton Live Interval Splitting";
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}
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/// print - Implement the dump method.
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virtual void print(std::ostream &O, const Module* M = 0) const {
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LIs->print(O, M);
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}
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void print(std::ostream *O, const Module* M = 0) const {
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if (O) print(*O, M);
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}
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private:
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MachineBasicBlock::iterator
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findNextEmptySlot(MachineBasicBlock*, MachineInstr*,
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unsigned&);
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MachineBasicBlock::iterator
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findSpillPoint(MachineBasicBlock*, MachineInstr*,
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SmallPtrSet<MachineInstr*, 4>&, unsigned&);
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MachineBasicBlock::iterator
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findRestorePoint(MachineBasicBlock*, MachineInstr*,
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SmallPtrSet<MachineInstr*, 4>&, unsigned&);
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void RecordSplit(unsigned, unsigned, unsigned, int);
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bool isAlreadySplit(unsigned, unsigned, int&);
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void UpdateIntervalForSplit(VNInfo*, unsigned, unsigned);
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bool ShrinkWrapToLastUse(MachineBasicBlock*,
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std::vector<MachineOperand*>&);
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void ShrinkWrapLiveInterval(VNInfo*, MachineBasicBlock*,
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MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*, 8>&,
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DenseMap<unsigned, std::vector<MachineOperand*> >&);
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bool SplitRegLiveInterval(LiveInterval*);
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bool SplitRegLiveIntervals(const TargetRegisterClass **);
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};
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} // end anonymous namespace
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@ -76,6 +134,507 @@ X("pre-alloc-splitting", "Pre-Register Allocation Live Interval Splitting");
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const PassInfo *const llvm::PreAllocSplittingID = &X;
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bool PreAllocSplitting::runOnMachineFunction(MachineFunction &MF) {
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return false;
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/// findNextEmptySlot - Find a gap after the given machine instruction in the
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/// instruction index map. If there isn't one, return end().
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MachineBasicBlock::iterator
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PreAllocSplitting::findNextEmptySlot(MachineBasicBlock *MBB, MachineInstr *MI,
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unsigned &SpotIndex) {
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MachineBasicBlock::iterator MII = MI;
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if (++MII != MBB->end()) {
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unsigned Index = LIs->findGapBeforeInstr(LIs->getInstructionIndex(MII));
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if (Index) {
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SpotIndex = Index;
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return MII;
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}
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}
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return MBB->end();
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}
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/// findSpillPoint - Find a gap as far away from the given MI that's suitable
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/// for spilling the current live interval. The index must be before any
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/// defs and uses of the live interval register in the mbb. Return begin() if
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/// none is found.
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MachineBasicBlock::iterator
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PreAllocSplitting::findSpillPoint(MachineBasicBlock *MBB, MachineInstr *MI,
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SmallPtrSet<MachineInstr*, 4> &RefsInMBB,
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unsigned &SpillIndex) {
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MachineBasicBlock::iterator Pt = MBB->begin();
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// Go top down if RefsInMBB is empty.
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if (RefsInMBB.empty()) {
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MachineBasicBlock::iterator MII = MBB->begin();
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MachineBasicBlock::iterator EndPt = MI;
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do {
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++MII;
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unsigned Index = LIs->getInstructionIndex(MII);
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unsigned Gap = LIs->findGapBeforeInstr(Index);
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if (Gap) {
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Pt = MII;
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SpillIndex = Gap;
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break;
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}
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} while (MII != EndPt);
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} else {
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MachineBasicBlock::iterator MII = MI;
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while (MII != MBB->begin() && !RefsInMBB.count(MII)) {
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unsigned Index = LIs->getInstructionIndex(MII);
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if (LIs->hasGapBeforeInstr(Index)) {
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Pt = MII;
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SpillIndex = LIs->findGapBeforeInstr(Index, true);
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}
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--MII;
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}
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}
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return Pt;
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}
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/// findRestorePoint - Find a gap in the instruction index map that's suitable
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/// for restoring the current live interval value. The index must be before any
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/// uses of the live interval register in the mbb. Return end() if none is
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/// found.
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MachineBasicBlock::iterator
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PreAllocSplitting::findRestorePoint(MachineBasicBlock *MBB, MachineInstr *MI,
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SmallPtrSet<MachineInstr*, 4> &RefsInMBB,
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unsigned &RestoreIndex) {
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MachineBasicBlock::iterator Pt = MBB->end();
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// Go bottom up if RefsInMBB is empty.
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if (RefsInMBB.empty()) {
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MachineBasicBlock::iterator MII = MBB->end();
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MachineBasicBlock::iterator EndPt = MI;
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do {
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--MII;
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unsigned Index = LIs->getInstructionIndex(MII);
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unsigned Gap = LIs->hasGapBeforeInstr(Index);
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if (Gap) {
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Pt = MII;
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RestoreIndex = Gap;
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break;
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}
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} while (MII != EndPt);
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} else {
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MachineBasicBlock::iterator MII = MI;
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MII = ++MII;
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while (MII != MBB->end()) {
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unsigned Index = LIs->getInstructionIndex(MII);
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unsigned Gap = LIs->findGapBeforeInstr(Index);
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if (Gap) {
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Pt = MII;
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RestoreIndex = Gap;
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}
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if (RefsInMBB.count(MII))
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break;
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++MII;
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}
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}
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return Pt;
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}
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/// RecordSplit - Given a register live interval is split, remember the spill
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/// slot where the val#s are in.
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void PreAllocSplitting::RecordSplit(unsigned Reg, unsigned SpillIndex,
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unsigned RestoreIndex, int SS) {
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LiveInterval::iterator LR =
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CurrLI->FindLiveRangeContaining(LIs->getUseIndex(SpillIndex));
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LIValNoSSMap.insert(std::make_pair(std::make_pair(CurrLI->reg, LR->valno->id),
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SS));
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LR = CurrLI->FindLiveRangeContaining(LIs->getDefIndex(RestoreIndex));
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LIValNoSSMap.insert(std::make_pair(std::make_pair(CurrLI->reg, LR->valno->id),
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SS));
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}
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/// isAlreadySplit - Return if a given val# of a register live interval is already
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/// split. Also return by reference the spill stock where the value is.
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bool PreAllocSplitting::isAlreadySplit(unsigned Reg, unsigned ValNoId, int &SS){
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std::map<std::pair<unsigned, unsigned>, int>::iterator I =
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LIValNoSSMap.find(std::make_pair(Reg, ValNoId));
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if (I == LIValNoSSMap.end())
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return false;
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SS = I->second;
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return true;
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}
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/// UpdateIntervalForSplit - Given the specified val# of the current live
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/// interval is being split, and the split and rejoin indices, update the live
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/// interval accordingly.
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void
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PreAllocSplitting::UpdateIntervalForSplit(VNInfo *ValNo, unsigned SplitIndex,
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unsigned JoinIndex) {
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SmallVector<std::pair<unsigned,unsigned>, 4> Before;
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SmallVector<std::pair<unsigned,unsigned>, 4> After;
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SmallVector<unsigned, 4> BeforeKills;
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SmallVector<unsigned, 4> AfterKills;
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SmallPtrSet<const LiveRange*, 4> Processed;
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// First, let's figure out which parts of the live interval is now defined
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// by the restore, which are defined by the original definition.
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const LiveRange *LR = CurrLI->getLiveRangeContaining(JoinIndex);
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After.push_back(std::make_pair(JoinIndex, LR->end));
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assert(LR->contains(SplitIndex));
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Before.push_back(std::make_pair(LR->start, SplitIndex));
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BeforeKills.push_back(SplitIndex);
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Processed.insert(LR);
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SmallVector<MachineBasicBlock*, 4> WorkList;
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MachineBasicBlock *MBB = LIs->getMBBFromIndex(LR->end-1);
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for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
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SE = MBB->succ_end(); SI != SE; ++SI)
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WorkList.push_back(*SI);
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while (!WorkList.empty()) {
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MBB = WorkList.back();
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WorkList.pop_back();
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unsigned Idx = LIs->getMBBStartIdx(MBB);
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LR = CurrLI->getLiveRangeContaining(Idx);
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if (LR && LR->valno == ValNo && !Processed.count(LR)) {
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After.push_back(std::make_pair(LR->start, LR->end));
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if (CurrLI->isKill(ValNo, LR->end))
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AfterKills.push_back(LR->end);
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Idx = LIs->getMBBEndIdx(MBB);
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if (LR->end > Idx) {
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for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
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SE = MBB->succ_end(); SI != SE; ++SI)
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WorkList.push_back(*SI);
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if (LR->end > Idx+1) {
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MBB = LIs->getMBBFromIndex(LR->end-1);
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for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
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SE = MBB->succ_end(); SI != SE; ++SI)
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WorkList.push_back(*SI);
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}
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}
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Processed.insert(LR);
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}
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}
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for (LiveInterval::iterator I = CurrLI->begin(), E = CurrLI->end();
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I != E; ++I) {
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LiveRange *LR = I;
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if (LR->valno == ValNo && !Processed.count(LR)) {
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Before.push_back(std::make_pair(LR->start, LR->end));
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if (CurrLI->isKill(ValNo, LR->end))
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BeforeKills.push_back(LR->end);
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}
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}
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// Now create new val#s to represent the live ranges defined by the old def
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// those defined by the restore.
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unsigned AfterDef = ValNo->def;
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MachineInstr *AfterCopy = ValNo->copy;
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bool HasPHIKill = ValNo->hasPHIKill;
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CurrLI->removeValNo(ValNo);
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VNInfo *BValNo = CurrLI->getNextValue(AfterDef, AfterCopy,
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LIs->getVNInfoAllocator());
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VNInfo *AValNo = CurrLI->getNextValue(JoinIndex,0, LIs->getVNInfoAllocator());
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AValNo->hasPHIKill = HasPHIKill;
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CurrLI->addKills(AValNo, AfterKills);
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CurrLI->addKills(BValNo, BeforeKills);
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for (unsigned i = 0, e = Before.size(); i != e; ++i) {
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unsigned Start = Before[i].first;
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unsigned End = Before[i].second;
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CurrLI->addRange(LiveRange(Start, End, BValNo));
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}
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for (unsigned i = 0, e = After.size(); i != e; ++i) {
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unsigned Start = After[i].first;
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unsigned End = After[i].second;
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CurrLI->addRange(LiveRange(Start, End, AValNo));
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}
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}
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/// ShrinkWrapToLastUse - There are uses of the current live interval in the
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/// given block, shrink wrap the live interval to the last use (i.e. remove
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/// from last use to the end of the mbb). In case mbb is the where the barrier
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/// is, remove from the last use to the barrier.
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bool
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PreAllocSplitting::ShrinkWrapToLastUse(MachineBasicBlock *MBB,
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std::vector<MachineOperand*> &Uses) {
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MachineOperand *LastMO = 0;
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MachineInstr *LastMI = 0;
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if (MBB != BarrierMBB && Uses.size() == 1) {
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// Single use, no need to traverse the block. We can't assume this for the
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// barrier bb though since the use is probably below the barrier.
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LastMO = Uses[0];
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LastMI = LastMO->getParent();
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} else {
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SmallPtrSet<MachineInstr*, 4> UseMIs;
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for (unsigned i = 0, e = Uses.size(); i != e; ++i)
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UseMIs.insert(Uses[i]->getParent());
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MachineBasicBlock::iterator MII;
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if (MBB == BarrierMBB) {
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MII = Barrier;
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--MII;
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} else
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MII = MBB->end();
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for (MachineBasicBlock::iterator MEE = MBB->begin(); MII != MEE; --MII) {
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MachineInstr *UseMI = &*MII;
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if (!UseMIs.count(UseMI))
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continue;
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for (unsigned i = 0, e = UseMI->getNumOperands(); i != e; ++i) {
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MachineOperand &MO = UseMI->getOperand(i);
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if (MO.isReg() && MO.getReg() == CurrLI->reg) {
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LastMO = &MO;
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break;
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}
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}
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LastMI = UseMI;
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break;
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}
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}
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// Cut off live range from last use (or beginning of the mbb if there
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// are no uses in it) to the end of the mbb.
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unsigned RangeStart, RangeEnd = LIs->getMBBEndIdx(MBB)+1;
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if (LastMI) {
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RangeStart = LIs->getUseIndex(LIs->getInstructionIndex(LastMI))+1;
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assert(!LastMO->isKill() && "Last use already terminates the interval?");
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LastMO->setIsKill();
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} else {
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assert(MBB == BarrierMBB);
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RangeStart = LIs->getMBBStartIdx(MBB);
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}
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if (MBB == BarrierMBB)
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RangeEnd = LIs->getUseIndex(BarrierIdx);
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CurrLI->removeRange(RangeStart, RangeEnd);
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// Return true if the last use becomes a new kill.
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return LastMI;
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}
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/// ShrinkWrapLiveInterval - Recursively traverse the predecessor
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/// chain to find the new 'kills' and shrink wrap the live interval to the
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/// new kill indices.
|
||||
void
|
||||
PreAllocSplitting::ShrinkWrapLiveInterval(VNInfo *ValNo,
|
||||
MachineBasicBlock *MBB, MachineBasicBlock *DefMBB,
|
||||
SmallPtrSet<MachineBasicBlock*, 8> &Visited,
|
||||
DenseMap<unsigned, std::vector<MachineOperand*> > &Uses) {
|
||||
if (!Visited.insert(MBB))
|
||||
return;
|
||||
|
||||
DenseMap<unsigned, std::vector<MachineOperand*> >::iterator UMII =
|
||||
Uses.find(MBB->getNumber());
|
||||
if (UMII != Uses.end()) {
|
||||
// At least one use in this mbb, lets look for the kill.
|
||||
if (ShrinkWrapToLastUse(MBB, UMII->second))
|
||||
// Found a kill, shrink wrapping of this path ends here.
|
||||
return;
|
||||
} else {
|
||||
// Remove entire live range of the bb out of the live interval.
|
||||
CurrLI->removeRange(LIs->getMBBStartIdx(MBB), LIs->getMBBEndIdx(MBB));
|
||||
abort(); // FIXME
|
||||
}
|
||||
|
||||
if (MBB == DefMBB)
|
||||
// Reached the def mbb, stop traversing this path further.
|
||||
return;
|
||||
|
||||
// Traverse the pathes up the predecessor chains further.
|
||||
for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(),
|
||||
PE = MBB->pred_end(); PI != PE; ++PI) {
|
||||
MachineBasicBlock *Pred = *PI;
|
||||
if (Pred == MBB)
|
||||
continue;
|
||||
if (Pred == DefMBB && ValNo->hasPHIKill)
|
||||
// Pred is the def bb and the def reaches other val#s, we must
|
||||
// allow the value to be live out of the bb.
|
||||
continue;
|
||||
ShrinkWrapLiveInterval(ValNo, Pred, DefMBB, Visited, Uses);
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
/// SplitRegLiveInterval - Split (spill and restore) the given live interval
|
||||
/// so it would not cross the barrier that's being processed. Shrink wrap
|
||||
/// (minimize) the live interval to the last uses.
|
||||
bool PreAllocSplitting::SplitRegLiveInterval(LiveInterval *LI) {
|
||||
CurrLI = LI;
|
||||
|
||||
// Find live range where current interval cross the barrier.
|
||||
LiveInterval::iterator LR =
|
||||
CurrLI->FindLiveRangeContaining(LIs->getUseIndex(BarrierIdx));
|
||||
VNInfo *ValNo = LR->valno;
|
||||
|
||||
if (ValNo->def == ~1U) {
|
||||
// Defined by a dead def? How can this be?
|
||||
assert(0 && "Val# is defined by a dead def?");
|
||||
abort();
|
||||
}
|
||||
|
||||
// Find all references in the barrier mbb.
|
||||
SmallPtrSet<MachineInstr*, 4> RefsInMBB;
|
||||
for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(CurrLI->reg),
|
||||
E = MRI->reg_end(); I != E; ++I) {
|
||||
MachineInstr *RefMI = &*I;
|
||||
if (RefMI->getParent() == BarrierMBB)
|
||||
RefsInMBB.insert(RefMI);
|
||||
}
|
||||
|
||||
// Find a point to restore the value after the barrier.
|
||||
unsigned RestoreIndex;
|
||||
MachineBasicBlock::iterator RestorePt =
|
||||
findRestorePoint(BarrierMBB, Barrier, RefsInMBB, RestoreIndex);
|
||||
if (RestorePt == BarrierMBB->end())
|
||||
return false;
|
||||
|
||||
// Add a spill either before the barrier or after the definition.
|
||||
MachineBasicBlock *DefMBB = NULL;
|
||||
const TargetRegisterClass *RC = MRI->getRegClass(CurrLI->reg);
|
||||
int SS;
|
||||
unsigned SpillIndex = 0;
|
||||
if (isAlreadySplit(CurrLI->reg, ValNo->id, SS)) {
|
||||
// If it's already split, just restore the value. There is no need to spill
|
||||
// the def again.
|
||||
abort(); // FIXME
|
||||
} else if (ValNo->def == ~0U) {
|
||||
// If it's defined by a phi, we must split just before the barrier.
|
||||
MachineBasicBlock::iterator SpillPt =
|
||||
findSpillPoint(BarrierMBB, Barrier, RefsInMBB, SpillIndex);
|
||||
if (SpillPt == BarrierMBB->begin())
|
||||
return false; // No gap to insert spill.
|
||||
// Add spill.
|
||||
SS = MFI->CreateStackObject(RC->getSize(), RC->getAlignment());
|
||||
TII->storeRegToStackSlot(*BarrierMBB, SpillPt, CurrLI->reg, true, SS, RC);
|
||||
MachineInstr *StoreMI = prior(SpillPt);
|
||||
LIs->InsertMachineInstrInMaps(StoreMI, SpillIndex);
|
||||
} else {
|
||||
// Check if it's possible to insert a spill after the def MI.
|
||||
MachineInstr *DefMI = LIs->getInstructionFromIndex(ValNo->def);
|
||||
DefMBB = DefMI->getParent();
|
||||
MachineBasicBlock::iterator SpillPt =
|
||||
findNextEmptySlot(DefMBB, DefMI, SpillIndex);
|
||||
if (SpillPt == DefMBB->end())
|
||||
return false; // No gap to insert spill.
|
||||
SS = MFI->CreateStackObject(RC->getSize(), RC->getAlignment());
|
||||
|
||||
// Add spill. The store instruction does *not* kill the register.
|
||||
TII->storeRegToStackSlot(*DefMBB, SpillPt, CurrLI->reg, false, SS, RC);
|
||||
MachineInstr *StoreMI = prior(SpillPt);
|
||||
LIs->InsertMachineInstrInMaps(StoreMI, SpillIndex);
|
||||
}
|
||||
|
||||
// Add restore.
|
||||
// FIXME: Create live interval for stack slot.
|
||||
TII->loadRegFromStackSlot(*BarrierMBB, RestorePt, CurrLI->reg, SS, RC);
|
||||
MachineInstr *LoadMI = prior(RestorePt);
|
||||
LIs->InsertMachineInstrInMaps(LoadMI, RestoreIndex);
|
||||
|
||||
// If live interval is spilled in the same block as the barrier, just
|
||||
// create a hole in the interval.
|
||||
if (!DefMBB ||
|
||||
LIs->getInstructionFromIndex(SpillIndex)->getParent() == BarrierMBB) {
|
||||
UpdateIntervalForSplit(ValNo, LIs->getUseIndex(SpillIndex)+1,
|
||||
LIs->getDefIndex(RestoreIndex));
|
||||
|
||||
// Record val# values are in the specific spill slot.
|
||||
RecordSplit(CurrLI->reg, SpillIndex, RestoreIndex, SS);
|
||||
|
||||
++NumSplit;
|
||||
return true;
|
||||
}
|
||||
|
||||
// Shrink wrap the live interval by walking up the CFG and find the
|
||||
// new kills.
|
||||
// Now let's find all the uses of the val#.
|
||||
DenseMap<unsigned, std::vector<MachineOperand*> > Uses;
|
||||
for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(CurrLI->reg),
|
||||
UE = MRI->use_end(); UI != UE; ++UI) {
|
||||
MachineOperand &UseMO = UI.getOperand();
|
||||
MachineInstr *UseMI = UseMO.getParent();
|
||||
unsigned UseIdx = LIs->getInstructionIndex(UseMI);
|
||||
LiveInterval::iterator ULR = CurrLI->FindLiveRangeContaining(UseIdx);
|
||||
if (ULR->valno != ValNo)
|
||||
continue;
|
||||
MachineBasicBlock *UseMBB = UseMI->getParent();
|
||||
unsigned MBBId = UseMBB->getNumber();
|
||||
DenseMap<unsigned, std::vector<MachineOperand*> >::iterator UMII =
|
||||
Uses.find(MBBId);
|
||||
if (UMII != Uses.end())
|
||||
UMII->second.push_back(&UseMO);
|
||||
else {
|
||||
std::vector<MachineOperand*> Ops;
|
||||
Ops.push_back(&UseMO);
|
||||
Uses.insert(std::make_pair(MBBId, Ops));
|
||||
}
|
||||
}
|
||||
|
||||
// Walk up the predecessor chains.
|
||||
SmallPtrSet<MachineBasicBlock*, 8> Visited;
|
||||
ShrinkWrapLiveInterval(ValNo, BarrierMBB, DefMBB, Visited, Uses);
|
||||
|
||||
// Remove live range from barrier to the restore. FIXME: Find a better
|
||||
// point to re-start the live interval.
|
||||
UpdateIntervalForSplit(ValNo, LIs->getUseIndex(BarrierIdx)+1,
|
||||
LIs->getDefIndex(RestoreIndex));
|
||||
// Record val# values are in the specific spill slot.
|
||||
RecordSplit(CurrLI->reg, BarrierIdx, RestoreIndex, SS);
|
||||
|
||||
++NumSplit;
|
||||
return true;
|
||||
}
|
||||
|
||||
/// SplitRegLiveIntervals - Split all register live intervals that cross the
|
||||
/// barrier that's being processed.
|
||||
bool
|
||||
PreAllocSplitting::SplitRegLiveIntervals(const TargetRegisterClass **RCs) {
|
||||
// First find all the virtual registers whose live intervals are intercepted
|
||||
// by the current barrier.
|
||||
SmallVector<LiveInterval*, 8> Intervals;
|
||||
for (const TargetRegisterClass **RC = RCs; *RC; ++RC) {
|
||||
std::vector<unsigned> &VRs = MRI->getRegClassVirtRegs(*RC);
|
||||
for (unsigned i = 0, e = VRs.size(); i != e; ++i) {
|
||||
unsigned Reg = VRs[i];
|
||||
if (!LIs->hasInterval(Reg))
|
||||
continue;
|
||||
LiveInterval *LI = &LIs->getInterval(Reg);
|
||||
if (LI->liveAt(BarrierIdx) && !Barrier->readsRegister(Reg))
|
||||
// Virtual register live interval is intercepted by the barrier. We
|
||||
// should split and shrink wrap its interval if possible.
|
||||
Intervals.push_back(LI);
|
||||
}
|
||||
}
|
||||
|
||||
// Process the affected live intervals.
|
||||
bool Change = false;
|
||||
while (!Intervals.empty()) {
|
||||
LiveInterval *LI = Intervals.back();
|
||||
Intervals.pop_back();
|
||||
Change |= SplitRegLiveInterval(LI);
|
||||
}
|
||||
|
||||
return Change;
|
||||
}
|
||||
|
||||
bool PreAllocSplitting::runOnMachineFunction(MachineFunction &MF) {
|
||||
CurMF = &MF;
|
||||
TM = &MF.getTarget();
|
||||
TII = TM->getInstrInfo();
|
||||
MFI = MF.getFrameInfo();
|
||||
MRI = &MF.getRegInfo();
|
||||
LIs = &getAnalysis<LiveIntervals>();
|
||||
|
||||
bool MadeChange = false;
|
||||
|
||||
// Make sure blocks are numbered in order.
|
||||
MF.RenumberBlocks();
|
||||
|
||||
for (MachineFunction::reverse_iterator I = MF.rbegin(), E = MF.rend();
|
||||
I != E; ++I) {
|
||||
BarrierMBB = &*I;
|
||||
for (MachineBasicBlock::reverse_iterator II = BarrierMBB->rbegin(),
|
||||
EE = BarrierMBB->rend(); II != EE; ++II) {
|
||||
Barrier = &*II;
|
||||
const TargetRegisterClass **BarrierRCs =
|
||||
Barrier->getDesc().getRegClassBarriers();
|
||||
if (!BarrierRCs)
|
||||
continue;
|
||||
BarrierIdx = LIs->getInstructionIndex(Barrier);
|
||||
MadeChange |= SplitRegLiveIntervals(BarrierRCs);
|
||||
}
|
||||
}
|
||||
|
||||
return MadeChange;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -49,6 +49,11 @@ NewHeuristic("new-spilling-heuristic",
|
|||
cl::desc("Use new spilling heuristic"),
|
||||
cl::init(false), cl::Hidden);
|
||||
|
||||
static cl::opt<bool>
|
||||
PreSplitIntervals("pre-alloc-split",
|
||||
cl::desc("Pre-register allocation live interval splitting"),
|
||||
cl::init(false), cl::Hidden);
|
||||
|
||||
static RegisterRegAlloc
|
||||
linearscanRegAlloc("linearscan", "linear scan register allocator",
|
||||
createLinearScanRegisterAllocator);
|
||||
|
|
@ -113,6 +118,8 @@ namespace {
|
|||
// Make sure PassManager knows which analyses to make available
|
||||
// to coalescing and which analyses coalescing invalidates.
|
||||
AU.addRequiredTransitive<RegisterCoalescer>();
|
||||
if (PreSplitIntervals)
|
||||
AU.addRequiredID(PreAllocSplittingID);
|
||||
AU.addRequired<LiveStacks>();
|
||||
AU.addPreserved<LiveStacks>();
|
||||
AU.addRequired<MachineLoopInfo>();
|
||||
|
|
|
|||
Loading…
Reference in New Issue