forked from OSchip/llvm-project
[AArch64] Don't combine "select (setcc i1 LHS, RHS), vL, vR".
r208210 introduced an optimization that improves the vector select codegen by doing the setcc on vectors directly. This is a problem they the setcc operands are i1s, because the optimization would create vectors of i1, which aren't legal. Part of PR21549. Differential Revision: http://reviews.llvm.org/D6308 llvm-svn: 223075
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@ -8479,6 +8479,12 @@ static SDValue performSelectCombine(SDNode *N, SelectionDAG &DAG) {
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// largest real NEON comparison is 64-bits per lane, which means the result is
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// at most 32-bits and an illegal vector. Just bail out for now.
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EVT SrcVT = N0.getOperand(0).getValueType();
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// Don't try to do this optimization when the setcc itself has i1 operands.
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// There are no legal vectors of i1, so this would be pointless.
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if (SrcVT == MVT::i1)
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return SDValue();
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int NumMaskElts = ResVT.getSizeInBits() / SrcVT.getSizeInBits();
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if (!ResVT.isVector() || NumMaskElts == 0)
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return SDValue();
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@ -204,3 +204,18 @@ define <2 x double> @test_select_cc_v2f64(double %a, double %b, <2 x double> %c,
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%e = select i1 %cmp31, <2 x double> %c, <2 x double> %d
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ret <2 x double> %e
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}
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; Special case: when the select condition is an icmp with i1 operands, don't
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; do the comparison on vectors.
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; Part of PR21549.
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define <2 x i32> @test_select_cc_v2i32_icmpi1(i1 %cc, <2 x i32> %a, <2 x i32> %b) {
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; CHECK-LABEL: test_select_cc_v2i32_icmpi1:
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; CHECK: tst w0, #0x1
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; CHECK: csetm [[MASK:w[0-9]+]], ne
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; CHECK: dup [[DUPMASK:v[0-9]+]].2s, [[MASK]]
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; CHECK: bsl [[DUPMASK]].8b, v0.8b, v1.8b
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; CHECK: mov v0.16b, [[DUPMASK]].16b
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%cmp = icmp ne i1 %cc, 0
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%e = select i1 %cmp, <2 x i32> %a, <2 x i32> %b
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ret <2 x i32> %e
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}
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