[AArch64] Don't combine "select (setcc i1 LHS, RHS), vL, vR".

r208210 introduced an optimization that improves the vector select
codegen by doing the setcc on vectors directly.
This is a problem they the setcc operands are i1s, because the
optimization would create vectors of i1, which aren't legal.

Part of PR21549.

Differential Revision: http://reviews.llvm.org/D6308

llvm-svn: 223075
This commit is contained in:
Ahmed Bougacha 2014-12-01 20:59:00 +00:00
parent 879463206e
commit d0ce058f2c
2 changed files with 21 additions and 0 deletions

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@ -8479,6 +8479,12 @@ static SDValue performSelectCombine(SDNode *N, SelectionDAG &DAG) {
// largest real NEON comparison is 64-bits per lane, which means the result is
// at most 32-bits and an illegal vector. Just bail out for now.
EVT SrcVT = N0.getOperand(0).getValueType();
// Don't try to do this optimization when the setcc itself has i1 operands.
// There are no legal vectors of i1, so this would be pointless.
if (SrcVT == MVT::i1)
return SDValue();
int NumMaskElts = ResVT.getSizeInBits() / SrcVT.getSizeInBits();
if (!ResVT.isVector() || NumMaskElts == 0)
return SDValue();

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@ -204,3 +204,18 @@ define <2 x double> @test_select_cc_v2f64(double %a, double %b, <2 x double> %c,
%e = select i1 %cmp31, <2 x double> %c, <2 x double> %d
ret <2 x double> %e
}
; Special case: when the select condition is an icmp with i1 operands, don't
; do the comparison on vectors.
; Part of PR21549.
define <2 x i32> @test_select_cc_v2i32_icmpi1(i1 %cc, <2 x i32> %a, <2 x i32> %b) {
; CHECK-LABEL: test_select_cc_v2i32_icmpi1:
; CHECK: tst w0, #0x1
; CHECK: csetm [[MASK:w[0-9]+]], ne
; CHECK: dup [[DUPMASK:v[0-9]+]].2s, [[MASK]]
; CHECK: bsl [[DUPMASK]].8b, v0.8b, v1.8b
; CHECK: mov v0.16b, [[DUPMASK]].16b
%cmp = icmp ne i1 %cc, 0
%e = select i1 %cmp, <2 x i32> %a, <2 x i32> %b
ret <2 x i32> %e
}