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[mips][microMIPS] Implement ABSQ.QB, ABSQ_S.PH, ABSQ_S.W, ABSQ_S.QB, INSV, MADD, MADDU, MSUB, MSUBU, MULT and MULTU instructions 

Differential Revision: http://reviews.llvm.org/D13721

llvm-svn: 250683
This commit is contained in:
Zlatko Buljan 2015-10-19 06:34:44 +00:00
parent 69535df0e9
commit d0a7d6e4ee
7 changed files with 97 additions and 11 deletions
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24
llvm/lib/Target/Mips/MicroMipsDSPInstrFormats.td
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@ -40,3 +40,27 @@ class POOL32A_AC2R_FMT<string opstr, bits<8> funct> : MMDSPInst<opstr> {
let Inst{13-6} = funct;
let Inst{5-0} = 0b111100;
}
class POOL32A_2R_FMT<string opstr, bits<10> op> : MMDSPInst<opstr> {
bits<5> rt;
bits<5> rs;
let Inst{31-26} = 0b000000;
let Inst{25-21} = rt;
let Inst{20-16} = rs;
let Inst{15-6} = op;
let Inst{5-0} = 0b111100;
}
class POOL32A_2RAC_FMT<string opstr, bits<8> op> : MMDSPInst<opstr> {
bits<5> rt;
bits<5> rs;
bits<2> ac;
let Inst{31-26} = 0b000000;
let Inst{25-21} = rt;
let Inst{20-16} = rs;
let Inst{15-14} = ac;
let Inst{13-6} = op;
let Inst{5-0} = 0b111100;
}

38
llvm/lib/Target/Mips/MicroMipsDSPInstrInfo.td
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@ -21,8 +21,34 @@ class DPAQX_SA_W_PH_MMR2_ENC : POOL32A_AC2R_FMT<"dpaqx_sa.w.ph", 0b11001010>;
class DPAU_H_QBL_MM_ENC : POOL32A_AC2R_FMT<"dpau.h.qbl", 0b10000010>;
class DPAU_H_QBR_MM_ENC : POOL32A_AC2R_FMT<"dpau.h.qbr", 0b11000010>;
class DPAX_W_PH_MMR2_ENC : POOL32A_AC2R_FMT<"dpax.w.ph", 0b01000010>;
class ABSQ_S_PH_MM_ENC : POOL32A_2R_FMT<"absq_s.ph", 0b0001000100>;
class ABSQ_S_W_MM_ENC : POOL32A_2R_FMT<"absq_s.w", 0b0010000100>;
class ABSQ_S_QB_MMR2_ENC : POOL32A_2R_FMT<"absq_s.qb", 0b0000000100>;
class INSV_MM_ENC : POOL32A_2R_FMT<"insv", 0b0100000100>;
class MADD_DSP_MM_ENC : POOL32A_2RAC_FMT<"madd", 0b00101010>;
class MADDU_DSP_MM_ENC : POOL32A_2RAC_FMT<"maddu", 0b01101010>;
class MSUB_DSP_MM_ENC : POOL32A_2RAC_FMT<"msub", 0b10101010>;
class MSUBU_DSP_MM_ENC : POOL32A_2RAC_FMT<"msubu", 0b11101010>;
class MULT_DSP_MM_ENC : POOL32A_2RAC_FMT<"mult", 0b00110010>;
class MULTU_DSP_MM_ENC : POOL32A_2RAC_FMT<"multu", 0b01110010>;
// Instruction defs.
class ABSQ_S_PH_MM_R2_DESC_BASE<string opstr, SDPatternOperator OpNode,
InstrItinClass itin, RegisterOperand ROD,
RegisterOperand ROS = ROD> {
dag OutOperandList = (outs ROD:$rt);
dag InOperandList = (ins ROS:$rs);
string AsmString = !strconcat(opstr, "\t$rt, $rs");
list<dag> Pattern = [(set ROD:$rt, (OpNode ROS:$rs))];
InstrItinClass Itinerary = itin;
}
class ABSQ_S_PH_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
"absq_s.ph", int_mips_absq_s_ph, NoItinerary, DSPROpnd>, Defs<[DSPOutFlag20]>;
class ABSQ_S_W_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
"absq_s.w", int_mips_absq_s_w, NoItinerary, GPR32Opnd>, Defs<[DSPOutFlag20]>;
class ABSQ_S_QB_MMR2_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
"absq_s.qb", int_mips_absq_s_qb, NoItinerary, DSPROpnd>, Defs<[DSPOutFlag20]>;
// microMIPS DSP Rev 1
def ADDU_QB_MM : DspMMRel, ADDU_QB_MM_ENC, ADDU_QB_DESC;
def DPAQ_S_W_PH_MM : DspMMRel, DPAQ_S_W_PH_MM_ENC, DPAQ_S_W_PH_DESC;
@ -36,3 +62,15 @@ def DPAQX_S_W_PH_MMR2 : DspMMRel, DPAQX_S_W_PH_MMR2_ENC, DPAQX_S_W_PH_DESC,
def DPAQX_SA_W_PH_MMR2 : DspMMRel, DPAQX_SA_W_PH_MMR2_ENC, DPAQX_SA_W_PH_DESC,
ISA_DSPR2;
def DPAX_W_PH_MMR2 : DspMMRel, DPAX_W_PH_MMR2_ENC, DPAX_W_PH_DESC, ISA_DSPR2;
def ABSQ_S_PH_MM : DspMMRel, ABSQ_S_PH_MM_ENC, ABSQ_S_PH_MM_DESC;
def ABSQ_S_W_MM : DspMMRel, ABSQ_S_W_MM_ENC, ABSQ_S_W_MM_DESC;
def INSV_MM : DspMMRel, INSV_MM_ENC, INSV_DESC;
def MADD_DSP_MM : DspMMRel, MADD_DSP_MM_ENC, MADD_DSP_DESC;
def MADDU_DSP_MM : DspMMRel, MADDU_DSP_MM_ENC, MADDU_DSP_DESC;
def MSUB_DSP_MM : DspMMRel, MSUB_DSP_MM_ENC, MSUB_DSP_DESC;
def MSUBU_DSP_MM : DspMMRel, MSUBU_DSP_MM_ENC, MSUBU_DSP_DESC;
def MULT_DSP_MM : DspMMRel, MULT_DSP_MM_ENC, MULT_DSP_DESC;
def MULTU_DSP_MM : DspMMRel, MULTU_DSP_MM_ENC, MULTU_DSP_DESC;
// microMIPS DSP Rev 2
def ABSQ_S_QB_MMR2 : DspMMRel, ABSQ_S_QB_MMR2_ENC, ABSQ_S_QB_MMR2_DESC,
ISA_DSPR2;

24
llvm/lib/Target/Mips/MipsDSPInstrInfo.td
View File

@ -315,6 +315,7 @@ class ABSQ_S_PH_R2_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
string AsmString = !strconcat(instr_asm, "\t$rd, $rt");
list<dag> Pattern = [(set ROD:$rd, (OpNode ROT:$rt))];
InstrItinClass Itinerary = itin;
string BaseOpcode = instr_asm;
}
class REPL_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
@ -456,6 +457,7 @@ class MULT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
list<dag> Pattern = [(set ACC64DSPOpnd:$ac, (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt))];
InstrItinClass Itinerary = itin;
bit isCommutable = 1;
string BaseOpcode = instr_asm;
}
class MADD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
@ -467,6 +469,7 @@ class MADD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
(OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64DSPOpnd:$acin))];
InstrItinClass Itinerary = itin;
string Constraints = "$acin = $ac";
string BaseOpcode = instr_asm;
}
class MFHI_DESC_BASE<string instr_asm, RegisterOperand RO, SDNode OpNode,
@ -508,6 +511,7 @@ class INSV_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
list<dag> Pattern = [(set GPR32Opnd:$rt, (OpNode GPR32Opnd:$src, GPR32Opnd:$rs))];
InstrItinClass Itinerary = itin;
string Constraints = "$src = $rt";
string BaseOpcode = instr_asm;
}
//===----------------------------------------------------------------------===//
@ -1088,8 +1092,8 @@ def ADDSC : ADDSC_ENC, ADDSC_DESC;
def ADDWC : ADDWC_ENC, ADDWC_DESC;
def MODSUB : MODSUB_ENC, MODSUB_DESC;
def RADDU_W_QB : RADDU_W_QB_ENC, RADDU_W_QB_DESC;
def ABSQ_S_PH : ABSQ_S_PH_ENC, ABSQ_S_PH_DESC;
def ABSQ_S_W : ABSQ_S_W_ENC, ABSQ_S_W_DESC;
def ABSQ_S_PH : DspMMRel, ABSQ_S_PH_ENC, ABSQ_S_PH_DESC;
def ABSQ_S_W : DspMMRel, ABSQ_S_W_ENC, ABSQ_S_W_DESC;
def PRECRQ_QB_PH : PRECRQ_QB_PH_ENC, PRECRQ_QB_PH_DESC;
def PRECRQ_PH_W : PRECRQ_PH_W_ENC, PRECRQ_PH_W_DESC;
def PRECRQ_RS_PH_W : PRECRQ_RS_PH_W_ENC, PRECRQ_RS_PH_W_DESC;
@ -1142,12 +1146,12 @@ def DPAQ_S_W_PH : DspMMRel, DPAQ_S_W_PH_ENC, DPAQ_S_W_PH_DESC;
def DPSQ_S_W_PH : DPSQ_S_W_PH_ENC, DPSQ_S_W_PH_DESC;
def DPAQ_SA_L_W : DspMMRel, DPAQ_SA_L_W_ENC, DPAQ_SA_L_W_DESC;
def DPSQ_SA_L_W : DPSQ_SA_L_W_ENC, DPSQ_SA_L_W_DESC;
def MULT_DSP : MULT_DSP_ENC, MULT_DSP_DESC;
def MULTU_DSP : MULTU_DSP_ENC, MULTU_DSP_DESC;
def MADD_DSP : MADD_DSP_ENC, MADD_DSP_DESC;
def MADDU_DSP : MADDU_DSP_ENC, MADDU_DSP_DESC;
def MSUB_DSP : MSUB_DSP_ENC, MSUB_DSP_DESC;
def MSUBU_DSP : MSUBU_DSP_ENC, MSUBU_DSP_DESC;
def MULT_DSP : DspMMRel, MULT_DSP_ENC, MULT_DSP_DESC;
def MULTU_DSP : DspMMRel, MULTU_DSP_ENC, MULTU_DSP_DESC;
def MADD_DSP : DspMMRel, MADD_DSP_ENC, MADD_DSP_DESC;
def MADDU_DSP : DspMMRel, MADDU_DSP_ENC, MADDU_DSP_DESC;
def MSUB_DSP : DspMMRel, MSUB_DSP_ENC, MSUB_DSP_DESC;
def MSUBU_DSP : DspMMRel, MSUBU_DSP_ENC, MSUBU_DSP_DESC;
def CMPU_EQ_QB : CMPU_EQ_QB_ENC, CMPU_EQ_QB_DESC;
def CMPU_LT_QB : CMPU_LT_QB_ENC, CMPU_LT_QB_DESC;
def CMPU_LE_QB : CMPU_LE_QB_ENC, CMPU_LE_QB_DESC;
@ -1169,7 +1173,7 @@ def LWX : LWX_ENC, LWX_DESC;
def LHX : LHX_ENC, LHX_DESC;
def LBUX : LBUX_ENC, LBUX_DESC;
def BPOSGE32 : BPOSGE32_ENC, BPOSGE32_DESC;
def INSV : INSV_ENC, INSV_DESC;
def INSV : DspMMRel, INSV_ENC, INSV_DESC;
def EXTP : EXTP_ENC, EXTP_DESC;
def EXTPV : EXTPV_ENC, EXTPV_DESC;
def EXTPDP : EXTPDP_ENC, EXTPDP_DESC;
@ -1198,7 +1202,7 @@ def SUBU_S_PH : SUBU_S_PH_ENC, SUBU_S_PH_DESC;
def CMPGDU_EQ_QB : CMPGDU_EQ_QB_ENC, CMPGDU_EQ_QB_DESC;
def CMPGDU_LT_QB : CMPGDU_LT_QB_ENC, CMPGDU_LT_QB_DESC;
def CMPGDU_LE_QB : CMPGDU_LE_QB_ENC, CMPGDU_LE_QB_DESC;
def ABSQ_S_QB : ABSQ_S_QB_ENC, ABSQ_S_QB_DESC;
def ABSQ_S_QB : DspMMRel, ABSQ_S_QB_ENC, ABSQ_S_QB_DESC;
def ADDUH_QB : ADDUH_QB_ENC, ADDUH_QB_DESC;
def ADDUH_R_QB : ADDUH_R_QB_ENC, ADDUH_R_QB_DESC;
def SUBUH_QB : SUBUH_QB_ENC, SUBUH_QB_DESC;

9
llvm/test/MC/Disassembler/Mips/micromips-dsp/valid.txt
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@ -5,3 +5,12 @@
0x00 0x64 0x92 0xbc # CHECK: dpaq_sa.l.w $ac2, $4, $3
0x00 0x83 0x60 0xbc # CHECK: dpau.h.qbl $ac1, $3, $4
0x02 0xb4 0xb0 0xbc # CHECK: dpau.h.qbr $ac2, $20, $21
0x00 0x64 0x11 0x3c # CHECK: absq_s.ph $3, $4
0x00 0x64 0x21 0x3c # CHECK: absq_s.w $3, $4
0x00 0x64 0x41 0x3c # CHECK: insv $3, $4
0x00 0xe6 0x4a 0xbc # CHECK: madd $ac1, $6, $7
0x01 0x28 0x1a 0xbc # CHECK: maddu $ac0, $8, $9
0x01 0x6a 0xea 0xbc # CHECK: msub $ac3, $10, $11
0x01 0xac 0xba 0xbc # CHECK: msubu $ac2, $12, $13
0x00 0x62 0xcc 0xbc # CHECK: mult $ac3, $2, $3
0x00 0xa4 0x9c 0xbc # CHECK: multu $ac2, $4, $5

3
llvm/test/MC/Disassembler/Mips/micromips-dspr2/valid.txt
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@ -1,5 +1,6 @@
# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r6 -mattr=micromips -mattr=+dspr2 | FileCheck %s
# RUN: llvm-mc --disassemble %s -triple=mips-unknown-linux -mcpu=mips32r6 -mattr=micromips -mattr=+dspr2 | FileCheck %s
0x00 0x64 0x01 0x3c # CHECK: absq_s.qb $3, $4
0x00 0x43 0x00 0xbc # CHECK: dpa.w.ph $ac0, $3, $2
0x00 0xec 0xe2 0xbc # CHECK: dpaqx_s.w.ph $ac3, $12, $7
0x00 0xc5 0x32 0xbc # CHECK: dpaqx_sa.w.ph $ac0, $5, $6

9
llvm/test/MC/Mips/micromips-dsp/valid.s
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@ -6,3 +6,12 @@
dpaq_sa.l.w $ac2, $4, $3 # CHECK: dpaq_sa.l.w $ac2, $4, $3 # encoding: [0x00,0x64,0x92,0xbc]
dpau.h.qbl $ac1, $3, $4 # CHECK: dpau.h.qbl $ac1, $3, $4 # encoding: [0x00,0x83,0x60,0xbc]
dpau.h.qbr $ac2, $20, $21 # CHECK: dpau.h.qbr $ac2, $20, $21 # encoding: [0x02,0xb4,0xb0,0xbc]
absq_s.ph $3, $4 # CHECK: absq_s.ph $3, $4 # encoding: [0x00,0x64,0x11,0x3c]
absq_s.w $3, $4 # CHECK: absq_s.w $3, $4 # encoding: [0x00,0x64,0x21,0x3c]
insv $3, $4 # CHECK: insv $3, $4 # encoding: [0x00,0x64,0x41,0x3c]
madd $ac1, $6, $7 # CHECK: madd $ac1, $6, $7 # encoding: [0x00,0xe6,0x4a,0xbc]
maddu $ac0, $8, $9 # CHECK: maddu $ac0, $8, $9 # encoding: [0x01,0x28,0x1a,0xbc]
msub $ac3, $10, $11 # CHECK: msub $ac3, $10, $11 # encoding: [0x01,0x6a,0xea,0xbc]
msubu $ac2, $12, $13 # CHECK: msubu $ac2, $12, $13 # encoding: [0x01,0xac,0xba,0xbc]
mult $ac3, $2, $3 # CHECK: mult $ac3, $2, $3 # encoding: [0x00,0x62,0xcc,0xbc]
multu $ac2, $4, $5 # CHECK: multu $ac2, $4, $5 # encoding: [0x00,0xa4,0x9c,0xbc]

1
llvm/test/MC/Mips/micromips-dspr2/valid.s
View File

@ -1,6 +1,7 @@
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips -mattr=+dspr2 | FileCheck %s
.set noat
absq_s.qb $3, $4 # CHECK: absq_s.qb $3, $4 # encoding: [0x00,0x64,0x01,0x3c]
dpa.w.ph $ac0, $3, $2 # CHECK: dpa.w.ph $ac0, $3, $2 # encoding: [0x00,0x43,0x00,0xbc]
dpaqx_s.w.ph $ac3, $12, $7 # CHECK: dpaqx_s.w.ph $ac3, $12, $7 # encoding: [0x00,0xec,0xe2,0xbc]
dpaqx_sa.w.ph $ac0, $5, $6 # CHECK: dpaqx_sa.w.ph $ac0, $5, $6 # encoding: [0x00,0xc5,0x32,0xbc]