forked from OSchip/llvm-project
[RISCV] Optimize vfmv.s.f intrinsic with scalar 0.0 to vmv.s.x with x0.
We already do this for RISCVISD::VFMV_S_F_VL and the vfmv.v.f intrinsic. Reviewed By: kito-cheng Differential Revision: https://reviews.llvm.org/D121429
This commit is contained in:
Craig Topper
parent
f2da8f5e4f
commit
d0969e485c
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@ -5413,6 +5413,11 @@ foreach fvti = AllFloatVectors in {
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(fvti.Vector $rs1),
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(fvti.Scalar fvti.ScalarRegClass:$rs2),
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GPR:$vl, fvti.Log2SEW)>;
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def : Pat<(fvti.Vector (int_riscv_vfmv_s_f (fvti.Vector fvti.RegClass:$rs1),
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(fvti.Scalar (fpimm0)), VLOpFrag)),
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(!cast<Instruction>("PseudoVMV_S_X_" # fvti.LMul.MX)
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(fvti.Vector $rs1), X0, GPR:$vl, fvti.Log2SEW)>;
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}
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} // Predicates = [HasVInstructionsAnyF]
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@ -198,3 +198,168 @@ entry:
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%a = call <vscale x 8 x double> @llvm.riscv.vfmv.s.f.nxv8f64(<vscale x 8 x double> %0, double %1, iXLen %2)
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ret <vscale x 8 x double> %a
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}
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define <vscale x 1 x half> @intrinsic_vfmv.s.f_f_zero_nxv1f16(<vscale x 1 x half> %0, iXLen %1) nounwind {
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; CHECK-LABEL: intrinsic_vfmv.s.f_f_zero_nxv1f16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
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; CHECK-NEXT: vmv.s.x v8, zero
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 1 x half> @llvm.riscv.vfmv.s.f.nxv1f16(<vscale x 1 x half> %0, half 0.0, iXLen %1)
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ret <vscale x 1 x half> %a
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}
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define <vscale x 2 x half> @intrinsic_vfmv.s.f_f_zero_nxv2f16(<vscale x 2 x half> %0, iXLen %1) nounwind {
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; CHECK-LABEL: intrinsic_vfmv.s.f_f_zero_nxv2f16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
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; CHECK-NEXT: vmv.s.x v8, zero
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 2 x half> @llvm.riscv.vfmv.s.f.nxv2f16(<vscale x 2 x half> %0, half 0.0, iXLen %1)
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ret <vscale x 2 x half> %a
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}
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define <vscale x 4 x half> @intrinsic_vfmv.s.f_f_zero_nxv4f16(<vscale x 4 x half> %0, iXLen %1) nounwind {
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; CHECK-LABEL: intrinsic_vfmv.s.f_f_zero_nxv4f16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
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; CHECK-NEXT: vmv.s.x v8, zero
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 4 x half> @llvm.riscv.vfmv.s.f.nxv4f16(<vscale x 4 x half> %0, half 0.0, iXLen %1)
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ret <vscale x 4 x half> %a
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}
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define <vscale x 8 x half> @intrinsic_vfmv.s.f_f_zero_nxv8f16(<vscale x 8 x half> %0, iXLen %1) nounwind {
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; CHECK-LABEL: intrinsic_vfmv.s.f_f_zero_nxv8f16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
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; CHECK-NEXT: vmv.s.x v8, zero
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 8 x half> @llvm.riscv.vfmv.s.f.nxv8f16(<vscale x 8 x half> %0, half 0.0, iXLen %1)
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ret <vscale x 8 x half> %a
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}
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define <vscale x 16 x half> @intrinsic_vfmv.s.f_f_zero_nxv16f16(<vscale x 16 x half> %0, iXLen %1) nounwind {
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; CHECK-LABEL: intrinsic_vfmv.s.f_f_zero_nxv16f16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
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; CHECK-NEXT: vmv.s.x v8, zero
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 16 x half> @llvm.riscv.vfmv.s.f.nxv16f16(<vscale x 16 x half> %0, half 0.0, iXLen %1)
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ret <vscale x 16 x half> %a
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}
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define <vscale x 32 x half> @intrinsic_vfmv.s.f_f_zero_nxv32f16(<vscale x 32 x half> %0, iXLen %1) nounwind {
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; CHECK-LABEL: intrinsic_vfmv.s.f_f_zero_nxv32f16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, mu
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; CHECK-NEXT: vmv.s.x v8, zero
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 32 x half> @llvm.riscv.vfmv.s.f.nxv32f16(<vscale x 32 x half> %0, half 0.0, iXLen %1)
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ret <vscale x 32 x half> %a
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}
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define <vscale x 1 x float> @intrinsic_vfmv.s.f_f_zero_nxv1f32(<vscale x 1 x float> %0, iXLen %1) nounwind {
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; CHECK-LABEL: intrinsic_vfmv.s.f_f_zero_nxv1f32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
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; CHECK-NEXT: vmv.s.x v8, zero
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 1 x float> @llvm.riscv.vfmv.s.f.nxv1f32(<vscale x 1 x float> %0, float 0.0, iXLen %1)
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ret <vscale x 1 x float> %a
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}
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define <vscale x 2 x float> @intrinsic_vfmv.s.f_f_zero_nxv2f32(<vscale x 2 x float> %0, iXLen %1) nounwind {
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; CHECK-LABEL: intrinsic_vfmv.s.f_f_zero_nxv2f32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
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; CHECK-NEXT: vmv.s.x v8, zero
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 2 x float> @llvm.riscv.vfmv.s.f.nxv2f32(<vscale x 2 x float> %0, float 0.0, iXLen %1)
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ret <vscale x 2 x float> %a
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}
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define <vscale x 4 x float> @intrinsic_vfmv.s.f_f_zero_nxv4f32(<vscale x 4 x float> %0, iXLen %1) nounwind {
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; CHECK-LABEL: intrinsic_vfmv.s.f_f_zero_nxv4f32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
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; CHECK-NEXT: vmv.s.x v8, zero
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 4 x float> @llvm.riscv.vfmv.s.f.nxv4f32(<vscale x 4 x float> %0, float 0.0, iXLen %1)
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ret <vscale x 4 x float> %a
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}
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define <vscale x 8 x float> @intrinsic_vfmv.s.f_f_zero_nxv8f32(<vscale x 8 x float> %0, iXLen %1) nounwind {
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; CHECK-LABEL: intrinsic_vfmv.s.f_f_zero_nxv8f32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
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; CHECK-NEXT: vmv.s.x v8, zero
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 8 x float> @llvm.riscv.vfmv.s.f.nxv8f32(<vscale x 8 x float> %0, float 0.0, iXLen %1)
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ret <vscale x 8 x float> %a
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}
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define <vscale x 16 x float> @intrinsic_vfmv.s.f_f_zero_nxv16f32(<vscale x 16 x float> %0, iXLen %1) nounwind {
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; CHECK-LABEL: intrinsic_vfmv.s.f_f_zero_nxv16f32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a0, e32, m8, tu, mu
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; CHECK-NEXT: vmv.s.x v8, zero
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 16 x float> @llvm.riscv.vfmv.s.f.nxv16f32(<vscale x 16 x float> %0, float 0.0, iXLen %1)
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ret <vscale x 16 x float> %a
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}
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define <vscale x 1 x double> @intrinsic_vfmv.s.f_f_zero_nxv1f64(<vscale x 1 x double> %0, iXLen %1) nounwind {
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; CHECK-LABEL: intrinsic_vfmv.s.f_f_zero_nxv1f64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
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; CHECK-NEXT: vmv.s.x v8, zero
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 1 x double> @llvm.riscv.vfmv.s.f.nxv1f64(<vscale x 1 x double> %0, double 0.0, iXLen %1)
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ret <vscale x 1 x double> %a
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}
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define <vscale x 2 x double> @intrinsic_vfmv.s.f_f_zero_nxv2f64(<vscale x 2 x double> %0, iXLen %1) nounwind {
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; CHECK-LABEL: intrinsic_vfmv.s.f_f_zero_nxv2f64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
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; CHECK-NEXT: vmv.s.x v8, zero
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 2 x double> @llvm.riscv.vfmv.s.f.nxv2f64(<vscale x 2 x double> %0, double 0.0, iXLen %1)
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ret <vscale x 2 x double> %a
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}
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define <vscale x 4 x double> @intrinsic_vfmv.s.f_f_zero_nxv4f64(<vscale x 4 x double> %0, iXLen %1) nounwind {
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; CHECK-LABEL: intrinsic_vfmv.s.f_f_zero_nxv4f64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
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; CHECK-NEXT: vmv.s.x v8, zero
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 4 x double> @llvm.riscv.vfmv.s.f.nxv4f64(<vscale x 4 x double> %0, double 0.0, iXLen %1)
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ret <vscale x 4 x double> %a
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}
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define <vscale x 8 x double> @intrinsic_vfmv.s.f_f_zero_nxv8f64(<vscale x 8 x double> %0, iXLen %1) nounwind {
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; CHECK-LABEL: intrinsic_vfmv.s.f_f_zero_nxv8f64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: vsetvli zero, a0, e64, m8, tu, mu
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; CHECK-NEXT: vmv.s.x v8, zero
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; CHECK-NEXT: ret
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entry:
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%a = call <vscale x 8 x double> @llvm.riscv.vfmv.s.f.nxv8f64(<vscale x 8 x double> %0, double 0.0, iXLen %1)
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ret <vscale x 8 x double> %a
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}
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