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[X86] Add SERIALIZE instruction. 

Summary: For more details about this instruction, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference

Reviewers: craig.topper, RKSimon, LuoYuanke

Reviewed By: craig.topper

Subscribers: mgorny, hiraditya, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D77193
This commit is contained in:
WangTianQing 2020-04-02 16:15:34 +08:00 committed by Xiang1 Zhang
parent 9f92d4612f
commit d08fadd662
24 changed files with 144 additions and 0 deletions
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2
clang/docs/ClangCommandLineReference.rst
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@ -3145,6 +3145,8 @@ X86
.. option:: -msahf, -mno-sahf
.. option:: -mserialize, -mno-serialize
.. option:: -msgx, -mno-sgx
.. option:: -msha, -mno-sha

3
clang/include/clang/Basic/BuiltinsX86.def
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@ -1900,6 +1900,9 @@ TARGET_BUILTIN(__builtin_ia32_invpcid, "vUiv*", "nc", "invpcid")
TARGET_BUILTIN(__builtin_ia32_enqcmd, "Ucv*vC*", "n", "enqcmd")
TARGET_BUILTIN(__builtin_ia32_enqcmds, "Ucv*vC*", "n", "enqcmd")
// SERIALIZE
TARGET_BUILTIN(__builtin_ia32_serialize, "v", "n", "serialize")
// MSVC
TARGET_HEADER_BUILTIN(_BitScanForward, "UcUNi*UNi", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
TARGET_HEADER_BUILTIN(_BitScanReverse, "UcUNi*UNi", "nh", "intrin.h", ALL_MS_LANGUAGES, "")

2
clang/include/clang/Driver/Options.td
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@ -3218,6 +3218,8 @@ def mrdseed : Flag<["-"], "mrdseed">, Group<m_x86_Features_Group>;
def mno_rdseed : Flag<["-"], "mno-rdseed">, Group<m_x86_Features_Group>;
def msahf : Flag<["-"], "msahf">, Group<m_x86_Features_Group>;
def mno_sahf : Flag<["-"], "mno-sahf">, Group<m_x86_Features_Group>;
def mserialize : Flag<["-"], "mserialize">, Group<m_x86_Features_Group>;
def mno_serialize : Flag<["-"], "mno-serialize">, Group<m_x86_Features_Group>;
def msgx : Flag<["-"], "msgx">, Group<m_x86_Features_Group>;
def mno_sgx : Flag<["-"], "mno-sgx">, Group<m_x86_Features_Group>;
def msha : Flag<["-"], "msha">, Group<m_x86_Features_Group>;

6
clang/lib/Basic/Targets/X86.cpp
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@ -857,6 +857,8 @@ bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
HasINVPCID = true;
} else if (Feature == "+enqcmd") {
HasENQCMD = true;
} else if (Feature == "+serialize") {
HasSERIALIZE = true;
}
X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
@ -1247,6 +1249,8 @@ void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
Builder.defineMacro("__INVPCID__");
if (HasENQCMD)
Builder.defineMacro("__ENQCMD__");
if (HasSERIALIZE)
Builder.defineMacro("__SERIALIZE__");
// Each case falls through to the previous one here.
switch (SSELevel) {
@ -1390,6 +1394,7 @@ bool X86TargetInfo::isValidFeatureName(StringRef Name) const {
.Case("rdseed", true)
.Case("rtm", true)
.Case("sahf", true)
.Case("serialize", true)
.Case("sgx", true)
.Case("sha", true)
.Case("shstk", true)
@ -1474,6 +1479,7 @@ bool X86TargetInfo::hasFeature(StringRef Feature) const {
.Case("retpoline-external-thunk", HasRetpolineExternalThunk)
.Case("rtm", HasRTM)
.Case("sahf", HasLAHFSAHF)
.Case("serialize", HasSERIALIZE)
.Case("sgx", HasSGX)
.Case("sha", HasSHA)
.Case("shstk", HasSHSTK)

1
clang/lib/Basic/Targets/X86.h
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@ -124,6 +124,7 @@ class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public TargetInfo {
bool HasPTWRITE = false;
bool HasINVPCID = false;
bool HasENQCMD = false;
bool HasSERIALIZE = false;
protected:
/// Enumeration of all of the X86 CPUs supported by Clang.

1
clang/lib/Headers/CMakeLists.txt
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@ -88,6 +88,7 @@ set(files
ptwriteintrin.h
rdseedintrin.h
rtmintrin.h
serializeintrin.h
sgxintrin.h
s390intrin.h
shaintrin.h

1
clang/lib/Headers/cpuid.h
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@ -182,6 +182,7 @@
/* Features in %edx for leaf 7 sub-leaf 0 */
#define bit_AVX5124VNNIW 0x00000004
#define bit_AVX5124FMAPS 0x00000008
#define bit_SERIALIZE 0x00004000
#define bit_PCONFIG 0x00040000
#define bit_IBT 0x00100000

4
clang/lib/Headers/immintrin.h
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@ -434,6 +434,10 @@ _storebe_i64(void * __P, long long __D) {
#include <enqcmdintrin.h>
#endif
#if !defined(_MSC_VER) || __has_feature(modules) || defined(__SERIALIZE__)
#include <serializeintrin.h>
#endif
#if defined(_MSC_VER) && __has_extension(gnu_asm)
/* Define the default attributes for these intrinsics */
#define __DEFAULT_FN_ATTRS __attribute__((__always_inline__, __nodebug__))

30
clang/lib/Headers/serializeintrin.h Normal file
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@ -0,0 +1,30 @@
/*===--------------- serializeintrin.h - serialize intrinsics --------------===
*
* Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
* See https://llvm.org/LICENSE.txt for license information.
* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
*
*===-----------------------------------------------------------------------===
*/
#ifndef __IMMINTRIN_H
#error "Never use <serializeintrin.h> directly; include <immintrin.h> instead."
#endif
#ifndef __SERIALIZEINTRIN_H
#define __SERIALIZEINTRIN_H
/// Serialize instruction fetch and execution.
///
/// \headerfile <x86intrin.h>
///
/// This intrinsic corresponds to the <c> SERIALIZE </c> instruction.
///
static __inline__ void
__attribute__((__always_inline__, __nodebug__, __target__("serialize")))
_serialize (void)
{
__builtin_ia32_serialize ();
}
#endif /* __SERIALIZEINTRIN_H */

11
clang/test/CodeGen/x86-serialize-intrin.c Normal file
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@ -0,0 +1,11 @@
// RUN: %clang_cc1 %s -ffreestanding -triple x86_64-unknown-unknown -target-feature +serialize -emit-llvm -o - | FileCheck %s
// RUN: %clang_cc1 %s -ffreestanding -triple i386-unknown-unknown -target-feature +serialize -emit-llvm -o - | FileCheck %s
#include <immintrin.h>
void test_serialize(void)
{
// CHECK-LABEL: test_serialize
// CHECK: call void @llvm.x86.serialize()
_serialize();
}

5
clang/test/Driver/x86-target-features.c
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@ -198,3 +198,8 @@
// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-vzeroupper %s -### -o %t.o 2>&1 | FileCheck --check-prefix=NO-VZEROUPPER %s
// VZEROUPPER: "-target-feature" "+vzeroupper"
// NO-VZEROUPPER: "-target-feature" "-vzeroupper"
// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mserialize %s -### -o %t.o 2>&1 | FileCheck -check-prefix=SERIALIZE %s
// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-serialize %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-SERIALIZE %s
// SERIALIZE: "-target-feature" "+serialize"
// NO-SERIALIZE: "-target-feature" "-serialize"

8
clang/test/Preprocessor/x86_target_features.c
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@ -483,3 +483,11 @@
// RUN: %clang -target i386-unknown-unknown -march=atom -mno-enqcmd -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=NOENQCMD %s
// NOENQCMD-NOT: #define __ENQCMD__ 1
// RUN: %clang -target i386-unknown-unknown -march=atom -mserialize -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=SERIALIZE %s
// SERIALIZE: #define __SERIALIZE__ 1
// RUN: %clang -target i386-unknown-unknown -march=atom -mno-serialize -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=NOSERIALIZE %s
// NOSERIALIZE-NOT: #define __SERIALIZE__ 1

8
llvm/include/llvm/IR/IntrinsicsX86.td
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@ -4930,3 +4930,11 @@ let TargetPrefix = "x86" in {
def int_x86_enqcmds : GCCBuiltin<"__builtin_ia32_enqcmds">,
Intrinsic<[llvm_i8_ty], [llvm_ptr_ty, llvm_ptr_ty], []>;
}
//===----------------------------------------------------------------------===//
// SERIALIZE - Serialize instruction fetch and execution
let TargetPrefix = "x86" in {
def int_x86_serialize : GCCBuiltin<"__builtin_ia32_serialize">,
Intrinsic<[], [], []>;
}

1
llvm/lib/Support/Host.cpp
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@ -1477,6 +1477,7 @@ bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
Features["movdir64b"] = HasLeaf7 && ((ECX >> 28) & 1);
Features["enqcmd"] = HasLeaf7 && ((ECX >> 29) & 1);
Features["serialize"] = HasLeaf7 && ((EDX >> 14) & 1);
// There are two CPUID leafs which information associated with the pconfig
// instruction:
// EAX=0x7, ECX=0x0 indicates the availability of the instruction (via the 18th

2
llvm/lib/Target/X86/X86.td
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@ -273,6 +273,8 @@ def FeatureWAITPKG : SubtargetFeature<"waitpkg", "HasWAITPKG", "true",
"Wait and pause enhancements">;
def FeatureENQCMD : SubtargetFeature<"enqcmd", "HasENQCMD", "true",
"Has ENQCMD instructions">;
def FeatureSERIALIZE : SubtargetFeature<"serialize", "HasSERIALIZE", "true",
"Has serialize instruction">;
// On some processors, instructions that implicitly take two memory operands are
// slow. In practice, this means that CALL, PUSH, and POP with memory operands
// should be avoided in favor of a MOV + register CALL/PUSH/POP.

8
llvm/lib/Target/X86/X86InstrInfo.td
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@ -955,6 +955,7 @@ def HasCmpxchg8b : Predicate<"Subtarget->hasCmpxchg8b()">;
def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
def HasPCONFIG : Predicate<"Subtarget->hasPCONFIG()">;
def HasENQCMD : Predicate<"Subtarget->hasENQCMD()">;
def HasSERIALIZE : Predicate<"Subtarget->hasSERIALIZE()">;
def Not64BitMode : Predicate<"!Subtarget->is64Bit()">,
AssemblerPredicate<(all_of (not Mode64Bit)), "Not 64-bit mode">;
def In64BitMode : Predicate<"Subtarget->is64Bit()">,
@ -2861,6 +2862,13 @@ let SchedRW = [WriteLoad] in {
def : InstAlias<"clzero\t{%eax|eax}", (CLZERO32r)>, Requires<[Not64BitMode]>;
def : InstAlias<"clzero\t{%rax|rax}", (CLZERO64r)>, Requires<[In64BitMode]>;
//===----------------------------------------------------------------------===//
// SERIALIZE Instruction
//
def SERIALIZE : I<0x01, MRM_E8, (outs), (ins), "serialize",
[(int_x86_serialize)]>, PS,
Requires<[HasSERIALIZE]>;
//===----------------------------------------------------------------------===//
// Pattern fragments to auto generate TBM instructions.
//===----------------------------------------------------------------------===//

4
llvm/lib/Target/X86/X86Subtarget.h
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@ -397,6 +397,9 @@ protected:
/// Processor supports PCONFIG instruction
bool HasPCONFIG = false;
/// Processor supports SERIALIZE instruction
bool HasSERIALIZE = false;
/// Processor has a single uop BEXTR implementation.
bool HasFastBEXTR = false;
@ -706,6 +709,7 @@ public:
bool threewayBranchProfitable() const { return ThreewayBranchProfitable; }
bool hasINVPCID() const { return HasINVPCID; }
bool hasENQCMD() const { return HasENQCMD; }
bool hasSERIALIZE() const { return HasSERIALIZE; }
bool useRetpolineIndirectCalls() const { return UseRetpolineIndirectCalls; }
bool useRetpolineIndirectBranches() const {
return UseRetpolineIndirectBranches;

26
llvm/test/CodeGen/X86/serialize-intrinsic.ll Normal file
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@ -0,0 +1,26 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+serialize | FileCheck %s --check-prefix=X86_64
; RUN: llc < %s -mtriple=i386-unknown-unknown -mattr=+serialize | FileCheck %s --check-prefix=X86
; RUN: llc < %s -mtriple=x86_64-linux-gnux32 -mattr=+serialize | FileCheck %s --check-prefix=X32
define void @test_serialize() {
; X86_64-LABEL: test_serialize:
; X86_64: # %bb.0: # %entry
; X86_64-NEXT: serialize
; X86_64-NEXT: retq
;
; X86-LABEL: test_serialize:
; X86: # %bb.0: # %entry
; X86-NEXT: serialize
; X86-NEXT: retl
;
; X32-LABEL: test_serialize:
; X32: # %bb.0: # %entry
; X32-NEXT: serialize
; X32-NEXT: retq
entry:
call void @llvm.x86.serialize()
ret void
}
declare void @llvm.x86.serialize()

3
llvm/test/MC/Disassembler/X86/x86-16.txt
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@ -836,3 +836,6 @@
# CHECK: enqcmds (%edi), %edi
0x67,0xf3,0x0f,0x38,0xf8,0x3f
# CHECK: serialize
0x0f 0x01 0xe8

3
llvm/test/MC/Disassembler/X86/x86-32.txt
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@ -943,3 +943,6 @@
# CHECK: enqcmds 8128(%bx,%di), %ax
0x67,0xf3,0x0f,0x38,0xf8,0x81,0xc0,0x1f
# CHECK: serialize
0x0f 0x01 0xe8

3
llvm/test/MC/Disassembler/X86/x86-64.txt
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@ -691,3 +691,6 @@
# CHECK: enqcmds 485498096, %rax
0xf3,0x0f,0x38,0xf8,0x04,0x25,0xf0,0x1c,0xf0,0x1c
# CHECK: serialize
0x0f 0x01 0xe8

4
llvm/test/MC/X86/x86-16.s
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@ -1029,3 +1029,7 @@ enqcmd (%edi), %edi
// CHECK: enqcmds (%edi), %edi
// CHECK: encoding: [0x67,0xf3,0x0f,0x38,0xf8,0x3f]
enqcmds (%edi), %edi
// CHECK: serialize
// CHECK: encoding: [0x0f,0x01,0xe8]
serialize

4
llvm/test/MC/X86/x86-32-coverage.s
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@ -10876,3 +10876,7 @@ enqcmds (%bx,%di), %di
// CHECK: enqcmds 8128(%bx,%di), %ax
// CHECK: encoding: [0x67,0xf3,0x0f,0x38,0xf8,0x81,0xc0,0x1f]
enqcmds 8128(%bx,%di), %ax
// CHECK: serialize
// CHECK: encoding: [0x0f,0x01,0xe8]
serialize

4
llvm/test/MC/X86/x86-64.s
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@ -1877,3 +1877,7 @@ enqcmds -8192(%rdx), %rbx
// CHECK: enqcmds 485498096, %rax
// CHECK: encoding: [0xf3,0x0f,0x38,0xf8,0x04,0x25,0xf0,0x1c,0xf0,0x1c]
enqcmds 485498096, %rax
// CHECK: serialize
// CHECK: encoding: [0x0f,0x01,0xe8]
serialize